Mirrors/VILLASnode
1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-09 00:00:00 +01:00
Code Issues Releases Wiki Activity

tests: let them fail if no Fifo or Timer is found

Browse source
This commit is contained in:
Daniel Krebs 2018-02-13 14:12:28 +01:00 • committed by Steffen Vogel
parent ef5f6fa3a8
commit acf273e406
3 changed files with 17 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
fpga/tests/fifo.cpp
View file

@ -34,6 +34,7 @@ Test(fpga, fifo, .description = "FIFO")
{
ssize_t len;
char src[255], dst[255];
size_t count = 0;
auto logger = loggerGetOrCreate("unittest:fifo");
@ -46,12 +47,14 @@ Test(fpga, fifo, .description = "FIFO")
auto fifo = reinterpret_cast<villas::fpga::ip::Fifo&>(*ip);
if(not fifo.loopbackPossible()) {
logger->info("Loopback test not possible for {}", *ip);
if(not fifo.connectLoopback()) {
continue;
}
if(not fifo.connectLoopback()) {
count++;
if(not fifo.loopbackPossible()) {
logger->info("Loopback test not possible for {}", *ip);
continue;
}
@ -80,4 +83,6 @@ Test(fpga, fifo, .description = "FIFO")
logger->info(TXT_GREEN("Passed"));
}
cr_assert(count > 0, "No fifo found");
}

4
fpga/tests/graph.cpp
View file

@ -44,6 +44,8 @@ Test(graph, basic, .description = "DirectedGraph")
g.dump();
cr_assert(g.getVertexCount() == 2);
cr_assert(g.vertexGetEdges(v2id).size() == 0);
logger->info(TXT_GREEN("Passed"));
}
Test(graph, path, .description = "Find path")
@ -108,6 +110,8 @@ Test(graph, path, .description = "Find path")
for(auto& edge : path4) {
logger->info(" -> edge {}", edge);
}
logger->info(TXT_GREEN("Passed"));
}
Test(graph, memory_manager, .description = "Global Memory Manager")

6
fpga/tests/timer.cpp
View file

@ -34,6 +34,8 @@ Test(fpga, timer, .description = "Timer Counter")
{
auto logger = loggerGetOrCreate("unittest:timer");
size_t count = 0;
for(auto& ip : state.cards.front()->ips) {
// skip non-timer IPs
if(*ip != villas::fpga::Vlnv("xilinx.com:ip:axi_timer:")) {
@ -42,6 +44,8 @@ Test(fpga, timer, .description = "Timer Counter")
logger->info("Testing {}", *ip);
count++;
auto timer = reinterpret_cast<villas::fpga::ip::Timer&>(*ip);
logger->info("Test simple waiting");
@ -68,5 +72,5 @@ Test(fpga, timer, .description = "Timer Counter")
logger->info(TXT_GREEN("Passed"));
}
return;
cr_assert(count > 0, "No timer found");
}