mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
add json smmu
Signed-off-by: IgnoreWarnings <pascal.bauer@rwth-aachen.de>
This commit is contained in:
IgnoreWarnings
parent
f25e1dd689
commit
b8ae1f91e7
1 changed files with 509 additions and 0 deletions
509
etc/fpga/zcu106-smmu/zcu106-smmu.json
Normal file
509
etc/fpga/zcu106-smmu/zcu106-smmu.json
Normal file
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@ -0,0 +1,509 @@
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{
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"axi_dma_0": {
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"vlnv": "xilinx.com:ip:axi_dma:7.1",
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"parameters": {
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"c_s_axi_lite_addr_width": 10,
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"c_s_axi_lite_data_width": 32,
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"c_dlytmr_resolution": 125,
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"c_prmry_is_aclk_async": 0,
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"c_enable_multi_channel": 0,
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"c_num_mm2s_channels": 1,
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"c_num_s2mm_channels": 1,
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"c_include_sg": 1,
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"c_sg_include_stscntrl_strm": 0,
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"c_sg_use_stsapp_length": 0,
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"c_sg_length_width": 23,
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"c_m_axi_sg_addr_width": 64,
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"c_m_axi_sg_data_width": 32,
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"c_m_axis_mm2s_cntrl_tdata_width": 32,
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"c_s_axis_s2mm_sts_tdata_width": 32,
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"c_micro_dma": 0,
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"c_include_mm2s": 1,
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"c_include_mm2s_sf": 1,
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"c_mm2s_burst_size": 16,
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"c_m_axi_mm2s_addr_width": 64,
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"c_m_axi_mm2s_data_width": 128,
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"c_m_axis_mm2s_tdata_width": 128,
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"c_include_mm2s_dre": 0,
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"c_include_s2mm": 1,
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"c_include_s2mm_sf": 1,
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"c_s2mm_burst_size": 16,
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"c_m_axi_s2mm_addr_width": 64,
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"c_m_axi_s2mm_data_width": 128,
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"c_s_axis_s2mm_tdata_width": 128,
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"c_include_s2mm_dre": 0,
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"c_increase_throughput": 0,
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"c_family": "zynquplus",
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"component_name": "design_1_axi_dma_0_0",
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"c_addr_width": 64,
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"c_single_interface": 0,
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"edk_iptype": "PERIPHERAL",
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"c_baseaddr": 2684354560,
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"c_highaddr": 2684420095
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},
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"memory-view": {
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"M_AXI_SG": {
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"zynq_ultra_ps_e_0": {
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"HPC1_DDR_LOW": {
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"baseaddr": 0,
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"highaddr": 2147483647,
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"size": 2147483648
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},
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"HPC1_QSPI": {
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"baseaddr": 3221225472,
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"highaddr": 3758096383,
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"size": 536870912
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},
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"HPC1_DDR_HIGH": {
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"baseaddr": 34359738368,
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"highaddr": 68719476735,
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"size": 34359738368
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}
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}
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},
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"M_AXI_MM2S": {
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"zynq_ultra_ps_e_0": {
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"HPC0_DDR_LOW": {
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"baseaddr": 0,
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"highaddr": 2147483647,
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"size": 2147483648
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},
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"HPC0_QSPI": {
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"baseaddr": 3221225472,
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"highaddr": 3758096383,
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"size": 536870912
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},
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"HPC0_DDR_HIGH": {
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"baseaddr": 34359738368,
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"highaddr": 68719476735,
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"size": 34359738368
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}
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}
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},
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"M_AXI_S2MM": {
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"zynq_ultra_ps_e_0": {
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"HPC0_DDR_LOW": {
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"baseaddr": 0,
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"highaddr": 2147483647,
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"size": 2147483648
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},
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"HPC0_QSPI": {
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"baseaddr": 3221225472,
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"highaddr": 3758096383,
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"size": 536870912
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},
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"HPC0_DDR_HIGH": {
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"baseaddr": 34359738368,
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"highaddr": 68719476735,
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"size": 34359738368
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}
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}
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}
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},
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"ports": [
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{
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"role": "master",
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"target": "axis_interconnect_0_xbar:S00_AXIS",
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"name": "MM2S"
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},
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{
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"role": "slave",
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"target": "axis_interconnect_0_xbar:M00_AXIS",
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"name": "S2MM"
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}
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]
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},
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"axis_interconnect_0_xbar": {
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"vlnv": "xilinx.com:ip:axis_switch:1.1",
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"parameters": {
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"c_family": "zynquplus",
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"c_num_si_slots": 2,
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"c_log_si_slots": 1,
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"c_num_mi_slots": 2,
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"c_axis_tdata_width": 128,
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"c_axis_tid_width": 1,
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"c_axis_tdest_width": 1,
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"c_axis_tuser_width": 1,
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"c_axis_signal_set": 91,
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"c_arb_on_max_xfers": 1,
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"c_arb_on_num_cycles": 0,
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"c_arb_on_tlast": 0,
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"c_include_arbiter": 1,
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"c_arb_algorithm": 0,
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"c_output_reg": 0,
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"c_decoder_reg": 1,
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"c_m_axis_connectivity_array": 15,
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"c_m_axis_basetdest_array": 2,
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"c_m_axis_hightdest_array": 2,
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"c_routing_mode": 1,
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"c_s_axi_ctrl_addr_width": 7,
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"c_s_axi_ctrl_data_width": 32,
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"c_common_clock": 0,
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"num_si": 2,
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"num_mi": 2,
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"routing_mode": 1,
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"has_tready": 1,
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"tdata_num_bytes": 16,
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"has_tstrb": 0,
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"has_tkeep": 1,
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"has_tlast": 1,
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"tid_width": 0,
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"tdest_width": 1,
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"tuser_width": 0,
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"has_aclken": 0,
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"arb_on_max_xfers": 1,
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"arb_on_num_cycles": 0,
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"arb_on_tlast": 0,
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"arb_algorithm": 0,
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"decoder_reg": 1,
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"output_reg": 0,
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"common_clock": 0,
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"m00_axis_basetdest": 0,
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"m01_axis_basetdest": 1,
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"m02_axis_basetdest": 2,
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"m03_axis_basetdest": 3,
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"m04_axis_basetdest": 4,
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"m05_axis_basetdest": 5,
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"m06_axis_basetdest": 6,
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"m07_axis_basetdest": 7,
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"m08_axis_basetdest": 8,
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"m09_axis_basetdest": 9,
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"m10_axis_basetdest": 10,
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"m11_axis_basetdest": 11,
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"m12_axis_basetdest": 12,
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"m13_axis_basetdest": 13,
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"m14_axis_basetdest": 14,
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"m15_axis_basetdest": 15,
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"m00_axis_hightdest": 0,
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"m01_axis_hightdest": 1,
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"m02_axis_hightdest": 2,
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"m03_axis_hightdest": 3,
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"m04_axis_hightdest": 4,
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"m05_axis_hightdest": 5,
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"m06_axis_hightdest": 6,
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"m07_axis_hightdest": 7,
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"m08_axis_hightdest": 8,
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"m09_axis_hightdest": 9,
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"m10_axis_hightdest": 10,
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"m11_axis_hightdest": 11,
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"m12_axis_hightdest": 12,
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"m13_axis_hightdest": 13,
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"m14_axis_hightdest": 14,
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"m15_axis_hightdest": 15,
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"m00_s00_connectivity": 1,
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"m00_s01_connectivity": 1,
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"m00_s02_connectivity": 1,
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"m00_s03_connectivity": 1,
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"m00_s04_connectivity": 1,
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"m00_s05_connectivity": 1,
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"m00_s06_connectivity": 1,
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"m00_s07_connectivity": 1,
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"m00_s08_connectivity": 1,
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"m00_s09_connectivity": 1,
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"m00_s10_connectivity": 1,
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"m00_s11_connectivity": 1,
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"m00_s12_connectivity": 1,
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"m00_s13_connectivity": 1,
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"m00_s14_connectivity": 1,
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"m00_s15_connectivity": 1,
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"m01_s00_connectivity": 1,
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"m01_s01_connectivity": 1,
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"m01_s02_connectivity": 1,
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"m01_s03_connectivity": 1,
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"m01_s04_connectivity": 1,
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"m01_s05_connectivity": 1,
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"m01_s06_connectivity": 1,
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"m01_s07_connectivity": 1,
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"m01_s08_connectivity": 1,
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"m01_s09_connectivity": 1,
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"m01_s10_connectivity": 1,
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"m01_s11_connectivity": 1,
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"m01_s12_connectivity": 1,
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"m01_s13_connectivity": 1,
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"m01_s14_connectivity": 1,
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"m01_s15_connectivity": 1,
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"m02_s00_connectivity": 1,
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"m02_s01_connectivity": 1,
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"m02_s02_connectivity": 1,
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"m02_s03_connectivity": 1,
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"m02_s04_connectivity": 1,
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"m02_s05_connectivity": 1,
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"m02_s06_connectivity": 1,
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"m02_s07_connectivity": 1,
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"m02_s08_connectivity": 1,
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"m02_s09_connectivity": 1,
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"m02_s10_connectivity": 1,
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"m02_s11_connectivity": 1,
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"m02_s12_connectivity": 1,
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"m02_s13_connectivity": 1,
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"m02_s14_connectivity": 1,
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"m02_s15_connectivity": 1,
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"m03_s00_connectivity": 1,
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"m03_s01_connectivity": 1,
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"m03_s02_connectivity": 1,
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"m03_s03_connectivity": 1,
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"m03_s04_connectivity": 1,
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"m03_s05_connectivity": 1,
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"m03_s06_connectivity": 1,
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"m03_s07_connectivity": 1,
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"m03_s08_connectivity": 1,
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"m03_s09_connectivity": 1,
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"m03_s10_connectivity": 1,
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"m03_s11_connectivity": 1,
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"m03_s12_connectivity": 1,
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"m03_s13_connectivity": 1,
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"m03_s14_connectivity": 1,
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"m03_s15_connectivity": 1,
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"m04_s00_connectivity": 1,
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"m04_s01_connectivity": 1,
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"m04_s02_connectivity": 1,
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"m04_s03_connectivity": 1,
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"m04_s04_connectivity": 1,
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"m04_s05_connectivity": 1,
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"m04_s06_connectivity": 1,
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"m04_s07_connectivity": 1,
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"m04_s08_connectivity": 1,
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"m04_s09_connectivity": 1,
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"m04_s10_connectivity": 1,
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"m04_s11_connectivity": 1,
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"m04_s12_connectivity": 1,
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"m04_s13_connectivity": 1,
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"m04_s14_connectivity": 1,
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"m04_s15_connectivity": 1,
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"m05_s00_connectivity": 1,
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"m05_s01_connectivity": 1,
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"m05_s02_connectivity": 1,
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"m05_s03_connectivity": 1,
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"m05_s04_connectivity": 1,
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"m05_s05_connectivity": 1,
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"m05_s06_connectivity": 1,
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"m05_s07_connectivity": 1,
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"m05_s08_connectivity": 1,
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"m05_s09_connectivity": 1,
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"m05_s10_connectivity": 1,
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"m05_s11_connectivity": 1,
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"m05_s12_connectivity": 1,
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"m05_s13_connectivity": 1,
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"m05_s14_connectivity": 1,
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"m05_s15_connectivity": 1,
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"m06_s00_connectivity": 1,
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"m06_s01_connectivity": 1,
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"m06_s02_connectivity": 1,
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"m06_s03_connectivity": 1,
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"m06_s04_connectivity": 1,
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"m06_s05_connectivity": 1,
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"m06_s06_connectivity": 1,
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"m06_s07_connectivity": 1,
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"m06_s08_connectivity": 1,
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"m06_s09_connectivity": 1,
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"m06_s10_connectivity": 1,
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"m06_s11_connectivity": 1,
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"m06_s12_connectivity": 1,
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"m06_s13_connectivity": 1,
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"m06_s14_connectivity": 1,
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"m06_s15_connectivity": 1,
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"m07_s00_connectivity": 1,
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"m07_s01_connectivity": 1,
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"m07_s02_connectivity": 1,
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"m07_s03_connectivity": 1,
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"m07_s04_connectivity": 1,
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"m07_s05_connectivity": 1,
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"m07_s06_connectivity": 1,
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"m07_s07_connectivity": 1,
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"m07_s08_connectivity": 1,
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"m07_s09_connectivity": 1,
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"m07_s10_connectivity": 1,
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"m07_s11_connectivity": 1,
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"m07_s12_connectivity": 1,
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"m07_s13_connectivity": 1,
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"m07_s14_connectivity": 1,
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"m07_s15_connectivity": 1,
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"m08_s00_connectivity": 1,
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"m08_s01_connectivity": 1,
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"m08_s02_connectivity": 1,
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"m08_s03_connectivity": 1,
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"m08_s04_connectivity": 1,
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"m08_s05_connectivity": 1,
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"m08_s06_connectivity": 1,
|
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"m08_s07_connectivity": 1,
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"m08_s08_connectivity": 1,
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"m08_s09_connectivity": 1,
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"m08_s10_connectivity": 1,
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||||
"m08_s11_connectivity": 1,
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||||
"m08_s12_connectivity": 1,
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"m08_s13_connectivity": 1,
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||||
"m08_s14_connectivity": 1,
|
||||
"m08_s15_connectivity": 1,
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"m09_s00_connectivity": 1,
|
||||
"m09_s01_connectivity": 1,
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"m09_s02_connectivity": 1,
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"m09_s03_connectivity": 1,
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"m09_s04_connectivity": 1,
|
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"m09_s05_connectivity": 1,
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"m09_s06_connectivity": 1,
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"m09_s07_connectivity": 1,
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"m09_s08_connectivity": 1,
|
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"m09_s09_connectivity": 1,
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||||
"m09_s10_connectivity": 1,
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||||
"m09_s11_connectivity": 1,
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||||
"m09_s12_connectivity": 1,
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||||
"m09_s13_connectivity": 1,
|
||||
"m09_s14_connectivity": 1,
|
||||
"m09_s15_connectivity": 1,
|
||||
"m10_s00_connectivity": 1,
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||||
"m10_s01_connectivity": 1,
|
||||
"m10_s02_connectivity": 1,
|
||||
"m10_s03_connectivity": 1,
|
||||
"m10_s04_connectivity": 1,
|
||||
"m10_s05_connectivity": 1,
|
||||
"m10_s06_connectivity": 1,
|
||||
"m10_s07_connectivity": 1,
|
||||
"m10_s08_connectivity": 1,
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||||
"m10_s09_connectivity": 1,
|
||||
"m10_s10_connectivity": 1,
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"m10_s11_connectivity": 1,
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||||
"m10_s12_connectivity": 1,
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"m10_s13_connectivity": 1,
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"m10_s14_connectivity": 1,
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"m10_s15_connectivity": 1,
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"m11_s00_connectivity": 1,
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"m11_s01_connectivity": 1,
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"m11_s02_connectivity": 1,
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"m11_s03_connectivity": 1,
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"m11_s04_connectivity": 1,
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"m11_s05_connectivity": 1,
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"m11_s06_connectivity": 1,
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"m11_s07_connectivity": 1,
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"m11_s08_connectivity": 1,
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"m11_s09_connectivity": 1,
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"m11_s10_connectivity": 1,
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"m11_s11_connectivity": 1,
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"m11_s12_connectivity": 1,
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"m11_s13_connectivity": 1,
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"m11_s14_connectivity": 1,
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"m11_s15_connectivity": 1,
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||||
"m12_s00_connectivity": 1,
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"m12_s01_connectivity": 1,
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"m12_s02_connectivity": 1,
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"m12_s03_connectivity": 1,
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"m12_s04_connectivity": 1,
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"m12_s05_connectivity": 1,
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"m12_s06_connectivity": 1,
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"m12_s07_connectivity": 1,
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"m12_s08_connectivity": 1,
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||||
"m12_s09_connectivity": 1,
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"m12_s10_connectivity": 1,
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"m12_s11_connectivity": 1,
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"m12_s12_connectivity": 1,
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||||
"m12_s13_connectivity": 1,
|
||||
"m12_s14_connectivity": 1,
|
||||
"m12_s15_connectivity": 1,
|
||||
"m13_s00_connectivity": 1,
|
||||
"m13_s01_connectivity": 1,
|
||||
"m13_s02_connectivity": 1,
|
||||
"m13_s03_connectivity": 1,
|
||||
"m13_s04_connectivity": 1,
|
||||
"m13_s05_connectivity": 1,
|
||||
"m13_s06_connectivity": 1,
|
||||
"m13_s07_connectivity": 1,
|
||||
"m13_s08_connectivity": 1,
|
||||
"m13_s09_connectivity": 1,
|
||||
"m13_s10_connectivity": 1,
|
||||
"m13_s11_connectivity": 1,
|
||||
"m13_s12_connectivity": 1,
|
||||
"m13_s13_connectivity": 1,
|
||||
"m13_s14_connectivity": 1,
|
||||
"m13_s15_connectivity": 1,
|
||||
"m14_s00_connectivity": 1,
|
||||
"m14_s01_connectivity": 1,
|
||||
"m14_s02_connectivity": 1,
|
||||
"m14_s03_connectivity": 1,
|
||||
"m14_s04_connectivity": 1,
|
||||
"m14_s05_connectivity": 1,
|
||||
"m14_s06_connectivity": 1,
|
||||
"m14_s07_connectivity": 1,
|
||||
"m14_s08_connectivity": 1,
|
||||
"m14_s09_connectivity": 1,
|
||||
"m14_s10_connectivity": 1,
|
||||
"m14_s11_connectivity": 1,
|
||||
"m14_s12_connectivity": 1,
|
||||
"m14_s13_connectivity": 1,
|
||||
"m14_s14_connectivity": 1,
|
||||
"m14_s15_connectivity": 1,
|
||||
"m15_s00_connectivity": 1,
|
||||
"m15_s01_connectivity": 1,
|
||||
"m15_s02_connectivity": 1,
|
||||
"m15_s03_connectivity": 1,
|
||||
"m15_s04_connectivity": 1,
|
||||
"m15_s05_connectivity": 1,
|
||||
"m15_s06_connectivity": 1,
|
||||
"m15_s07_connectivity": 1,
|
||||
"m15_s08_connectivity": 1,
|
||||
"m15_s09_connectivity": 1,
|
||||
"m15_s10_connectivity": 1,
|
||||
"m15_s11_connectivity": 1,
|
||||
"m15_s12_connectivity": 1,
|
||||
"m15_s13_connectivity": 1,
|
||||
"m15_s14_connectivity": 1,
|
||||
"m15_s15_connectivity": 1,
|
||||
"component_name": "design_1_xbar_0",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 2684420096,
|
||||
"c_highaddr": 2684485631
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "axi_dma_0:MM2S",
|
||||
"name": "S00_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "master",
|
||||
"target": "axi_dma_0:S2MM",
|
||||
"name": "M00_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "master",
|
||||
"target": "axis_interconnect_0_xbar:S01_AXIS",
|
||||
"name": "M01_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "axis_interconnect_0_xbar:M01_AXIS",
|
||||
"name": "S01_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "axis_interconnect_0_xbar:M01_AXIS",
|
||||
"name": "S01_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "master",
|
||||
"target": "axis_interconnect_0_xbar:S01_AXIS",
|
||||
"name": "M01_AXIS"
|
||||
}
|
||||
],
|
||||
"num_ports": 2
|
||||
},
|
||||
"zynq_ultra_ps_e_0": {
|
||||
"vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.3",
|
||||
"memory-view": {
|
||||
"M_AXI_HPM0_FPD": {
|
||||
"axi_dma_0": {
|
||||
"Reg": {
|
||||
"baseaddr": 2684354560,
|
||||
"highaddr": 2684420095,
|
||||
"size": 65536
|
||||
}
|
||||
},
|
||||
"axis_interconnect_0_xbar": {
|
||||
"Reg": {
|
||||
"baseaddr": 2684420096,
|
||||
"highaddr": 2684485631,
|
||||
"size": 65536
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue