Mirrors/VILLASnode
1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-09 00:00:00 +01:00
Code Issues Releases Wiki Activity

hwdef-parse: count total switch ports and populate property

Browse source
This commit is contained in:
daniel-k 2018-01-23 14:41:31 +01:00
parent fb37253623
commit bbff2c9a88
1 changed files with 6 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
fpga/scripts/hwdef-parse.py
View file

@ -166,10 +166,13 @@ for mrange in mmap:
# find AXI-Stream switch port mapping
switch = root.find('.//MODULE[@MODTYPE="axis_switch"]')
busifs = switch.find('.//BUSINTERFACES')
switch_ports = 0
for busif in busifs:
if busif.get('VLNV') != 'xilinx.com:interface:axis:1.0':
continue
switch_ports += 1
busname = busif.get('BUSNAME')
name = busif.get('NAME')
type = busif.get('TYPE')
@ -193,6 +196,9 @@ for busif in busifs:
if busif_ep:
ports[-1]['name'] = sanitize_name(busif_ep.get('NAME'))
# set number of master/slave port pairs for switch
ips[switch.get('INSTANCE')]['num_ports'] = switch_ports / 2
# find Interrupt assignments
intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]')