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fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
parent
d99d0918ad
commit
ca03e1d406
4 changed files with 30 additions and 5 deletions
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@ -24,8 +24,8 @@ public:
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virtual bool init() override;
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private:
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static constexpr char axiInterface[] = "M_AXI";
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protected:
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virtual const char *getAxiInterfaceName() { return "M_AXI"; };
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static constexpr char pcieMemory[] = "BAR0";
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struct AxiBar {
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@ -42,6 +42,11 @@ private:
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std::map<std::string, PciBar> pcieToAxiTranslations;
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};
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class XDmaBridge : public AxiPciExpressBridge {
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protected:
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virtual const char *getAxiInterfaceName() { return "M_AXI_B"; };
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};
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class AxiPciExpressBridgeFactory : CoreFactory {
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public:
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@ -63,6 +68,20 @@ protected:
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virtual void parse(Core &, json_t *) override;
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};
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class XDmaBridgeFactory : public AxiPciExpressBridgeFactory {
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public:
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virtual std::string getDescription() const {
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return "Xilinx's XDMA IP configured as AXI-PCIe Bridge";
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}
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private:
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virtual Vlnv getCompatibleVlnv() const { return Vlnv("xilinx.com:ip:xdma:"); }
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// Create a concrete IP instance
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Core *make() const { return new XDmaBridge; };
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};
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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@ -31,6 +31,7 @@ using namespace villas::fpga::ip;
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// first.
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static std::list<Vlnv> vlnvInitializationOrder = {
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Vlnv("xilinx.com:ip:axi_pcie:"),
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Vlnv("xilinx.com:ip:xdma:"),
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Vlnv("xilinx.com:module_ref:axi_pcie_intc:"),
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Vlnv("xilinx.com:ip:axis_switch:"),
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Vlnv("xilinx.com:ip:axi_iic:"),
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@ -22,7 +22,7 @@ bool AxiPciExpressBridge::init() {
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// Throw an exception if the is no bus master interface and thus no
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// address space we can use for translation -> error
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card->addrSpaceIdHostToDevice = busMasterInterfaces.at(axiInterface);
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card->addrSpaceIdHostToDevice = busMasterInterfaces.at(getAxiInterfaceName());
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// Map PCIe BAR0 via VFIO
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const void *bar0_mapped =
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@ -139,3 +139,4 @@ void AxiPciExpressBridgeFactory::parse(Core &ip, json_t *cfg) {
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}
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static AxiPciExpressBridgeFactory p;
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static XDmaBridgeFactory p2;
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@ -43,6 +43,7 @@ whitelist = [
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["xilinx.com", "ip", "axi_gpio"],
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["xilinx.com", "ip", "axi_bram_ctrl"],
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["xilinx.com", "ip", "axi_pcie"],
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["xilinx.com", "ip", "xdma"],
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["xilinx.com", "ip", "axi_iic"],
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["xilinx.com", "module_ref", "dinoif_fast"],
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["xilinx.com", "module_ref", "dinoif_dac"],
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@ -322,7 +323,7 @@ for bram in brams:
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if instance in ips:
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ips[instance]["size"] = int(size)
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pcies = root.xpath('.//MODULE[@MODTYPE="axi_pcie"]')
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pcies = root.xpath('.//MODULE[@MODTYPE="axi_pcie" or @MODTYPE="xdma"]')
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for pcie in pcies:
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instance = pcie.get("INSTANCE")
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axi_bars = ips[instance].setdefault("axi_bars", {})
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@ -332,8 +333,11 @@ for pcie in pcies:
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("AXIBAR", "PCIEBAR", axi_bars),
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("PCIEBAR", "AXIBAR", pcie_bars),
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):
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barnum = pcie.find('.//PARAMETER[@NAME="C_{}_NUM"]'.format(from_bar))
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if barnum == None:
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barnum = pcie.find('.//PARAMETER[@NAME="{}_NUM"]'.format(from_bar))
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from_bar_num = int(
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pcie.find('.//PARAMETER[@NAME="C_{}_NUM"]'.format(from_bar)).get("VALUE")
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barnum.get("VALUE")
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)
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for i in range(0, from_bar_num):
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