Mirrors/VILLASnode
1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-09 00:00:00 +01:00
Code Issues Releases Wiki Activity

fpga: fix timestep being hardcoded

Browse source 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
Niklas Eiling 2024-06-17 13:18:20 +02:00 • committed by Niklas Eiling
parent 675c489126
commit d2c1f55f21
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
lib/nodes/fpga.cpp
View file

@ -74,7 +74,7 @@ int FpgaNode::prepare() {
if (reg != nullptr &&
card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:"))) {
fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, 10e-3);
fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, timestep);
} else {
logger->warn("No DinoAdc or no Register found on FPGA.");
}