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fpga: fix timestep being hardcoded

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
Niklas Eiling 2024-06-17 13:18:20 +02:00 committed by Niklas Eiling
parent 675c489126
commit d2c1f55f21

View file

@ -74,7 +74,7 @@ int FpgaNode::prepare() {
if (reg != nullptr &&
card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:"))) {
fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, 10e-3);
fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, timestep);
} else {
logger->warn("No DinoAdc or no Register found on FPGA.");
}