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fpga: fix timestep being hardcoded
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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1 changed files with 1 additions and 1 deletions
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@ -74,7 +74,7 @@ int FpgaNode::prepare() {
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if (reg != nullptr &&
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card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:"))) {
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fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, 10e-3);
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fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, timestep);
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} else {
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logger->warn("No DinoAdc or no Register found on FPGA.");
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}
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