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hwdef-parse: parse baseaddr and size of BRAM instances in the design

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This commit is contained in:
Steffen Vogel 2017-11-21 18:42:27 +01:00
parent 5ba80c171d
commit e0959b562f
1 changed files with 15 additions and 1 deletions
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16
tools/hwdef-parse.py
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@ -33,7 +33,8 @@ whitelist = [
[ 'acs.eonerc.rwth-aachen.de', 'user', 'rtds_axis' ],
[ 'acs.eonerc.rwth-aachen.de', 'hls' ],
[ 'acs.eonerc.rwth-aachen.de', 'sysgen' ],
[ 'xilinx.com', 'ip', 'axi_gpio' ]
[ 'xilinx.com', 'ip', 'axi_gpio' ],
[ 'xilinx.com', 'ip', 'axi_bram_ctrl' ]
]
# List of VLNI ids of AXI4-Stream infrastructure IP cores which do not alter data
@ -183,4 +184,17 @@ for port in ports:
if instance in ips:
ips[instance]['irqs'][irqname] = irq
# Find BRAM storage depths (size)
brams = root.xpath('.//MODULE[@MODTYPE="axi_bram_ctrl"]')
for bram in brams:
instance = bram.get('INSTANCE')
width = bram.find('.//PARAMETER[@NAME="DATA_WIDTH"]').get('VALUE')
depth = bram.find('.//PARAMETER[@NAME="MEM_DEPTH"]').get('VALUE')
size = int(width) * int(depth) / 8
if instance in ips:
ips[instance]['size'] = int(size)
print(json.dumps(ips, indent=2))