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fpga: improve comments
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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1 changed files with 5 additions and 4 deletions
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@ -140,7 +140,9 @@ void DinoAdc::configureHardware() {
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void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
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double sampleRate) {
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constexpr double dinoClk = 25e6; // Dino is clocked with 25 Mhz
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// constexpr double dinoDacDelay = 828e-9; // Delay for DAC to settle
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// From the data sheets we can assume an analog delay of 828e-9s
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// However this will eat into our computation time, so it should be
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// configurable. Let's assume 0 until we implement this.
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constexpr double dinoDacDelay = 0; // Delay for DAC to settle
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constexpr size_t dinoRegisterTimer = 0;
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constexpr size_t dinoRegisterAdcScale = 1;
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@ -155,9 +157,8 @@ void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
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uint32_t dinoTimerVal = static_cast<uint32_t>(dinoClk / sampleRate) - 1;
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uint32_t dinoDacDelayCycles = static_cast<uint32_t>(dinoClk * dinoDacDelay);
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double rateError = dinoClk / (dinoTimerVal + 1) - sampleRate;
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reg->setRegister(
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dinoRegisterTimer,
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dinoTimerVal); // Timer value for generating ADC trigger signal
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// Timer value for generating ADC trigger signal
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reg->setRegister(dinoRegisterTimer, dinoTimerVal);
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// The following are calibration values for the ADC and DAC. Scale
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// sets an factor to be multiplied with the input value. This is the
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