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ip/switch: reformat and add function that prints current switch config

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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
Niklas Eiling 2024-02-07 15:08:08 +01:00 • committed by Niklas Eiling
parent 7c6d350eb0
commit f2db38fe44
2 changed files with 50 additions and 42 deletions
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67
fpga/include/villas/fpga/ips/switch.hpp
View file

@ -22,68 +22,51 @@ namespace ip {
class AxiStreamSwitch : public Node {
public:
friend class AxiStreamSwitchFactory;
friend class AxiStreamSwitchFactory;
virtual
bool init() override;
virtual bool init() override;
bool connectInternal(const std::string &slavePort,
const std::string &masterPort);
bool connectInternal(const std::string &slavePort,
const std::string &masterPort);
void printConfig() const;
private:
int portNameToNum(const std::string &portName);
int portNameToNum(const std::string &portName);
private:
static constexpr
const char* PORT_DISABLED = "DISABLED";
static constexpr const char *PORT_DISABLED = "DISABLED";
static constexpr
char registerMemory[] = "Reg";
static constexpr char registerMemory[] = "Reg";
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
registerMemory
};
}
std::list<MemoryBlockName> getMemoryBlocks() const {
return {registerMemory};
}
XAxis_Switch xSwitch;
XAxis_Switch_Config xConfig;
XAxis_Switch xSwitch;
XAxis_Switch_Config xConfig;
std::map<std::string, std::string> portMapping;
std::map<std::string, std::string> portMapping;
};
class AxiStreamSwitchFactory : NodeFactory {
public:
virtual
std::string getName() const
{
return "switch";
}
virtual std::string getName() const { return "switch"; }
virtual
std::string getDescription() const
{
return "Xilinx's AXI4-Stream switch";
}
virtual std::string getDescription() const {
return "Xilinx's AXI4-Stream switch";
}
private:
virtual
Vlnv getCompatibleVlnv() const
{
return Vlnv("xilinx.com:ip:axis_switch:");
}
virtual Vlnv getCompatibleVlnv() const {
return Vlnv("xilinx.com:ip:axis_switch:");
}
// Create a concrete IP instance
Core* make() const
{
return new AxiStreamSwitch;
};
// Create a concrete IP instance
Core *make() const { return new AxiStreamSwitch; };
protected:
virtual
void parse(Core &, json_t *) override;
virtual void parse(Core &, json_t *) override;
};
} // namespace ip

25
fpga/lib/ips/switch.cpp
View file

@ -47,6 +47,31 @@ bool AxiStreamSwitch::init()
return true;
}
void AxiStreamSwitch::printConfig() const {
u32 MiPortAddr;
u32 RegValue;
u8 Enable;
logger->info(
"Switch configuration: {} Master Interfaces, {} Slave Interfaces",
xConfig.MaxNumMI, xConfig.MaxNumSI);
for (int i = 0; i < xConfig.MaxNumMI; i++) {
/* Calculate MI port address to be enabled */
MiPortAddr = XAXIS_SCR_MI_MUX_START_OFFSET + 4 * i;
/* Read MI port data */
RegValue = XAxisScr_ReadReg(xSwitch.Config.BaseAddress, MiPortAddr);
/* Fetch enable bit */
Enable = RegValue >> XAXIS_SCR_MI_X_DISABLE_SHIFT;
/* Fetch SI value */
RegValue &= XAXIS_SCR_MI_X_MUX_MASK;
logger->info("Master Interface {}: {} (enabled: {})", i, RegValue, Enable);
}
}
bool AxiStreamSwitch::connectInternal(const std::string &portSlave,
const std::string &portMaster)
{