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ips/pcie: move BAR0 mapping from card into PCIe IP

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This commit is contained in:
Daniel Krebs 2018-05-15 17:50:48 +02:00
parent 89b5169a6e
commit f644a9faa8
2 changed files with 16 additions and 37 deletions
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30
fpga/lib/card.cpp
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@ -205,7 +205,6 @@ PCIeCard::mapMemoryBlock(const MemoryBlock& block)
bool
PCIeCard::init()
{
auto& mm = MemoryManager::get();
logger = getLogger();
logger->info("Initializing FPGA card {}", name);
@ -221,41 +220,12 @@ PCIeCard::init()
VfioDevice& device = vfioContainer->attachDevice(pdev);
this->vfioDevice = &device;
/* Enable memory access and PCI bus mastering for DMA */
if (not device.pciEnable()) {
logger->error("Failed to enable PCI device");
return false;
}
/* Map PCIe BAR */
const void* bar0_mapped = vfioDevice->regionMap(VFIO_PCI_BAR0_REGION_INDEX);
if (bar0_mapped == MAP_FAILED) {
logger->error("Failed to mmap() BAR0");
return false;
}
// determine size of BAR0 region
const size_t bar0_size = vfioDevice->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX);
/* Link mapped BAR0 to global memory graph */
// get the address space of the current application
const auto villasAddrSpace = mm.getProcessAddressSpace();
// get the address space for the PCIe proxy we use with VFIO
const auto cardPCIeAddrSpaceName = mm.getMasterAddrSpaceName(name, "PCIe");
// create a new address space for this FPGA card
addrSpaceIdHostToDevice = mm.getOrCreateAddressSpace(cardPCIeAddrSpaceName);
// create a mapping from our address space to the FPGA card via vfio
mm.createMapping(reinterpret_cast<uintptr_t>(bar0_mapped),
0, bar0_size, "VFIO_map",
villasAddrSpace, addrSpaceIdHostToDevice);
/* Reset system? */
if (do_reset) {
/* Reset / detect PCI device */

23
fpga/lib/ips/pcie.cpp
View file

@ -42,14 +42,23 @@ AxiPciExpressBridge::init()
// Throw an exception if the is no bus master interface and thus no
// address space we can use for translation -> error
const MemoryManager::AddressSpaceId myAddrSpaceid =
busMasterInterfaces.at(axiInterface);
card->addrSpaceIdHostToDevice = busMasterInterfaces.at(axiInterface);
// Create an identity mapping from the FPGA card to this IP as an entry
// point to all other IPs in the FPGA, because Vivado will generate a
// memory view for this bridge that can see all others.
MemoryManager::get().createMapping(0x00, 0x00, SIZE_MAX, "PCIeBridge",
card->addrSpaceIdHostToDevice, myAddrSpaceid);
/* Map PCIe BAR0 via VFIO */
const void* bar0_mapped = card->vfioDevice->regionMap(VFIO_PCI_BAR0_REGION_INDEX);
if (bar0_mapped == MAP_FAILED) {
logger->error("Failed to mmap() BAR0");
return false;
}
// determine size of BAR0 region
const size_t bar0_size = card->vfioDevice->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX);
// create a mapping from process address space to the FPGA card via vfio
mm.createMapping(reinterpret_cast<uintptr_t>(bar0_mapped),
0, bar0_size, "VFIO-H2D",
mm.getProcessAddressSpace(),
card->addrSpaceIdHostToDevice);
/* Make PCIe (IOVA) address space available to FPGA via BAR0 */