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https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
merged config-fpga.h into config.h
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303e730f3a
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8 changed files with 17 additions and 41 deletions
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@ -1,30 +0,0 @@
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/** Hardcoded configuration for VILLASfpga
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2015-2016, Steffen Vogel
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* This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
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* Unauthorized copying of this file, via any medium is strictly prohibited.
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**********************************************************************************/
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#ifndef _CONFIG_FPGA_H_
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#define _CONFIG_FPGA_H_
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#define AFFINITY (1 << 3)
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#define PRIORITY 90
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#define RTDS_DM_FIFO 1
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#define RTDS_DM_DMA_SIMPLE 2
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#define RTDS_DM_DMA_SG 3
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#define DATAMOVER RTDS_DM_DMA_SIMPLE
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/** PCIe BAR number of VILLASfpga registers */
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#define PCI_BAR 0
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/** AXI Bus frequency for all components
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* except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
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#define AXI_HZ 125000000 // 125 MHz
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#define PCI_VID_XILINX 0x10ee
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#define PCI_PID_VFPGA 0x7022
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#endif /* _CONFIG_FPGA_H_ */
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9
config.h
9
config.h
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@ -52,6 +52,15 @@
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#define BENCH_DM_EXP_MIN 0
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#define BENCH_DM_EXP_MAX 20
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/** PCIe BAR number of VILLASfpga registers */
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#define FPGA_PCI_BAR 0
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#define FPGA_PCI_VID_XILINX 0x10ee
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#define FPGA_PCI_PID_VFPGA 0x7022
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/** AXI Bus frequency for all components
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* except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
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#define FPGA_AXI_HZ 125000000 // 125 MHz
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/** Global configuration */
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struct settings {
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int priority; /**< Process priority (lower is better) */
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@ -10,7 +10,7 @@
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#include "fpga/fifo.h"
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#include "nodes/fpga.h"
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#include "config-fpga.h"
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#include "config.h"
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struct list ip_types; /**< Table of existing FPGA IP core drivers */
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@ -9,7 +9,7 @@
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* Unauthorized copying of this file, via any medium is strictly prohibited.
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**********************************************************************************/
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#include "config-fpga.h"
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#include "config.h"
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#include "fpga/ip.h"
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#include "fpga/timer.h"
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@ -22,7 +22,7 @@ int timer_init(struct ip *c)
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XTmrCtr *xtmr = &tmr->inst;
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XTmrCtr_Config xtmr_cfg = {
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.BaseAddress = (uintptr_t) f->map + c->baseaddr,
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.SysClockFreqHz = AXI_HZ
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.SysClockFreqHz = FPGA_AXI_HZ
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};
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XTmrCtr_CfgInitialize(xtmr, &xtmr_cfg, (uintptr_t) f->map + c->baseaddr);
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@ -17,7 +17,7 @@
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#include "nodes/fpga.h"
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#include "config-fpga.h"
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#include "config.h"
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#include "utils.h"
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#include "timing.h"
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@ -94,8 +94,8 @@ int fpga_parse_card(struct fpga *f, int argc, char * argv[], config_setting_t *c
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config_setting_t *cfg_ips, *cfg_slot, *cfg_id, *cfg_fpgas;
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/* Default values */
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f->filter.vendor = PCI_VID_XILINX;
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f->filter.device = PCI_PID_VFPGA;
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f->filter.vendor = FPGA_PCI_VID_XILINX;
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f->filter.device = FPGA_PCI_PID_VFPGA;
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cfg_fpgas = config_setting_get_member(cfg, "fpgas");
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if (!cfg_fpgas)
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@ -22,7 +22,6 @@
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#include <xilinx/xtmrctr_l.h>
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#include "config.h"
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#include "config-fpga.h"
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int fpga_benchmark_datamover(struct fpga *f);
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int fpga_benchmark_jitter(struct fpga *f);
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@ -106,7 +105,7 @@ int fpga_benchmark_jitter(struct fpga *f)
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int *hist = alloc(8 << 20);
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XTmrCtr_SetOptions(xtmr, 0, XTC_INT_MODE_OPTION | XTC_EXT_COMPARE_OPTION | XTC_DOWN_COUNT_OPTION | XTC_AUTO_RELOAD_OPTION);
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XTmrCtr_SetResetValue(xtmr, 0, period * AXI_HZ);
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XTmrCtr_SetResetValue(xtmr, 0, period * FPGA_AXI_HZ);
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XTmrCtr_Start(xtmr, 0);
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uint64_t end, start = rdtscp();
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@ -22,7 +22,6 @@
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#include <villas/fpga/intc.h>
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#include "config.h"
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#include "config-fpga.h"
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#define TEST_LEN 0x1000
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@ -335,7 +334,7 @@ int fpga_test_timer(struct fpga *f)
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error("Failed to enable interrupt");
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XTmrCtr_SetOptions(xtmr, 0, XTC_EXT_COMPARE_OPTION | XTC_DOWN_COUNT_OPTION);
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XTmrCtr_SetResetValue(xtmr, 0, AXI_HZ / 125);
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XTmrCtr_SetResetValue(xtmr, 0, FPGA_AXI_HZ / 125);
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XTmrCtr_Start(xtmr, 0);
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uint64_t counter = intc_wait(f->intc, tmr->irq);
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@ -24,7 +24,6 @@
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#include <villas/kernel/kernel.h>
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#include "config.h"
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#include "config-fpga.h"
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/* Declarations */
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int fpga_benchmarks(int argc, char *argv[], struct fpga *f);
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