Steffen Vogel
1520743f73
fix: Formatting with clang-format
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-10-31 12:18:20 +01:00
60b397dc29
Remove broken opal node-type
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-10-31 11:07:52 +01:00
Philipp Jungkamp
802f86090b
node-ethercat: Fix #include after opened namespace
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The `ethercat_config.hpp` header was included from `ethercat.hpp`
after opening the `villas::node` namespace. This made all definitions
originating from that header including the transitive definitions
from ethercat's `ecrt.h` part of the `villas::node` namespace.
The especially problematic part was that `ecrt.h` itself has an
`#include <netinet/in.h>` introduced in [1]. This caused the libc
definitions for `sa_familt_t`, `sockaddr_in` and `sockaddr_in6` to be
moved into the `villas::node` namespace, causing build error on recent
`ethercat` versions.
[1]: c2f9baf96a
2024-10-16 21:59:41 +02:00
Steffen Vogel
28d354cb84
Fix formatting with clang-format
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-10-15 19:31:49 +02:00
Philipp Jungkamp
40440f2466
ethercat: Shuffle includes to fix failing Nix builds
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Signed-off-by: Philipp Jungkamp <p.jungkamp@gmx.net>
2024-08-28 23:20:52 +02:00
Niklas Eiling
6697e2eb72
Protobuf: Remove include dependency on generated header
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This allows easier reuse of ProtobufFormat.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-27 06:44:47 +02:00
Niklas Eiling
18cdd2a636
protobuf: Clean up CMakeLists
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
7e1bad3590
fpga: Use float accessor for reading and writing floats
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This fixes breaking strict aliasing rules.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
48189b1aaa
protobuf: Install villas.pb-c.h to include/villas/formats
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
9b79c16fb3
fpga: make FPGA support sending and receiving integers
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
296b7d873a
fpga: improve comments and removed dead code
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
34bca6826b
fpga: make dino sampling rate configurable at top level and via json
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
61e74b3e73
Revert default sample length to 64
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
722280f968
Increase default sample length
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
b0680bb5cf
test_rtt: Fix compiler errors
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
2e00453f7b
test_rtt: Improve handling of defaults
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
c4afbf5453
test_rtt: Print estimated test durations
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
f6c7434a61
test_rtt: Rework calculation of test duration
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
64749223e8
test_rtt: Improve statistics
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
047fca5561
test_rtt: Another round of new features
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
d8520699b1
format: Allow printing test meta data to result file
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
a366b80109
Fix formatting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
cad2da3a59
iec61850_sv: Fix IEC 61850-9-2 Sampled Values node and unit test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
4b896a8d7c
super_node: Fix configuration of idle_stop setting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
bc95217766
test_rtt: Stop test cases properly in order to close file handles
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
1748f433fe
webrtc: Fix libdatachannel version detection
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
Niklas Eiling
c151be5cca
fpga: fix includes and various comments
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
9cf926d84e
fpga: add lowLatencyMode setting
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This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d
fpga: improve dma latency
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
718f6ca7eb
test_rtt: Fix cppcheck warnings
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
7f8f7023b4
test_rtt: Port to C++
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
aad7fb478e
Fix code formatting in commented code section
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
3023ddaa3a
Fix some typos and harmonize log output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
a2d55a9b6e
Harmonize descriptions of plugins
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:06:15 +02:00
93cbc5d518
webrtc: Fix several TODOs and other smaller tweaks
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:02:55 +02:00
8db66e25c1
rtp: Fix headers
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
f64c9af259
compat: Fix comptability check in webrtc node-type
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
a792a4abd6
nix: Update to unstable use new nixpkgs-version of libiec61850, lib60870 and libdatachannel
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-26 13:01:15 +01:00
d8acf7b26b
hook: Fix compiler warning about overloaded virtual function
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-26 13:01:15 +01:00
5e70fc38fd
rtp: Upgrade libre dependency to v3.6.0
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-26 13:01:15 +01:00
535d64a644
Replace last tab indentation with spaces
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
dc436073a2
Use spaces for indention of C++ comments
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
3d73c759ea
Reformat all code with clang-format
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 19:34:27 +01:00
b573644133
Remove obsolete SuperNode::getConfigUri()
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-27 19:19:27 +01:00
Niklas Eiling
49523a5076
fpga: remove std::filesystem and properly retrieve searchPath from
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configPath
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
81ff679b41
node: add configPath member
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we need the path of the config file in the nodes in case we want to
parse a separate sub-config with relative path names. This is required
for the fpga node type to parse the ips config file from Fpga::parse.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Steffen Vogel
226ccecd19
Remove usage of std::filesystem
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-26 17:10:57 +01:00
Steffen Vogel
c1410ef8a8
Fix formatting using clang-format
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
Steffen Vogel
9b3a33f31b
Remove unused C++20 include which breaks build on C++17 compilers
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-13 16:23:02 +01:00
Niklas Eiling
18aa0c8862
rework fpga node type
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The various changes in fpga require a rewrite of the fpga node type.
To allow relative paths for the fpga config file, Config and SuperNode
had to be modified so they store the path of the main config file.
The syntax of the fpga node type configuration has changed - the example
config in etc has been modified accordingly.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
