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573 commits

Author SHA1 Message Date
Niklas Eiling
1578a26915 i2c: fix missing getMemoryBlocks method leading to unmapped memory 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
d34ab182e4 fix unmapped ring buffers in dma.cpp leading to segfault 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
e93b8e998d fix IPs without stream port causing an error and fix formatting in 
node.cpp

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
bd1f32da7b fix fomatting in core.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
64d5a6ba42 fpgas.json: switch to new json per default and fix the same 
use fpga definition that includes dino and i2c controller to use the
latest bitstream (vc707-xbar-pcie-dino).
Fix the json for that bitstream to also include the interrupt
controller.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
3e64e5d238 hwdef-parse.py: add interrupt controller added as module_ref to 
whitelist

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
7e07da6e60 add i2c ip draft 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
0138119bff copy new editorconf from node 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
d61337023e add draft for i2c drvier implementation 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:17:26 +01:00
Niklas Eiling
ba71f6384f hwdef-parse.py: add SPDX compliant license info 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:11:26 +01:00
Niklas Eiling
4f4312127d add json for vc707-xbar-pcie-dino 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:11:26 +01:00
Niklas Eiling
ada7cac017 hwdef-parse.py: whitelist iic and DINO IPs 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:11:26 +01:00
Niklas Eiling
e2382c643b add hwdef-parse script from hardware repo 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:11:26 +01:00
Niklas Eiling
2967fb8ac9 fix fpga.cpp unit test failing due to changed DeviceList interface 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Niklas Eiling
654ee84e9e make FPGA device interface agnostic 
remove explicit mentioning of PCIe in the use of Device as a preparation
for integrating platform devices. auto formatted some files.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Niklas Eiling
7ce1ee5a6c make villas-fpga-ctrl accept multiple connect strings 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Niklas Eiling
804f3eea29 update common subrepo 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Philipp Jungkamp
e2c2ec2c8b Fix fmt 10.0.0 related formatting errors. 
Signed-off-by: Philipp Jungkamp <p.jungkamp@gmx.net>
 2023-09-26 17:00:31 +02:00
Steffen Vogel
157d5b21d7 Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82) 
This edits the headers in every file so the copyright notice mentions RWTH Aachen University. We also update some copyright years and fix various comments so the header is the same across all of VILLASframework.

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

---------

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-09-08 11:35:18 +02:00
Niklas Eiling
c2176113d7 update libxil submodule 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-09-08 11:24:43 +02:00
Niklas Eiling
a5991bc794 deactivate stric-aliasing for cast 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-07-25 18:26:19 +02:00
Niklas Eiling
c84df46d9e update libxil submodule, adding correct install path for libxil 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-07-25 17:36:01 +02:00
Niklas Eiling
d9993409e0 fix possible NULL dereferencing in villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 14:56:54 +01:00
Niklas Eiling
1d9ccd6c05 add license note to villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:59:22 +01:00
Niklas Eiling
9d4cd5384d clean up debuggin output and fix scanf usage in villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:52:36 +01:00
Niklas Eiling
d273162f71 fix PCIeCardFactory looking for IP config file at the wrong location 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:29:32 +01:00
Niklas Eiling
d9e60e22b1 make it possible to specify a search path in PcieCard::make so we can use relative paths in config files 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:15:25 +01:00
Niklas Eiling
c05ae4d282 add C bindings for DMA interactions and add a test/example 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 10:47:45 +01:00
Niklas Eiling
b05910f24e add C bindings for external use of VILLASfpga 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 17:12:47 +01:00
Niklas Eiling
7847658548 fix output formatting not being able to print numbers larger than 9 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 15:35:38 +01:00
Niklas Eiling
e6f34f83f4 make villas-fpga-pipe use separat memory segments for reading and writing 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 12:10:37 +01:00
Niklas Eiling
4ef114fad4 remove unnecessary characters in villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-20 10:23:13 +01:00
Niklas Eiling
6b58624e57 fix villas-fpga-pipe 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-15 16:11:44 +01:00
Niklas Eiling
cbad1ca9d1 ConnectString: also allow pipe as a connection target 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-15 16:11:44 +01:00
Pascal Henry Bauer
3db2005bbf removed duplicated declarations 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-02-10 13:34:20 +01:00
Pascal Henry Bauer
26e2251afe reorder of members and added virtual 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-02-10 13:34:20 +01:00
Pascal Henry Bauer
85b2e8b030 removed duplicate implementation 
Signed-off-by: Pascal Henry Bauer <pascal.bauer@rwth-aachen.de>
 2023-02-10 13:34:20 +01:00
Niklas Eiling
c80e5c083d remove map and umapmemoryblock from PcieCard 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:26:11 +01:00
Niklas Eiling
10ecf6c9a6 fix memoryBlocksMapped being defined in both Card and PcieCard 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:18:42 +01:00
Niklas Eiling
87968ab73e enable reading from stdin to DMA in villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
1e3294d14c start readFromDmaToStdOut in separate thread 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
62cab0c4dc clean up README.md 
add project description and related projects (MIOB and DINO)

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
e6f035cd31 add basic thread-safety to ips/dma 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
590cef10d0 add check for missed interrupts when handling reads 
introduce new struct Completion that is returned by Dma::readCompletion
and Dma::writeCompletion

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:16 +01:00
Niklas Eiling
ab39f57405 add more configuration options to villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
8ff0370d36 fix license of utils.hpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
ce1e8e28ce move formatting of printing to stdout to separate class and make in configurable 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
498af9fd1c ips/dma: make read correctly wait on interrupts 
Modify villas-fpga-ctrl to fit the new behavior of Dma.
Makes reading from DMA work even when we are too slow and
only receive partial batches of BDs.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:15 +01:00
Niklas Eiling
5ab6007909 small code review 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:12:10 +01:00
Niklas Eiling
14f924b6c5 rework MemoryBlock use to make use of shared_ptr so the lifetime of the objects is properly tracked 
this fixes that the wrong order of allocating and PciCard destruction
causes an undefined state.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-01-30 16:09:09 +01:00