Niklas Eiling
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16b6a21512
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fpga: make hwdef-parse.py correctly detect interrupt on zynq designs
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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2025-01-24 10:32:57 +01:00 |
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Niklas Eiling
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9bf8f24695
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fpga: update example jsons
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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2025-01-24 10:32:57 +01:00 |
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Niklas Eiling
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2d8b3fccd5
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fpga: consolidate and update FPGA config examples
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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2025-01-24 10:32:57 +01:00 |
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Niklas Eiling
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d99d0918ad
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fpga: add configurations for alveo FPGA
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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2024-03-14 16:07:45 +01:00 |
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a2abaa3cda
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Merge project files, scripts and CMake files of VILLASfpga
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
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2024-02-29 19:33:23 +01:00 |
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