84f0ea9cb5
test_rtt: Fix test case numbering
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
bc95217766
test_rtt: Stop test cases properly in order to close file handles
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
1748f433fe
webrtc: Fix libdatachannel version detection
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
Niklas Eiling
f1776f8be4
fpga: improve comments for fastRead and fastWrite
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
a2ff0aca43
fix formatting in fpga
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
9cf926d84e
fpga: add lowLatencyMode setting
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This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d
fpga: improve dma latency
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
2529c7b2d7
Remove superfluous includes
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 18:56:28 +02:00
1204b47d29
test_rtt: Fix integration test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
718f6ca7eb
test_rtt: Fix cppcheck warnings
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
7fb7294ff0
Fix signal and format handling
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
7f8f7023b4
test_rtt: Port to C++
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
0b04f4fd39
test_rtt: Show test process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
c1f8d0fa80
stats: Indent histogram output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
3023ddaa3a
Fix some typos and harmonize log output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
a2d55a9b6e
Harmonize descriptions of plugins
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:06:15 +02:00
93cbc5d518
webrtc: Fix several TODOs and other smaller tweaks
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:02:55 +02:00
936830d484
Remove unused includes and variables
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
8db66e25c1
rtp: Fix headers
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
553f01d131
compat: Update reliability PAI for libdatachannel >= 0.20
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
79484bc67c
python: Add protobuf format and test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-26 23:59:51 +01:00
5e70fc38fd
rtp: Upgrade libre dependency to v3.6.0
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-26 13:01:15 +01:00
01da8ac47f
protobuf: Add support for new frame flag
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-26 11:53:20 +01:00
Niklas Eiling
c644c8f630
fpga: DMA: poll BD instead of hardware register
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polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Niklas Eiling
322cdf9639
fpga: do not create the vfio container twice
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Steffen Vogel
f9ed272456
node: Fix null-pointer dereference for internal loopback nodes
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-03-12 23:20:09 +01:00
Steffen Vogel
576df42e42
mqtt: Do not attempt validating topics if they are not set
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-03-12 13:20:32 +01:00
73ff061ca8
Fix syntax error
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
dc436073a2
Use spaces for indention of C++ comments
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
4b36073711
Use spaces for indention of CMake files
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
bc670254e2
file: Make directories listable when created
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 22:34:35 +01:00
b573644133
Remove obsolete SuperNode::getConfigUri()
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-27 19:19:27 +01:00
9247846805
exec: Pass name of node and config path via environment variable to sub-process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-27 19:19:27 +01:00
Niklas Eiling
49523a5076
fpga: remove std::filesystem and properly retrieve searchPath from
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configPath
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
ea0bfcf7f4
fpga: clean up debug outputs
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
26e22ca6f4
fpga: make implementation compatible with new createCard interface
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
47362ccede
fpga: enable inline config of card
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additionally to configuring the card in a separate block, we need to be
able to configure the card from the node config to enable libvillas
users to use the fpga node-type.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
81ff679b41
node: add configPath member
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we need the path of the config file in the nodes in case we want to
parse a separate sub-config with relative path names. This is required
for the fpga node type to parse the ips config file from Fpga::parse.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Steffen Vogel
226ccecd19
Remove usage of std::filesystem
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-26 17:10:57 +01:00
Steffen Vogel
272a3fac36
Fix include order
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
Steffen Vogel
c1410ef8a8
Fix formatting using clang-format
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
Niklas Eiling
4ca9c88bd0
fpga: add note about wrong cast
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
97a391c271
update fpga submodule
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
18aa0c8862
rework fpga node type
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The various changes in fpga require a rewrite of the fpga node type.
To allow relative paths for the fpga config file, Config and SuperNode
had to be modified so they store the path of the main config file.
The syntax of the fpga node type configuration has changed - the example
config in etc has been modified accordingly.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
f09e6e909b
fix possible segfault due to non-functional range check with unsigned int
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Philipp Jungkamp
b1e9407f83
packaging-nix: Update inputs
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-26 17:59:39 +02:00
Philipp Jungkamp
33cd6165df
Fix fmt 10.0.0 related formatting errors.
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-26 17:59:39 +02:00
Philipp Jungkamp
f9853f52c7
hook-digest: Add integration test
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-19 19:07:22 +02:00
Philipp Jungkamp
25601efa54
hook-reorder_ts: Add integration test
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-19 19:07:22 +02:00
Philipp Jungkamp
54d3f51afb
format-villas.human: Add NEW_FRAME flag to format
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-19 19:07:22 +02:00
