1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-30 00:00:11 +01:00
Commit graph

13 commits

Author SHA1 Message Date
Niklas Eiling
1710bc48d4 fpga: make compatible to new bitstream iteration
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-11-15 10:36:58 +00:00
Niklas Eiling
fda074d97f fpga: remove duplicate mapping in platform_card
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-11-15 10:36:58 +00:00
Pascal Bauer
677404534e apply refactor 2024-11-15 10:36:57 +00:00
Pascal Bauer
85264ec3c9 change zynq name 2024-11-15 10:36:57 +00:00
Pascal Bauer
3654076c0c add ignored ips 2024-11-15 10:36:57 +00:00
Pascal Bauer
7cc05f9e17 platform irq draft 2024-11-15 10:36:57 +00:00
Pascal Bauer
7e53452767 refactor 2024-11-15 10:36:57 +00:00
Pascal Bauer
6c1a70d44f remove blank line 2024-11-15 10:36:57 +00:00
Pascal Bauer
aedeca5c3b refactor ip_device_reader 2024-11-15 10:36:57 +00:00
Pascal Bauer
7fe15cbd05 update comment 2024-11-15 10:36:57 +00:00
Pascal Bauer
2151865048 change copy to direct initialization 2024-11-15 10:36:57 +00:00
Pascal Bauer
53baa788a1 adjust to driver rework 2024-11-15 10:36:57 +00:00
Pascal Bauer
768284549b add platform card 2024-11-15 10:36:35 +00:00