8 commits

Author	SHA1	Message	Date
daniel-k	92aea92f19	etc: update fpga.json with output of hwdef-parse	2018-01-23 14:43:53 +01:00
daniel-k	f94476b716	ip/node: rename OtherIpNode to StreamPort and other to to	2018-01-10 11:02:08 +01:00
daniel-k	4d3e4dd931	ips: make irqs a list	2018-01-10 11:02:08 +01:00
daniel-k	12024d53e5	lib/ip-node: add IpNode class, IpCore which has streaming ports	2018-01-10 11:02:08 +01:00
daniel-k	a5b5e317d4	wip implementing dependency parsing and proper memeory handling ... works and compiles so for. next is to implement different IP interfaces (Model, Interface, DataMover, Infrastructure, ...)	2018-01-10 11:02:08 +01:00
daniel-k	eeafb2bcc6	etc/fpga: card is in slot 03:00.0 currently	2017-11-28 12:06:26 +01:00
daniel-k	c67c8aac5b	tests: add fpga.json and correctly parse it for unit tests	2017-11-22 19:46:07 +01:00
Steffen Vogel	c3164e93ef	imported source code from VILLASfpga repo and made it compile	2017-11-21 21:31:08 +01:00