6 commits

Author	SHA1	Message	Date
daniel-k	71a54eeab6	lib/ips: implement fifo driver and adapt test	2018-01-10 11:02:08 +01:00
daniel-k	018c89a2b0	tests/main: C++-ify	2018-01-10 11:02:08 +01:00
daniel-k	a5b5e317d4	wip implementing dependency parsing and proper memeory handling ... works and compiles so for. next is to implement different IP interfaces (Model, Interface, DataMover, Infrastructure, ...)	2018-01-10 11:02:08 +01:00
daniel-k	e590d1a350	add namespace villas::fpga and villas::fpga::ip and some renaming	2018-01-10 11:02:08 +01:00
daniel-k	b0e55e6fb2	current wip implementing card, many changes in ip too	2018-01-10 11:02:08 +01:00
daniel-k	d63c2b30bf	tests: compile main as C++	2018-01-10 11:02:08 +01:00

Renamed from fpga/tests/main.c (Browse further)