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53ddbe4e10
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refactor registration of IP core drivers to be aligned with registration of VILLASnode formats and node-types
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
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2023-01-05 14:21:20 +01:00 |
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Pascal Bauer
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c77d124682
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fixed allocation order
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
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2022-12-19 15:47:36 +01:00 |
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Pascal Bauer
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a2b8b2942e
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fixed memory leak (missing deletes before return)
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
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2022-12-19 15:47:35 +01:00 |
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dee5b2d81f
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update Steffens mail address
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
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2022-12-14 17:44:17 +01:00 |
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fb824a82f9
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cleanup of comments
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2022-08-30 12:21:46 -04:00 |
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e5545aa17e
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emc: add initial code to flash FPGA bitstream via PCIe
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2020-07-08 17:16:43 +02:00 |
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08114652d6
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emc: add stub IP
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2020-07-08 15:20:05 +02:00 |
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