Niklas Eiling
0ae08e8434
fpga: improve comments for fastRead and fastWrite
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
98c1f36a02
fix formatting in fpga
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
87a1628c4a
fpga: add lowLatencyMode setting
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This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
f67ca37b0c
fpga: improve dma latency
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
a7d24f756f
Remove superfluous includes
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
71d493cb42
test_rtt: Fix integration test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
a5487f4210
test_rtt: Fix cppcheck warnings
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
95610be274
Fix signal and format handling
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
55238f58b9
test_rtt: Port to C++
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
5ffc0f92f0
test_rtt: Show test process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
6b0d6891a0
stats: Indent histogram output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
d4bc2409c3
Fix some typos and harmonize log output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
3326499e19
Harmonize descriptions of plugins
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
6c5e29de68
webrtc: Fix several TODOs and other smaller tweaks
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
714db711db
Remove unused includes and variables
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
ef27de2d6f
rtp: Fix headers
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
1e6c714560
compat: Update reliability PAI for libdatachannel >= 0.20
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
143e59e3bf
python: Add protobuf format and test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
43a9ab532a
rtp: Upgrade libre dependency to v3.6.0
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
785fe651c2
protobuf: Add support for new frame flag
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
d9b3bdb0de
fpga: DMA: poll BD instead of hardware register
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polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
cc5cd1cbed
fpga: do not create the vfio container twice
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Steffen Vogel
353fb545db
node: Fix null-pointer dereference for internal loopback nodes
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-06-18 12:39:42 +02:00
Steffen Vogel
250d016a98
mqtt: Do not attempt validating topics if they are not set
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-06-18 12:39:42 +02:00
pipeacosta
6b1bc2af1b
Implemented code for i_ipDFT and e_ipDFT
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Signed-off-by: pipeacosta <pipeacosta@gmail.com>
2024-03-18 17:30:52 +00:00
pipeacosta
a08b2fb2d3
Initial commit of the pmu_truncated_ipdft hook
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Signed-off-by: pipeacosta <pipeacosta@gmail.com>
2024-03-18 11:16:04 +00:00
73ff061ca8
Fix syntax error
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
dc436073a2
Use spaces for indention of C++ comments
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
4b36073711
Use spaces for indention of CMake files
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
bc670254e2
file: Make directories listable when created
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 22:34:35 +01:00
b573644133
Remove obsolete SuperNode::getConfigUri()
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-27 19:19:27 +01:00
9247846805
exec: Pass name of node and config path via environment variable to sub-process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-27 19:19:27 +01:00
Niklas Eiling
49523a5076
fpga: remove std::filesystem and properly retrieve searchPath from
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configPath
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
ea0bfcf7f4
fpga: clean up debug outputs
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
26e22ca6f4
fpga: make implementation compatible with new createCard interface
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
47362ccede
fpga: enable inline config of card
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additionally to configuring the card in a separate block, we need to be
able to configure the card from the node config to enable libvillas
users to use the fpga node-type.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Niklas Eiling
81ff679b41
node: add configPath member
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we need the path of the config file in the nodes in case we want to
parse a separate sub-config with relative path names. This is required
for the fpga node type to parse the ips config file from Fpga::parse.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-27 13:40:12 +01:00
Steffen Vogel
226ccecd19
Remove usage of std::filesystem
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-26 17:10:57 +01:00
Steffen Vogel
272a3fac36
Fix include order
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
Steffen Vogel
c1410ef8a8
Fix formatting using clang-format
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-02-14 10:09:52 +01:00
Niklas Eiling
4ca9c88bd0
fpga: add note about wrong cast
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
97a391c271
update fpga submodule
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
18aa0c8862
rework fpga node type
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The various changes in fpga require a rewrite of the fpga node type.
To allow relative paths for the fpga config file, Config and SuperNode
had to be modified so they store the path of the main config file.
The syntax of the fpga node type configuration has changed - the example
config in etc has been modified accordingly.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Niklas Eiling
f09e6e909b
fix possible segfault due to non-functional range check with unsigned int
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-08 11:19:51 +01:00
Philipp Jungkamp
b1e9407f83
packaging-nix: Update inputs
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-26 17:59:39 +02:00
Philipp Jungkamp
33cd6165df
Fix fmt 10.0.0 related formatting errors.
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-26 17:59:39 +02:00
Philipp Jungkamp
f9853f52c7
hook-digest: Add integration test
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-19 19:07:22 +02:00
Philipp Jungkamp
25601efa54
hook-reorder_ts: Add integration test
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-19 19:07:22 +02:00
Philipp Jungkamp
54d3f51afb
format-villas.human: Add NEW_FRAME flag to format
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-19 19:07:22 +02:00
Philipp Jungkamp
c49e339ad1
Don't overwrite sample flags during path sample muxing.
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Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
2023-09-19 19:07:22 +02:00
