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https://git.rwth-aachen.de/acs/public/villas/node/
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94 lines
2 KiB
C++
94 lines
2 KiB
C++
/* Communicate with VILLASfpga Xilinx FPGA boards.
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*
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* Author: Steffen Vogel <post@steffenvogel.de>
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* SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <villas/format.hpp>
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#include <villas/node.hpp>
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#include <villas/node/config.hpp>
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#include <villas/timing.hpp>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include <villas/fpga/node.hpp>
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#include <villas/fpga/pcie_card.hpp>
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namespace villas {
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namespace node {
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#define FPGA_DMA_VLNV
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#define FPGA_AURORA_VLNV "acs.eonerc.rwth-aachen.de:user:aurora_axis:"
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class FpgaNode : public Node {
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protected:
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int irqFd;
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int coalesce;
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bool polling;
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std::shared_ptr<fpga::PCIeCard> card;
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std::shared_ptr<fpga::ip::Dma> dma;
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std::shared_ptr<fpga::ip::Node> intf;
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std::unique_ptr<const MemoryBlock> blockRx;
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std::unique_ptr<const MemoryBlock> blockTx;
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// Config only
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std::string cardName;
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std::string intfName;
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std::string dmaName;
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protected:
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virtual int _read(Sample *smps[], unsigned cnt);
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virtual int _write(Sample *smps[], unsigned cnt);
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public:
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FpgaNode(const uuid_t &id = {}, const std::string &name = "");
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virtual ~FpgaNode();
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virtual int parse(json_t *json);
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virtual const std::string &getDetails();
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virtual int check();
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virtual int prepare();
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virtual std::vector<int> getPollFDs();
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};
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class FpgaNodeFactory : public NodeFactory {
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public:
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using NodeFactory::NodeFactory;
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virtual Node *make(const uuid_t &id = {}, const std::string &nme = "") {
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auto *n = new FpgaNode(id, nme);
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init(n);
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return n;
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}
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virtual int getFlags() const {
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return (int)NodeFactory::Flags::SUPPORTS_READ |
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(int)NodeFactory::Flags::SUPPORTS_WRITE |
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(int)NodeFactory::Flags::SUPPORTS_POLL;
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}
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virtual std::string getName() const { return "fpga"; }
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virtual std::string getDescription() const { return "VILLASfpga"; }
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virtual int start(SuperNode *sn);
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};
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} // namespace node
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} // namespace villas
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