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VILLASnode/include/villas/nodes/fpga.hpp

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/* Communicate with VILLASfpga Xilinx FPGA boards.
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*
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* Author: Steffen Vogel <post@steffenvogel.de>
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* SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
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* SPDX-License-Identifier: Apache-2.0
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*/
#pragma once
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#include <villas/format.hpp>
#include <villas/node.hpp>
#include <villas/node/config.hpp>
#include <villas/timing.hpp>
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#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/dma.hpp>
#include <villas/fpga/node.hpp>
#include <villas/fpga/pcie_card.hpp>
namespace villas {
namespace node {
#define FPGA_DMA_VLNV
#define FPGA_AURORA_VLNV "acs.eonerc.rwth-aachen.de:user:aurora_axis:"
class FpgaNode : public Node {
protected:
int irqFd;
int coalesce;
bool polling;
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std::shared_ptr<fpga::PCIeCard> card;
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std::shared_ptr<fpga::ip::Dma> dma;
std::shared_ptr<fpga::ip::Node> intf;
std::unique_ptr<const MemoryBlock> blockRx;
std::unique_ptr<const MemoryBlock> blockTx;
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// Config only
std::string cardName;
std::string intfName;
std::string dmaName;
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protected:
virtual int _read(Sample *smps[], unsigned cnt);
virtual int _write(Sample *smps[], unsigned cnt);
public:
FpgaNode(const uuid_t &id = {}, const std::string &name = "");
virtual ~FpgaNode();
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virtual int parse(json_t *json);
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virtual const std::string &getDetails();
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virtual int check();
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virtual int prepare();
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virtual std::vector<int> getPollFDs();
};
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class FpgaNodeFactory : public NodeFactory {
public:
using NodeFactory::NodeFactory;
virtual Node *make(const uuid_t &id = {}, const std::string &nme = "") {
auto *n = new FpgaNode(id, nme);
init(n);
return n;
}
virtual int getFlags() const {
return (int)NodeFactory::Flags::SUPPORTS_READ |
(int)NodeFactory::Flags::SUPPORTS_WRITE |
(int)NodeFactory::Flags::SUPPORTS_POLL;
}
virtual std::string getName() const { return "fpga"; }
virtual std::string getDescription() const { return "VILLASfpga"; }
virtual int start(SuperNode *sn);
};
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} // namespace node
} // namespace villas