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VILLASnode/fpga/lib/ips
Niklas Eiling c644c8f630 fpga: DMA: poll BD instead of hardware register
polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
..
rtds2gpu Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
aurora.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
aurora_xilinx.cpp Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82) 2023-09-08 11:35:18 +02:00
bram.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
dino.cpp dino: use enum instead of literal for GAIN 2024-02-26 11:50:44 +01:00
dma.cpp fpga: DMA: poll BD instead of hardware register 2024-03-14 16:07:45 +01:00
emc.cpp Use spaces for indention of C++ comments 2024-02-29 23:18:47 +01:00
fifo.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
gpio.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
i2c.cpp use polling instead of interrupt 2024-02-26 11:50:44 +01:00
intc.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
pcie.cpp fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs 2024-03-14 16:07:45 +01:00
register.cpp fpga: default Dino rate should be 20kHz 2024-03-14 16:07:45 +01:00
rtds.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
switch.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00
timer.cpp Reformat all code with clang-format 2024-02-29 19:34:27 +01:00