1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-09 00:00:00 +01:00
VILLASnode/etc/examples/nodes/fpga.conf
Niklas Eiling 2d8b3fccd5 fpga: consolidate and update FPGA config examples
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2025-01-24 10:32:57 +01:00

34 lines
677 B
Text

# SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
logging = {
level = "debug"
}
fpgas = {
vc707 = {
interface = "pcie"
id = "10ee:7021"
slot = "0000:88:00.0"
do_reset = true
ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino.json"
polling = false
}
}
nodes = {
fpga_0 = {
type = "fpga"
card = "vc707"
connect = ["0->3", "3->dma", "0<-dma"]
timestep = 10e-3
}
}
paths = (
{
in = "fpga_0"
out = "fpga_0"
hooks = ({ type = "print"})
}
)