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https://git.rwth-aachen.de/acs/public/villas/node/
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101 lines
2.6 KiB
C++
101 lines
2.6 KiB
C++
/* Driver for AXI Stream read cache.
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*
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* This module is used to lower latency of
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* a DMA Scatter Gather engine's descriptor fetching. The driver allows for
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* invalidating the cache.
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*
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* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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* SPDX-FileCopyrightText: 2024 Niklas Eiling
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xilinx/xil_io.h>
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#include <villas/fpga/ips/axis_cache.hpp>
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using namespace villas::fpga::ip;
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#define REGISTER_OUT(NUM) (4 * NUM)
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AxisCache::AxisCache() : Node() {}
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bool AxisCache::init() {
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invalidate();
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return true;
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}
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bool AxisCache::check() {
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logger->debug("Checking register interface: Base address: 0x{:08x}",
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getBaseAddr(registerMemory));
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uint32_t buf;
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// We should not change the rate register, because this can lead to hardware fault, so start at 1
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for (size_t i = 1; i < registerNum; i++) {
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setRegister(i, static_cast<uint32_t>(0x00FF00FF));
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}
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for (size_t i = 1; i < registerNum; i++) {
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if (!getRegister(i, buf)) {
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logger->error("Failed to read register {}", i);
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return false;
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}
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if (buf != 0x00FF00FF) {
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logger->error("Register {}: 0x{:08x} != 0x{:08x}", i, buf, i);
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return false;
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}
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}
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// Reset Registers
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resetAllRegisters();
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for (size_t i = 0; i < registerNum; i++) {
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if (!getRegister(i, buf)) {
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logger->error("Failed to read register {}", i);
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return false;
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}
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logger->debug("Register {}: 0x{:08x}", i, buf);
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}
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return true;
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}
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void AxisCache::invalidate() {
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setRegister(0, 1U << 31);
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logger->info("invalidated AXIS cache.");
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}
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bool AxisCache::setRegister(size_t reg, uint32_t value) {
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if (reg >= registerNum) {
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logger->error("Register index out of range: {}/{}", reg, registerNum);
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return false;
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}
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Xil_Out32(getBaseAddr(registerMemory) + REGISTER_OUT(reg), value);
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return true;
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}
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bool AxisCache::getRegister(size_t reg, uint32_t &value) {
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if (reg >= registerNum) {
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logger->error("Register index out of range: {}/{}", reg, registerNum);
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return false;
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}
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value = Xil_In32(getBaseAddr(registerMemory) + REGISTER_OUT(reg));
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return true;
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}
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bool AxisCache::resetRegister(size_t reg) { return setRegister(reg, 0); }
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bool AxisCache::resetAllRegisters() {
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bool result = true;
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for (size_t i = 1; i < registerNum; i++) {
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result &= resetRegister(i);
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}
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return result;
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}
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AxisCache::~AxisCache() {}
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static char n[] = "axis_cache";
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static char d[] = "Register interface VHDL module 'axi_read_cache'";
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static char v[] = "xilinx.com:module_ref:axi_read_cache:";
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static CorePlugin<AxisCache, n, d, v> f;
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