mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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157 lines
4 KiB
C++
157 lines
4 KiB
C++
/** AXI-PCIe Interrupt controller
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <unistd.h>
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#include "config.h"
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#include "log.h"
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#include "plugin.hpp"
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#include "kernel/vfio.h"
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#include "kernel/kernel.h"
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#include "fpga/card.hpp"
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#include "fpga/ips/intc.hpp"
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namespace villas {
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namespace fpga {
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namespace ip {
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// instantiate factory to make available to plugin infrastructure
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static InterruptControllerFactory factory;
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InterruptController::~InterruptController()
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{
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vfio_pci_msi_deinit(&card->vfio_device , this->efds);
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}
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bool InterruptController::start()
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{
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const uintptr_t base = getBaseaddr();
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num_irqs = vfio_pci_msi_init(&card->vfio_device, efds);
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if (num_irqs < 0)
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return false;
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if(vfio_pci_msi_find(&card->vfio_device, nos) != 0)
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return false;
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/* For each IRQ */
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for (int i = 0; i < num_irqs; i++) {
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/* Pin to core */
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if(kernel_irq_setaffinity(nos[i], card->affinity, NULL) !=0)
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serror("Failed to change affinity of VFIO-MSI interrupt");
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/* Setup vector */
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XIntc_Out32(base + XIN_IVAR_OFFSET + i * 4, i);
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}
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XIntc_Out32(base + XIN_IMR_OFFSET, 0); /* Use manual acknowlegement for all IRQs */
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XIntc_Out32(base + XIN_IAR_OFFSET, 0xFFFFFFFF); /* Acknowlege all pending IRQs manually */
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XIntc_Out32(base + XIN_IMR_OFFSET, 0xFFFFFFFF); /* Use fast acknowlegement for all IRQs */
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XIntc_Out32(base + XIN_IER_OFFSET, 0x00000000); /* Disable all IRQs by default */
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XIntc_Out32(base + XIN_MER_OFFSET, XIN_INT_HARDWARE_ENABLE_MASK | XIN_INT_MASTER_ENABLE_MASK);
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debug(4, "FPGA: enabled interrupts");
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return true;
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}
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int
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InterruptController::enableInterrupt(InterruptController::IrqMaskType mask, bool polling)
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{
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uint32_t ier, imr;
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const uintptr_t base = getBaseaddr();
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/* Current state of INTC */
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ier = XIntc_In32(base + XIN_IER_OFFSET);
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imr = XIntc_In32(base + XIN_IMR_OFFSET);
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/* Clear pending IRQs */
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XIntc_Out32(base + XIN_IAR_OFFSET, mask);
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for (int i = 0; i < num_irqs; i++) {
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if (mask & (1 << i))
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this->polling[i] = polling;
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}
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if (polling) {
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XIntc_Out32(base + XIN_IMR_OFFSET, imr & ~mask);
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XIntc_Out32(base + XIN_IER_OFFSET, ier & ~mask);
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}
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else {
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XIntc_Out32(base + XIN_IER_OFFSET, ier | mask);
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XIntc_Out32(base + XIN_IMR_OFFSET, imr | mask);
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}
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debug(3, "New ier = %#x", XIntc_In32(base + XIN_IER_OFFSET));
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debug(3, "New imr = %#x", XIntc_In32(base + XIN_IMR_OFFSET));
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debug(3, "New isr = %#x", XIntc_In32(base + XIN_ISR_OFFSET));
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debug(8, "FPGA: Interupts enabled: mask=%#x polling=%d", mask, polling);
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return true;
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}
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int
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InterruptController::disableInterrupt(InterruptController::IrqMaskType mask)
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{
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const uintptr_t base = getBaseaddr();
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uint32_t ier = XIntc_In32(base + XIN_IER_OFFSET);
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XIntc_Out32(base + XIN_IER_OFFSET, ier & ~mask);
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return true;
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}
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uint64_t InterruptController::waitForInterrupt(int irq)
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{
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assert(irq < maxIrqs);
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const uintptr_t base = getBaseaddr();
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if (this->polling[irq]) {
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uint32_t isr, mask = 1 << irq;
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do {
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isr = XIntc_In32(base + XIN_ISR_OFFSET);
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pthread_testcancel();
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} while ((isr & mask) != mask);
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XIntc_Out32(base + XIN_IAR_OFFSET, mask);
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return 1;
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}
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else {
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uint64_t cnt;
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ssize_t ret = read(efds[irq], &cnt, sizeof(cnt));
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if (ret != sizeof(cnt))
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return 0;
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return cnt;
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}
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}
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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