Niklas Eiling ca03e1d406 fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs ... Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>		2024-03-14 16:07:45 +01:00
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villas/fpga	fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs	2024-03-14 16:07:45 +01:00