mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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409 lines
No EOL
10 KiB
C
409 lines
No EOL
10 KiB
C
/** DMA related helper functions
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*
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* These functions present a simpler interface to Xilinx' DMA driver (XAxiDma_*)
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2015-2016, Steffen Vogel
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* This file is part of VILLASfpga. All Rights Reserved. Proprietary and confidential.
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* Unauthorized copying of this file, via any medium is strictly prohibited.
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**********************************************************************************/
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#include <sys/types.h>
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#include <unistd.h>
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#include <villas/log.h>
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#include "utils.h"
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#include "fpga/dma.h"
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int dma_write_complete(XAxiDma *xdma, int irq)
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{
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int processed, ret;
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XAxiDma_Bd *bd;
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XAxiDma_BdRing *ring = XAxiDma_GetTxRing(xdma);
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/* Wait until the one BD TX transaction is done */
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while ((processed = XAxiDma_BdRingFromHw(ring, XAXIDMA_ALL_BDS, &bd)) == 0) {
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if (irq >= 0)
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wait_irq(irq);
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}
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/* Free all processed TX BDs for future transmission */
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ret = XAxiDma_BdRingFree(ring, processed, bd);
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if (ret != XST_SUCCESS) {
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info("Failed to free %d tx BDs %d", processed, ret);
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return -1;
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}
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return processed;
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}
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int dma_read_complete(XAxiDma *xdma, int irq)
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{
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return 0;
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}
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ssize_t dma_write(XAxiDma *xdma, char *buf, size_t len, int irq)
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{
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int ret;
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if (xdma->HasSg) {
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XAxiDma_BdRing *ring;
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XAxiDma_Bd *bd;
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ring = XAxiDma_GetTxRing(xdma);
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ret = XAxiDma_BdRingAlloc(ring, 1, &bd);
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if (ret != XST_SUCCESS)
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return -1;
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/* Set up the BD using the information of the packet to transmit */
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ret = XAxiDma_BdSetBufAddr(bd, (uintptr_t) buf);
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if (ret != XST_SUCCESS) {
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info("Tx set buffer addr %p on BD %p failed %d", buf, bd, ret);
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return -1;
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}
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ret = XAxiDma_BdSetLength(bd, len, ring->MaxTransferLen);
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if (ret != XST_SUCCESS) {
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info("Tx set length %zu on BD %p failed %d", len, bd, ret);
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return -1;
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}
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/* Set SOF / EOF / ID */
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XAxiDma_BdSetCtrl(bd, XAXIDMA_BD_CTRL_TXEOF_MASK | XAXIDMA_BD_CTRL_TXSOF_MASK);
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XAxiDma_BdSetId(bd, (uintptr_t) buf);
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/* Give the BD to DMA to kick off the transmission. */
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ret = XAxiDma_BdRingToHw(ring, 1, bd);
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if (ret != XST_SUCCESS) {
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info("to hw failed %d", ret);
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return -1;
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}
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dma_write_complete(xdma, irq);
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}
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else {
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ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) buf, len, XAXIDMA_DMA_TO_DEVICE);
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if (ret != XST_SUCCESS) {
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warn("Failed DMA transfer");
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return -1;
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}
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if (irq >= 0) {
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wait_irq(irq);
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XAxiDma_IntrAckIrq(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
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}
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else {
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while (XAxiDma_Busy(xdma, XAXIDMA_DMA_TO_DEVICE))
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__asm__("nop");
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}
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}
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return len;
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}
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ssize_t dma_read(XAxiDma *xdma, char *buf, size_t len, int irq)
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{
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int ret;
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if (xdma->HasSg) {
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int freecnt, processed;
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XAxiDma_BdRing *ring;
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XAxiDma_Bd *bd;
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ring = XAxiDma_GetRxRing(xdma);
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processed = 0;
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do {
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/* Wait until the data has been received by the Rx channel */
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while (XAxiDma_BdRingFromHw(ring, 1, &bd) == 0) {
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if (irq >= 0)
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wait_irq(irq);
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}
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//char *bdbuf = XAxiDma_BdGetBufAddr(bd);
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//size_t bdlen = XAxiDma_BdGetActualLength(bd, XAXIDMA_MAX_TRANSFER_LEN);
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//memcpy(buf, bdbuf, bdlen);
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//buf += bdlen;
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processed++;
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} while (XAxiDma_BdGetSts(bd) & XAXIDMA_BD_STS_RXEOF_MASK);
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/* Free all processed RX BDs for future transmission */
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ret = XAxiDma_BdRingFree(ring, processed, bd);
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if (ret != XST_SUCCESS) {
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info("Failed to free %d rx BDs %d", processed, ret);
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return XST_FAILURE;
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}
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/* Return processed BDs to RX channel so we are ready to receive new
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* packets:
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* - Allocate all free RX BDs
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* - Pass the BDs to RX channel
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*/
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freecnt = XAxiDma_BdRingGetFreeCnt(ring);
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ret = XAxiDma_BdRingAlloc(ring, freecnt, &bd);
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if (ret != XST_SUCCESS) {
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info("bd alloc failed");
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return -1;
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}
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ret = XAxiDma_BdRingToHw(ring, freecnt, bd);
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if (ret != XST_SUCCESS) {
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info("Submit %d rx BDs failed %d", freecnt, ret);
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return -1;
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}
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}
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else {
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ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) buf, len, XAXIDMA_DEVICE_TO_DMA);
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if (ret != XST_SUCCESS)
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warn("Failed DMA transfer");
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if (irq >= 0) {
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wait_irq(irq);
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XAxiDma_IntrAckIrq(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
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}
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else {
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while (XAxiDma_Busy(xdma, XAXIDMA_DEVICE_TO_DMA))
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__asm__("nop");
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}
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}
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return len;
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}
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ssize_t dma_ping_pong(XAxiDma *xdma, char *src, char *dst, size_t len, int s2mm_irq)
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{
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int ret;
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/* Prepare S2MM transfer */
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ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) dst, len, XAXIDMA_DEVICE_TO_DMA);
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if (ret != XST_SUCCESS)
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warn("Failed DMA transfer");
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/* Start MM2S transfer */
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ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) src, len, XAXIDMA_DMA_TO_DEVICE);
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if (ret != XST_SUCCESS) {
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warn("Failed DMA transfer");
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return -1;
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}
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/* Wait for completion */
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if (s2mm_irq >= 0) {
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wait_irq(s2mm_irq);
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XAxiDma_IntrAckIrq(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
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}
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else {
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while (XAxiDma_Busy(xdma, XAXIDMA_DEVICE_TO_DMA))
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__asm__("nop");
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}
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return XAxiDma_ReadReg(xdma->RegBase + XAXIDMA_RX_OFFSET, XAXIDMA_BUFFLEN_OFFSET);
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}
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static int dma_setup_bdring(XAxiDma_BdRing *ring, struct dma_mem *bdbuf)
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{
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int delay = 0;
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int coalesce = 1;
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int ret, cnt;
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XAxiDma_Bd clearbd;
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/* Disable all RX interrupts before RxBD space setup */
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XAxiDma_BdRingIntDisable(ring, XAXIDMA_IRQ_ALL_MASK);
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/* Set delay and coalescing */
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XAxiDma_BdRingSetCoalesce(ring, coalesce, delay);
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/* Setup Rx BD space */
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cnt = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, bdbuf->len);
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ret = XAxiDma_BdRingCreate(ring, bdbuf->base_phys, bdbuf->base_virt, XAXIDMA_BD_MINIMUM_ALIGNMENT, cnt);
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if (ret != XST_SUCCESS) {
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info("RX create BD ring failed %d", ret);
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return XST_FAILURE;
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}
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/*
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* Setup an all-zero BD as the template for the Rx channel.
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*/
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XAxiDma_BdClear(&clearbd);
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ret = XAxiDma_BdRingClone(ring, &clearbd);
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if (ret != XST_SUCCESS) {
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info("RX clone BD failed %d", ret);
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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static int dma_setup_rx(XAxiDma *AxiDmaInstPtr, struct dma_mem *bdbuf, struct dma_mem *rxbuf, size_t maxlen)
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{
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int ret;
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XAxiDma_BdRing *ring;
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XAxiDma_Bd *bd, *curbd;
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uint32_t freecnt;
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uintptr_t rxptr;
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ring = XAxiDma_GetRxRing(AxiDmaInstPtr);
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ret = dma_setup_bdring(ring, bdbuf);
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if (ret != XST_SUCCESS)
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return -1;
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/* Attach buffers to RxBD ring so we are ready to receive packets */
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freecnt = XAxiDma_BdRingGetFreeCnt(ring);
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ret = XAxiDma_BdRingAlloc(ring, freecnt, &bd);
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if (ret != XST_SUCCESS) {
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info("RX alloc BD failed %d", ret);
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return XST_FAILURE;
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}
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curbd = bd;
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rxptr = rxbuf->base_phys;
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for (int i = 0; i < freecnt; i++) {
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ret = XAxiDma_BdSetBufAddr(curbd, rxptr);
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if (ret != XST_SUCCESS) {
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info("Set buffer addr %#lx on BD %p failed %d", rxptr, curbd, ret);
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return XST_FAILURE;
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}
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ret = XAxiDma_BdSetLength(curbd, maxlen, ring->MaxTransferLen);
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if (ret != XST_SUCCESS) {
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info("Rx set length %zu on BD %p failed %d", maxlen, curbd, ret);
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return XST_FAILURE;
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}
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/* Receive BDs do not need to set anything for the control
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* The hardware will set the SOF/EOF bits per stream ret */
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XAxiDma_BdSetCtrl(curbd, 0);
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XAxiDma_BdSetId(curbd, rxptr);
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rxptr += maxlen;
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curbd = (XAxiDma_Bd *) XAxiDma_BdRingNext(ring, curbd);
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}
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/* Clear the receive buffer, so we can verify data */
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memset((void *) (uintptr_t) rxbuf->base_virt, 0, rxbuf->len);
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ret = XAxiDma_BdRingToHw(ring, freecnt, bd);
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if (ret != XST_SUCCESS) {
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info("RX submit hw failed %d", ret);
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return XST_FAILURE;
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}
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/* Start RX DMA channel */
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ret = XAxiDma_BdRingStart(ring);
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if (ret != XST_SUCCESS) {
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info("RX start hw failed %d", ret);
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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static int dma_setup_tx(XAxiDma *AxiDmaInstPtr, struct dma_mem *bd)
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{
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int ret;
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XAxiDma_BdRing *ring;
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ring = XAxiDma_GetTxRing(AxiDmaInstPtr);
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ret = dma_setup_bdring(ring, bd);
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if (ret != XST_SUCCESS)
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return -1;
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/* Start the TX channel */
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ret = XAxiDma_BdRingStart(ring);
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if (ret != XST_SUCCESS) {
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info("failed start bdring txsetup %d", ret);
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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int dma_init(XAxiDma *xdma, char *baseaddr, enum dma_mode mode, struct dma_mem *bd, struct dma_mem *rx, size_t maxlen)
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{
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int ret, sgincld;
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XAxiDma_Config xdma_cfg = {
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.BaseAddr = (uintptr_t) baseaddr,
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.HasStsCntrlStrm = 0,
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.HasMm2S = 1,
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.HasMm2SDRE = 0,
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.Mm2SDataWidth = 32,
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.HasS2Mm = 1,
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.HasS2MmDRE = 0, /* Data Realignment Engine */
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.S2MmDataWidth = 32,
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.HasSg = (mode == DMA_MODE_SG) ? 1 : 0,
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.Mm2sNumChannels = 1,
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.S2MmNumChannels = 1,
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.Mm2SBurstSize = 64,
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.S2MmBurstSize = 64,
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.MicroDmaMode = 0,
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.AddrWidth = 32
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};
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ret = XAxiDma_CfgInitialize(xdma, &xdma_cfg);
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if (ret != XST_SUCCESS) {
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info("Initialization failed %d", ret);
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return -1;
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}
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/* Check if correct DMA type */
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sgincld = XAxiDma_In32((uintptr_t) baseaddr + XAXIDMA_TX_OFFSET+ XAXIDMA_SR_OFFSET) &
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XAxiDma_In32((uintptr_t) baseaddr + XAXIDMA_RX_OFFSET+ XAXIDMA_SR_OFFSET) &
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XAXIDMA_SR_SGINCL_MASK;
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if ((mode == DMA_MODE_SIMPLE && sgincld == XAXIDMA_SR_SGINCL_MASK) ||
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(mode == DMA_MODE_SG && sgincld != XAXIDMA_SR_SGINCL_MASK)) {
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info("This is not a %s DMA controller", (mode == DMA_MODE_SG) ? "SG" : "Simple");
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return -1;
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}
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/* Perform selftest */
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ret = XAxiDma_Selftest(xdma);
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if (ret != XST_SUCCESS) {
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info("DMA selftest failed");
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return -1;
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}
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/* Setup Buffer Descriptor rings for SG DMA */
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if (mode == DMA_MODE_SG) {
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/* Split BD memory equally between Rx and Tx rings */
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struct dma_mem bd_rx = {
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.base_virt = bd->base_virt,
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.base_phys = bd->base_phys,
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.len = bd->len / 2
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};
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struct dma_mem bd_tx = {
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.base_virt = bd->base_virt + bd_rx.len,
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.base_phys = bd->base_phys + bd_rx.len,
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.len = bd->len - bd_rx.len
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};
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ret = dma_setup_rx(xdma, &bd_rx, rx, maxlen);
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if (ret != XST_SUCCESS)
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return -1;
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ret = dma_setup_tx(xdma, &bd_tx);
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if (ret != XST_SUCCESS)
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return -1;
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}
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/* Enable completion interrupts for both channels */
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XAxiDma_IntrEnable(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
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XAxiDma_IntrEnable(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
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return 0;
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} |