Niklas Eiling c644c8f630 fpga: DMA: poll BD instead of hardware register ... polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways. Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>		2024-03-14 16:07:45 +01:00
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ips	fpga: DMA: poll BD instead of hardware register	2024-03-14 16:07:45 +01:00
card.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
CMakeLists.txt	Use spaces for indention of CMake files	2024-02-29 23:18:47 +01:00
core.cpp	fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs	2024-03-14 16:07:45 +01:00
dma.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
memory.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
node.cpp	fix IPs without stream port causing an error and fix formatting in	2024-01-09 17:14:05 +01:00
pcie_card.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
utils.cpp	fpga: fpga::createCards not finding a config is not an error	2024-03-14 16:07:45 +01:00
vlnv.cpp	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00