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https://git.rwth-aachen.de/acs/public/villas/node/
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e20bcd3d1e
This setting improves latency by remove various checks. Use with caution! Requires read cache in FPGA design! The common use case in VILLASfpga is that we have exactly one write for every read and the number of exchanged signals do not change. If this is the case, we can reuse the buffer descriptors during reads and write, thus avoidng freeing, reallocating and setting them up. We set up the descriptors in start, and in write or read, we only reset the complete bit in the buffer descriptor and write to the tdesc register to start the DMA transfer. Improves read/write latency by approx. 40%. Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
110 lines
3.1 KiB
C++
110 lines
3.1 KiB
C++
/* Communicate with VILLASfpga Xilinx FPGA boards.
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*
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* Author: Steffen Vogel <post@steffenvogel.de>
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* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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* SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
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* SPDX-FileCopyrightText: 2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <thread>
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#include <villas/format.hpp>
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#include <villas/node.hpp>
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#include <villas/node/config.hpp>
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#include <villas/timing.hpp>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include <villas/fpga/node.hpp>
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#include <villas/fpga/pcie_card.hpp>
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namespace villas {
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namespace node {
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class FpgaNode : public Node {
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enum InterfaceType { PCIE, PLATFORM };
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protected:
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// Settings
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std::string cardName;
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std::list<std::string> connectStrings;
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// This setting improves latency by remove various checks.
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// Use with caution! Requires read cache in FPGA design!
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// The common use case in VILLASfpga is that we have exactly
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// one write for every read and the number of exchanged signals
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// do not change. If this is the case, we can reuse the buffer
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// descriptors during reads and write, thus avoidng freeing,
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// reallocating and setting them up.
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// We set up the descriptors in start, and in write or read,
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// we only reset the complete bit in the buffer descriptor and
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// write to the tdesc register to start the DMA transfer.
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// Improves read/write latency by approx. 40%.
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bool lowLatencyMode;
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// State
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std::shared_ptr<fpga::Card> card;
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std::shared_ptr<villas::fpga::ip::Dma> dma;
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std::shared_ptr<villas::MemoryBlock> blockRx;
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std::shared_ptr<villas::MemoryBlock> blockTx;
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// Non-public methods
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virtual int fastRead(Sample *smps[], unsigned cnt);
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virtual int slowRead(Sample *smps[], unsigned cnt);
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virtual int _read(Sample *smps[], unsigned cnt) override;
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virtual int fastWrite(Sample *smps[], unsigned cnt);
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virtual int slowWrite(Sample *smps[], unsigned cnt);
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virtual int _write(Sample *smps[], unsigned cnt) override;
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public:
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FpgaNode(const uuid_t &id = {}, const std::string &name = "");
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virtual ~FpgaNode();
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virtual int prepare() override;
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virtual int parse(json_t *json) override;
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virtual int check() override;
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virtual int start() override;
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virtual int stop() override;
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virtual std::vector<int> getPollFDs() override;
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virtual const std::string &getDetails() override;
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};
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class FpgaNodeFactory : public NodeFactory {
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public:
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using NodeFactory::NodeFactory;
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virtual Node *make(const uuid_t &id = {},
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const std::string &nme = "") override {
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auto *n = new FpgaNode(id, nme);
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init(n);
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return n;
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}
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virtual int getFlags() const override {
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return (int)NodeFactory::Flags::SUPPORTS_READ |
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(int)NodeFactory::Flags::SUPPORTS_WRITE |
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(int)NodeFactory::Flags::SUPPORTS_POLL;
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}
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virtual std::string getName() const override { return "fpga"; }
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virtual std::string getDescription() const override { return "VILLASfpga"; }
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virtual int start(SuperNode *sn) override;
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};
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} // namespace node
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} // namespace villas
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