canfd_v1_0: Updated the driver as per new RTL change.
This patch updates the canfd driver as per new RTL changes. Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
This commit is contained in:
naga sureshkumar relli
Nava kishore Manne
parent
cc4798846a
commit
0458436f41
4 changed files with 206 additions and 151 deletions
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@ -49,6 +49,11 @@
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* 1.0 nsk 15/05/15 Updated Correct AFRID and AFRMSK Registers.
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* Modified DataSwaping when EDL is Zero.
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* (CR 861772)
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* 1.0 nsk 16/06/15 Updated XCanFd_Recv_Mailbox(), XCanFd_EnterMode(),
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* XCanFd_GetMode() since RTL has changed.RTL Changes,Added
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* new bits to MSR,SR,ISR,IER,ICR Registers and modified
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* TS2 bits in BTR and F_SJW bits in F_BTR Registers.
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* .
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*
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* </pre>
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******************************************************************************/
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@ -179,7 +184,9 @@ u32 XCanFd_AcceptFilterGetEnabled(XCanFd *InstancePtr)
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* - XCANFD_MODE_NORMAL if the device is in Normal Mode.
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* - XCANFD_MODE_LOOPBACK if the device is in Loop Back Mode.
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* - XCANFD_MODE_SNOOP if the device is in Snoop Mode.
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*
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* - XCANFD_MODE_BR if the device is in Bus-Off recovery Mode.
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* - XCANFD_MODE_PEE if the device is in Protocol Exception
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* Event mode.
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* @note None.
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*
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*****************************************************************************/
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@ -199,7 +206,6 @@ u8 XCanFd_GetMode(XCanFd *InstancePtr)
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else if ((Value & XCANFD_SR_SLEEP_MASK) != (u32)0) {
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Mode = XCANFD_MODE_SLEEP;
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}
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else if ((Value & XCANFD_SR_NORMAL_MASK) != (u32)0) {
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if ((Value & XCANFD_SR_SNOOP_MASK) != (u32)0) {
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Mode = XCANFD_MODE_SNOOP;
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@ -213,6 +219,10 @@ u8 XCanFd_GetMode(XCanFd *InstancePtr)
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/* If this line is reached, the device is in Loop Back Mode. */
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Mode = XCANFD_MODE_LOOPBACK;
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}
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if ((Value & XCANFD_SR_PEE_CONFIG_MASK) != (u32)0){
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Mode = Mode | XCANFD_MODE_PEE;
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}
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return (u8)Mode;
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}
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@ -225,8 +235,12 @@ u8 XCanFd_GetMode(XCanFd *InstancePtr)
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* - Configuration Mode: Pass in parameter XCANFD_MODE_CONFIG
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* - Sleep Mode: Pass in parameter XCANFD_MODE_SLEEP
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* - Normal Mode: Pass in parameter XCANFD_MODE_NORMAL
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* - Loop Back Mode: Pass in parameter XCANFD_MODE_LOOPBACK.
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* - Loop Back Mode: Pass in parameter XCANFD_MODE_LOOPBACK
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* - Snoop Mode: Pass in Parameter XCANFD_MODE_SNOOP
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* - Auto Bus-Off Recovery Mode: Pass in Parameter XCANFD_MODE_ABR
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* - Start Bus-Off Recovery Mode: Pass in Parameter XCANFD_MODE_SBR
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* - Protocol Exception Event Mode: Pass in Parameter XCANFD_MODE_PEE
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* - Disable AutoRetransmission Mode: Pass in Paramter XCANFD_MODE_DAR
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*
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* Read xcanfd.h and device specification for detailed description of each
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* operation mode.
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@ -255,11 +269,15 @@ void XCanFd_EnterMode(XCanFd *InstancePtr, u8 OperationMode)
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(OperationMode == XCANFD_MODE_SLEEP) ||
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(OperationMode == XCANFD_MODE_NORMAL) ||
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(OperationMode == XCANFD_MODE_LOOPBACK) ||
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(OperationMode == XCANFD_MODE_SNOOP));
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(OperationMode == XCANFD_MODE_SNOOP) ||
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(OperationMode == XCANFD_MODE_PEE) ||
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(OperationMode == XCANFD_MODE_ABR) ||
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(OperationMode == XCANFD_MODE_DAR) ||
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(OperationMode == XCANFD_MODE_SBR));
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CurrentMode = XCanFd_GetMode(InstancePtr);
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MsrReg = XCanFd_ReadReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET) & XCANFD_DAR_MASK;
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XCANFD_MSR_OFFSET) & XCANFD_MSR_CONFIG_MASK;
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if ((CurrentMode == XCANFD_MODE_NORMAL) &&
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(OperationMode == XCANFD_MODE_SLEEP)) {
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@ -282,7 +300,7 @@ void XCanFd_EnterMode(XCanFd *InstancePtr, u8 OperationMode)
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* mode.
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*/
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET,MsrReg);
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XCANFD_SRR_OFFSET, 0);
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/*
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* Check if the device has entered Configuration Mode, if not, return
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@ -293,47 +311,81 @@ void XCanFd_EnterMode(XCanFd *InstancePtr, u8 OperationMode)
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}
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switch (OperationMode) {
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case XCANFD_MODE_CONFIG:
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case XCANFD_MODE_CONFIG:
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break;
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case XCANFD_MODE_SLEEP:
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case XCANFD_MODE_SLEEP:
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/* Switch the device into Sleep Mode */
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET,
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(XCANFD_MSR_SLEEP_MASK | MsrReg));
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET,
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XCANFD_SRR_CEN_MASK);
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/* Switch the device into Sleep Mode */
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET,
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(XCANFD_MSR_SLEEP_MASK | MsrReg));
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET, XCANFD_SRR_CEN_MASK);
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break;
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case XCANFD_MODE_NORMAL:
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET, MsrReg);
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET, XCANFD_SRR_CEN_MASK);
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break;
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case XCANFD_MODE_LOOPBACK:
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET,
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(XCANFD_MSR_LBACK_MASK | MsrReg));
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET, XCANFD_SRR_CEN_MASK);
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break;
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case XCANFD_MODE_SNOOP:
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET, (XCANFD_MSR_SNOOP_MASK |
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MsrReg));
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET, XCANFD_SRR_CEN_MASK);
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break;
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case XCANFD_MODE_ABR:
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET, (XCANFD_MSR_ABR_MASK |
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MsrReg));
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET, XCANFD_SRR_CEN_MASK);
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break;
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case XCANFD_MODE_NORMAL:
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case XCANFD_MODE_SBR:
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET,MsrReg);
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET,XCANFD_SRR_CEN_MASK);
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET, (XCANFD_MSR_SBR_MASK |
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MsrReg));
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break;
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case XCANFD_MODE_PEE:
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET, (XCANFD_MSR_DPEE_MASK |
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MsrReg));
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET, XCANFD_SRR_CEN_MASK);
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break;
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case XCANFD_MODE_LOOPBACK:
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET,
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(XCANFD_MSR_LBACK_MASK | MsrReg));
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET,
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XCANFD_SRR_CEN_MASK);
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case XCANFD_MODE_DAR:
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break;
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET, (XCANFD_MSR_DAR_MASK |
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MsrReg));
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET, XCANFD_SRR_CEN_MASK);
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case XCANFD_MODE_SNOOP:
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_MSR_OFFSET, (XCANFD_MSR_SNOOP_MASK | MsrReg));
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_SRR_OFFSET, XCANFD_SRR_CEN_MASK);
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break;
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}
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}
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@ -419,11 +471,11 @@ int XCanFd_Send(XCanFd *InstancePtr, u32 *FramePtr,u32 *TxBufferNumber)
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/* Write ID to ID Register */
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_TXID_OFFSET(FreeTxBuffer),FramePtr[0]);
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XCANFD_TXID_OFFSET(FreeTxBuffer), FramePtr[0]);
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/* Write DLC to DLC Register */
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_TXDLC_OFFSET(FreeTxBuffer),FramePtr[1]);
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XCANFD_TXDLC_OFFSET(FreeTxBuffer), FramePtr[1]);
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CanEDL = XCanFd_ReadReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_TXDLC_OFFSET(FreeTxBuffer));
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@ -440,7 +492,7 @@ int XCanFd_Send(XCanFd *InstancePtr, u32 *FramePtr,u32 *TxBufferNumber)
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XCanFd_WriteReg(
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InstancePtr->CanFdConfig.BaseAddress,
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(XCANFD_TXDW_OFFSET(FreeTxBuffer)+
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(DwIndex*XCANFD_DW_BYTES)),OutValue);
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(DwIndex*XCANFD_DW_BYTES)), OutValue);
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DwIndex++;
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}
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}
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@ -455,7 +507,7 @@ int XCanFd_Send(XCanFd *InstancePtr, u32 *FramePtr,u32 *TxBufferNumber)
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XCanFd_WriteReg(
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InstancePtr->CanFdConfig.BaseAddress,
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(XCANFD_TXDW_OFFSET(FreeTxBuffer)+
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(Len)),OutValue);
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(Len)), OutValue);
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DwIndex++;
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}
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}
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@ -465,7 +517,7 @@ int XCanFd_Send(XCanFd *InstancePtr, u32 *FramePtr,u32 *TxBufferNumber)
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XCANFD_TRR_OFFSET);
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Value |= (1 << FreeTxBuffer);
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XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_TRR_OFFSET,Value);
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XCANFD_TRR_OFFSET, Value);
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/* Assign buffer number to user */
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*TxBufferNumber = FreeTxBuffer;
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@ -672,9 +724,9 @@ u32 XCanFd_Recv_Sequential(XCanFd *InstancePtr, u32 *FramePtr)
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/*****************************************************************************/
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/**
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*
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* This function receives a CAN Frame in MAIL BOX Mode. Read Receive
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* Control Status Registers.if CoreStatus bit is set then read that
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* corresponding buffer and update the data to user buffer.
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* This function receives a CAN Frame in MAIL BOX Mode. Read Rx Last Buffer
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* Index from ISR Register. This tells which buffer is having data.then read
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* and update the data to user buffer.
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*
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* @param InstancePtr is a pointer to the XCanFd instance to be worked on.
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* @param FramePtr is a pointer to a 32-bit aligned buffer where the CAN
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@ -696,91 +748,77 @@ u32 XCanFd_Recv_Mailbox(XCanFd *InstancePtr, u32 *FramePtr)
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u32 DwIndex=0;
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u32 Result;
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u32 CanEDL;
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u32 ReadIndex=0;
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u32 NoCtrlStatus;
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u32 Dlc;
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u32 Len;
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u32 NofRcsReg=0;
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u32 RcsRegNr=0;
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u32 RxBufferIndex;
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u32 CoreStatusBit;
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u32 Mask;
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/*
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* Core status bit in Receive Control Status Register starts from 16
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* th bit Location.
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*/
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u32 CoreStatusBit=16;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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NofRcsReg = XCanFd_Get_NofRxBuffers(InstancePtr);
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RxBufferIndex = XCanFd_ReadReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_ISR_OFFSET) &
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XCANFD_IXR_RXLRM_BI_MASK;
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RxBufferIndex >>= XCANFD_RXLRM_BI_SHIFT;
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CoreStatusBit = (RxBufferIndex%XCANFD_CSB_SHIFT) + XCANFD_CSB_SHIFT;
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RcsRegNr = RxBufferIndex/XCANFD_CSB_SHIFT;
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for (NoCtrlStatus = 0;NoCtrlStatus < NofRcsReg;NoCtrlStatus++) {
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Result = XCanFd_ReadReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_RCS_OFFSET(NoCtrlStatus));
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Result = XCanFd_ReadReg(InstancePtr->CanFdConfig.BaseAddress,
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XCANFD_RCS_OFFSET(RcsRegNr));
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Mask = Result & XCANFD_RCS_HCB_MASK;
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if (Result & 1<<CoreStatusBit) {
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/* Read CanFd ID*/
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FramePtr[0] = XCanFd_ReadReg(InstancePtr->CanFdConfig.
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BaseAddress,XCANFD_RXID_OFFSET(RxBufferIndex));
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while (CoreStatusBit <32) {
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if (Result & (1<< CoreStatusBit)) {
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/* Read CanFd DLC */
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FramePtr[1] = CanEDL = XCanFd_ReadReg(InstancePtr->CanFdConfig.
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BaseAddress,
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XCANFD_RXDLC_OFFSET(RxBufferIndex));
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/* Read ID from ID Register of that FIFO */
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FramePtr[0] = XCanFd_ReadReg(
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InstancePtr->CanFdConfig.
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BaseAddress,
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XCANFD_RXID_OFFSET(ReadIndex));
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Dlc = XCanFd_GetDlc2len(FramePtr[1] &
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XCANFD_DLCR_DLC_MASK);
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/* A CanFD Frame is received */
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/* Read DLC from DLC Register of that FIFO */
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FramePtr[1] = CanEDL = XCanFd_ReadReg(
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InstancePtr->CanFdConfig.
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BaseAddress,
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XCANFD_RXDLC_OFFSET(ReadIndex));
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if (CanEDL & XCANFD_DLCR_EDL_MASK) {
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Dlc = XCanFd_GetDlc2len(FramePtr[1] &
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XCANFD_DLCR_DLC_MASK);
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/* Read all Bytes from DW Register */
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/* CanFD Frame is received */
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if (CanEDL & XCANFD_DLCR_EDL_MASK) {
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/*
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* Read all Bytes from DW Register of
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* that FIFO
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*/
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for (Len = 0;Len < Dlc;Len += 4) {
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FramePtr[2+DwIndex] =
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Xil_EndianSwap32(
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XCanFd_ReadReg(
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InstancePtr->CanFdConfig.
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BaseAddress,
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(XCANFD_RXDW_OFFSET(
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ReadIndex)
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+(DwIndex*XCANFD_DW_BYTES))));
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DwIndex++;
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}
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DwIndex=0;
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}
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else {
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/* Legacy CAN Frame */
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for (Len = 0;Len < Dlc;Len += 4) {
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FramePtr[2+DwIndex] =
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Xil_EndianSwap32(
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XCanFd_ReadReg(
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InstancePtr->CanFdConfig.
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BaseAddress,
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(XCANFD_RXDW_OFFSET(ReadIndex)+
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(Len))));
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DwIndex++;
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}
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}
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Mask = Result & 0xFFFF;
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Result &= 1<<CoreStatusBit;
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Result |= Mask;
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XCanFd_WriteReg(InstancePtr->CanFdConfig.
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BaseAddress,
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XCANFD_RCS_OFFSET(NoCtrlStatus),Result);
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return XST_SUCCESS;
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for (Len = 0;Len < Dlc;Len += 4) {
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FramePtr[2+DwIndex] = Xil_EndianSwap32(
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XCanFd_ReadReg(
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InstancePtr->CanFdConfig.
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BaseAddress,
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(XCANFD_RXDW_OFFSET(
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RxBufferIndex)
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+(DwIndex*XCANFD_DW_BYTES))));
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DwIndex++;
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}
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ReadIndex++;
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CoreStatusBit++;
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DwIndex=0;
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}
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CoreStatusBit = 16;
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else {
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/* Legacy CAN Frame */
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for (Len = 0;Len < Dlc;Len += 4) {
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FramePtr[2+DwIndex] = Xil_EndianSwap32(
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XCanFd_ReadReg(
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InstancePtr->CanFdConfig.
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BaseAddress,
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(XCANFD_RXDW_OFFSET(
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RxBufferIndex)+
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(Len))));
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DwIndex++;
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}
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}
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/* Clear CSB Bit of RCS Register */
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Result = Mask | (1 << CoreStatusBit);
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XCanFd_WriteReg(InstancePtr->CanFdConfig.
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BaseAddress,XCANFD_RCS_OFFSET(RcsRegNr),Result);
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return XST_SUCCESS;
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} else {
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return XST_NO_DATA;
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}
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return XST_NO_DATA;
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}
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/*****************************************************************************/
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@ -55,7 +55,7 @@
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* - Readable Error Counters.
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* - External PHY chip required.
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* - Backward compatiable for Legacy CAN.
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* - Supports reception in Milibox and Sequential Mode
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* - Supports reception in Mailbox and Sequential Mode
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*
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* The device driver supports all the features listed above, if applicable.
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*
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@ -195,6 +195,13 @@ exclusion
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* Updated xcanfd.c while sending data when EDL is Zero.
|
||||
* Updated driver tcl file to get configurable TxBuffers.
|
||||
* (CR 861772).
|
||||
* 1.0 nsk 16/06/15 Updated XCanFd_Recv_Mailbox(), XCanFd_EnterMode()
|
||||
* XCanFd_GetMode() in xcanfd.c and Added new definition
|
||||
* for Register bits in xcanfd_hw.h and updated
|
||||
* XCanFd_IntrHandler() in xcanfd_intr.c as per new RTL.
|
||||
* Changes in RTL, Added new bits to MSR,SR,ISR,IER,ICR
|
||||
* Registers and modified TS2 bits in BTR and F_SJW bits
|
||||
* in F_BTR Registers.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -219,8 +226,14 @@ extern "C" {
|
|||
#define XCANFD_MODE_CONFIG 0x00000001 /**< Configuration mode */
|
||||
#define XCANFD_MODE_NORMAL 0x00000002 /**< Normal mode */
|
||||
#define XCANFD_MODE_LOOPBACK 0x00000004 /**< Loop Back mode */
|
||||
#define XCANFD_MODE_SLEEP 0x00000008 /**< Sleep mode */
|
||||
#define XCANFD_MODE_SNOOP 0x00000010
|
||||
#define XCANFD_MODE_SLEEP 0x00000008 /**< Sleep mode */
|
||||
#define XCANFD_MODE_SNOOP 0x00000010 /**< Snoop mode */
|
||||
#define XCANFD_MODE_ABR 0x00000020 /**< Auto Bus-Off Recovery */
|
||||
#define XCANFD_MODE_SBR 0x00000040 /**< Starut Bus-Off Recovery */
|
||||
#define XCANFD_MODE_PEE 0x00000080 /**< Protocol Exception mode */
|
||||
#define XCANFD_MODE_DAR 0x0000000A /**< Disable Auto Retransmission
|
||||
mode */
|
||||
#define XCANFD_MODE_BR 0x0000000B /**< Bus-Off Recovery Mode */
|
||||
/* @} */
|
||||
|
||||
/** @name Callback identifiers used as parameters to XCanFd_SetHandler()
|
||||
|
|
@ -237,6 +250,7 @@ extern "C" {
|
|||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/**
|
||||
* @struct
|
||||
* This typedef contains configuration information for a device.
|
||||
*/
|
||||
typedef struct {
|
||||
|
|
@ -286,6 +300,7 @@ typedef void (*XCanFd_EventHandler) (void *CallBackRef, u32 Mask);
|
|||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @struct
|
||||
* The XCanFd driver instance data. The user is required to allocate a
|
||||
* variable of this type for every CAN device in the system. A pointer
|
||||
* to a variable of this type is then passed to the driver API functions.
|
||||
|
|
@ -752,24 +767,6 @@ typedef struct {
|
|||
(XCanFd_ReadReg(InstancePtr->CanFdConfig.BaseAddress,\
|
||||
XCANFD_TIMESTAMPR_OFFSET) >> 16)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function Disables the Auto retransmissions.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XCanFd instance to be worked on.
|
||||
*
|
||||
* @return TimeStampCount
|
||||
*
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XCanFd_DisableAuto_Retransmission(InstancePtr) \
|
||||
XCanFd_WriteReg(InstancePtr->CanFdConfig.BaseAddress, XCANFD_MSR_OFFSET, \
|
||||
(XCanFd_ReadReg(InstancePtr->CanFdConfig.BaseAddress, XCANFD_MSR_OFFSET) \
|
||||
| XCANFD_DAR_MASK));
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
|
|
|
|||
|
|
@ -45,10 +45,14 @@
|
|||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- ---------- -----------------------------------------------
|
||||
* ----- ---- ---------- -------------------------------------------------------
|
||||
* 1.0 nsk 06/04/2015 First release
|
||||
* 1.0 nsk 15/05/2015 Modified XCANFD_BTR_TS1_MASK
|
||||
* (CR 861772).
|
||||
* 1.0 nsk 16/06/2015 Added New definitions for Register
|
||||
* bits since RTL has changed.RTL Changes,Added
|
||||
* new bits to MSR,SR,ISR,IER,ICR Registers and modified
|
||||
* TS2 bits in BTR and F_SJW bits in F_BTR Registers.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
|
|
@ -110,6 +114,8 @@ extern "C" {
|
|||
*/
|
||||
#define XCANFD_RCS2_OFFSET 0x0B8 /**< Rx Buffer Control Status 2 Register
|
||||
*/
|
||||
#define XCANFD_RCS_HCB_MASK 0xFFFF /**< Rx Buffer Control Status Register
|
||||
Host Control Bit Mask */
|
||||
#define XCANFD_RXBFLL1_OFFSET 0x0C0 /**< Rx Buffer Full Interrupt Enable
|
||||
Register */
|
||||
#define XCANFD_RXBFLL2_OFFSET 0x0C4 /**< Rx Buffer Full Interrupt Enable
|
||||
|
|
@ -679,6 +685,11 @@ extern "C" {
|
|||
#define XCANFD_MSR_DAR_MASK 0x00000010 /**< Disable Auto-Retransmission
|
||||
Select Mask */
|
||||
#define XCANFD_MSR_SNOOP_MASK 0x00000004 /**< Snoop Mode Select Mask */
|
||||
#define XCANFD_MSR_DPEE_MASK 0x00000020 /**< Protocol Exception Event
|
||||
Mask */
|
||||
#define XCANFD_MSR_SBR_MASK 0x00000040 /**< Start Bus-Off Recovery Mask */
|
||||
#define XCANFD_MSR_ABR_MASK 0x00000080 /**< Auto Bus-Off Recovery Mask */
|
||||
#define XCANFD_MSR_CONFIG_MASK 0x000000F8 /**< Configuration Mode Mask */
|
||||
/* @} */
|
||||
|
||||
/** @name Baud Rate Prescaler register
|
||||
|
|
@ -692,7 +703,7 @@ extern "C" {
|
|||
*/
|
||||
#define XCANFD_BTR_SJW_MASK 0x000F0000 /**< Sync Jump Width Mask */
|
||||
#define XCANFD_BTR_SJW_SHIFT 16 /**< Sync Jump Width Shift */
|
||||
#define XCANFD_BTR_TS2_MASK 0x00001F00 /**< Time Segment 2 Mask */
|
||||
#define XCANFD_BTR_TS2_MASK 0x00000F00 /**< Time Segment 2 Mask */
|
||||
#define XCANFD_BTR_TS2_SHIFT 8 /**< Time Segment 2 Shift */
|
||||
#define XCANFD_BTR_TS1_MASK 0x0000003F /**< Time Segment 1 Mask */
|
||||
#define XCANFD_F_BRPR_TDCMASK 0x00001F00 /**< Tranceiver Delay
|
||||
|
|
@ -705,7 +716,7 @@ extern "C" {
|
|||
/** @name Fast Bit Timing Register
|
||||
* @{
|
||||
*/
|
||||
#define XCANFD_F_BTR_SJW_MASK 0x00030000 /**< Sync Jump Width Mask */
|
||||
#define XCANFD_F_BTR_SJW_MASK 0x00070000 /**< Sync Jump Width Mask */
|
||||
#define XCANFD_F_BTR_SJW_SHIFT 16 /**< Sync Jump Width Shift */
|
||||
#define XCANFD_F_BTR_TS2_MASK 0x00000700 /**< Time Segment 2 Mask */
|
||||
#define XCANFD_F_BTR_TS2_SHIFT 8 /**< Time Segment 2 Shift */
|
||||
|
|
@ -749,13 +760,23 @@ extern "C" {
|
|||
#define XCANFD_SR_SLEEP_MASK 0x00000004 /**< Sleep Mode Mask */
|
||||
#define XCANFD_SR_LBACK_MASK 0x00000002 /**< Loop Back Mode Mask */
|
||||
#define XCANFD_SR_CONFIG_MASK 0x00000001 /**< Configuration Mode Mask */
|
||||
#define XCANFD_SR_PEE_CONFIG_MASK 0x00000200 /**< Protocol Exception Mode
|
||||
Indicator Mask */
|
||||
#define XCANFD_SR_BSFR_CONFIG_MASK 0x00000400 /**< Bus-Off recovery Mode
|
||||
Indicator Mask */
|
||||
#define XCANFD_SR_NISO_MASK 0x00000800 /**< Non-ISO Core Mask */
|
||||
/* @} */
|
||||
|
||||
/** @name Interrupt Status/Enable/Clear Register
|
||||
* @{
|
||||
*/
|
||||
#define XCANFD_IXR_RXBOFLW_BI_MASK 0x3F000000 /**< Rx Buffer index for Overflow
|
||||
Intr Mask (Mailbox Mode))*/
|
||||
(Mailbox Mode) */
|
||||
#define XCANFD_IXR_RXLRM_BI_MASK 0x00FC0000 /**< Rx Buffer index for Last
|
||||
Received Message (Mailbox
|
||||
Mode) */
|
||||
#define XCANFD_RXLRM_BI_SHIFT 18 /**< Rx Buffer Index Shift Value */
|
||||
#define XCANFD_CSB_SHIFT 16 /**< Core Status Bit Shift Value */
|
||||
#define XCANFD_IXR_RXMNF_MASK 0x00020000 /**< Rx Match Not Finished Intr
|
||||
Mask */
|
||||
#define XCANFD_IXR_RXBOFLW_MASK 0x00010000 /**< Rx Buffer Overflow interrupt
|
||||
|
|
@ -778,7 +799,11 @@ extern "C" {
|
|||
#define XCANFD_IXR_TXOK_MASK 0x00000002 /**< TX Successful Interrupt Mask
|
||||
*/
|
||||
#define XCANFD_IXR_ARBLST_MASK 0x00000001 /**< Arbitration Lost Intr Mask */
|
||||
#define XCANFD_IXR_ALL (XCANFD_IXR_RXBOFLW_BI_MASK | \
|
||||
#define XCANFD_IXR_PEE_MASK 0x00000004 /**< Protocol Exception Intr Mask */
|
||||
#define XCANFD_IXR_BSRD_MASK 0x00000008 /**< Bus-Off recovery done Intr
|
||||
Mask */
|
||||
#define XCANFD_IXR_ALL (XCANFD_IXR_PEE_MASK | \
|
||||
XCANFD_IXR_BSRD_MASK | \
|
||||
XCANFD_IXR_RXMNF_MASK | \
|
||||
XCANFD_IXR_RXBOFLW_MASK | \
|
||||
XCANFD_IXR_RXRBF_MASK | \
|
||||
|
|
|
|||
|
|
@ -43,9 +43,12 @@
|
|||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- --------- -----------------------------------------------
|
||||
* ----- ---- --------- -------------------------------------------------------
|
||||
* 1.0 nsk 06/04/15 First release
|
||||
*
|
||||
* 1.0 nsk 16/06/15 Updated XCanFd_IntrHandler() since RTL has
|
||||
* changed. RTL Changes,Added new bits to MSR,SR,ISR,
|
||||
* IER,ICR Registers and modified TS2 bits in
|
||||
* BTR and F_SJW bits in F_BTR Registers.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
|
@ -474,6 +477,7 @@ void XCanFd_IntrHandler(void *InstancePtr)
|
|||
* - Enter sleep mode
|
||||
* - Enter Bus off status
|
||||
* - Arbitration is lost
|
||||
* - Protocol Exception Event
|
||||
*
|
||||
* If so, call event callback provided by upper level.
|
||||
*/
|
||||
|
|
@ -484,21 +488,12 @@ void XCanFd_IntrHandler(void *InstancePtr)
|
|||
XCANFD_IXR_WKUP_MASK |
|
||||
XCANFD_IXR_SLP_MASK | XCANFD_IXR_BSOFF_MASK |
|
||||
XCANFD_IXR_RXFOFLW_MASK | XCANFD_IXR_ARBLST_MASK |
|
||||
XCANFD_IXR_RXRBF_MASK);
|
||||
XCANFD_IXR_RXRBF_MASK |
|
||||
XCANFD_IXR_PEE_MASK |
|
||||
XCANFD_IXR_BSRD_MASK);
|
||||
if (EventIntr) {
|
||||
|
||||
CanPtr->EventHandler(CanPtr->EventRef, EventIntr);
|
||||
|
||||
if ((EventIntr & XCANFD_IXR_BSOFF_MASK)) {
|
||||
|
||||
/*
|
||||
* Event callback should reset whole device if "Enter
|
||||
* Bus Off Status" interrupt occurred. All pending
|
||||
* interrupts are cleared and no further checking and
|
||||
* handling of other interrupts is needed any more.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue