dp: Fixed typos.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion
Nava kishore Manne
parent
ddabc3c5ab
commit
062b550ad6
6 changed files with 29 additions and 29 deletions
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@ -407,7 +407,7 @@ u32 XDp_TxEstablishLink(XDp *InstancePtr)
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return XST_FAILURE;
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}
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/* Reenable main link after training if required. */
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/* Re-enable main link after training if required. */
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if (ReenableMainLink) {
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XDp_TxEnableMainLink(InstancePtr);
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}
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@ -417,8 +417,8 @@ u32 XDp_TxEstablishLink(XDp *InstancePtr)
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/******************************************************************************/
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/**
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* This function checks if the reciever's DisplayPort Configuration Data (DPCD)
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* indicates the reciever has achieved and maintained clock recovery, channel
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* This function checks if the receiver's DisplayPort Configuration Data (DPCD)
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* indicates the receiver has achieved and maintained clock recovery, channel
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* equalization, symbol lock, and interlane alignment for all lanes currently in
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* use.
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*
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@ -1424,7 +1424,7 @@ void XDp_TxSetPhyPolarityLane(XDp *InstancePtr, u8 Lane, u8 Polarity)
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/******************************************************************************/
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/**
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* This function checks if the reciever's internal registers indicate that link
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* This function checks if the receiver's internal registers indicate that link
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* training has complete. That is, training has achieved channel equalization,
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* symbol lock, and interlane alignment for all lanes currently in use.
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*
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@ -2047,7 +2047,7 @@ static u32 XDp_TxRunTraining(XDp *InstancePtr)
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* - XDP_TX_TS_CHANNEL_EQUALIZATION if the clock recovery sequence
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* completed successfully.
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* - XDP_TX_TS_FAILURE if writing the drive settings to the RX
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* device was unsuccesful.
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* device was unsuccessful.
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* - XDP_TX_TS_ADJUST_LINK_RATE if the clock recovery sequence
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* did not complete successfully.
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*
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@ -2158,7 +2158,7 @@ static XDp_TxTrainingState XDp_TxTrainingStateClockRecovery(XDp *InstancePtr)
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* @return The next training state:
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* - XDP_TX_TS_SUCCESS if training succeeded.
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* - XDP_TX_TS_FAILURE if writing the drive settings to the RX
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* device was unsuccesful.
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* device was unsuccessful.
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* - XDP_TX_TS_ADJUST_LINK_RATE if, after 5 loop iterations, the
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* channel equalization sequence did not complete successfully.
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*
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@ -2214,8 +2214,8 @@ static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization(
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break;
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}
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/* Check that all lanes stihave accomplished channel
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* equalization, symbol lock, and interlane alignment. */
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/* Check if all lanes have accomplished channel equalization,
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* symbol lock, and interlane alignment. */
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Status = XDp_TxCheckChannelEqualization(InstancePtr,
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InstancePtr->TxInstance.LinkConfig.LaneCount);
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if (Status == XST_SUCCESS) {
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@ -2232,8 +2232,8 @@ static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization(
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IterationCount++;
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}
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/* Tried MaxIteration times with no success. Try a reduced bitrate
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* first, then reduce the number of lanes. */
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/* Tried 5 times with no success. Try a reduced bitrate first, then
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* reduce the number of lanes. */
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return XDP_TX_TS_ADJUST_LINK_RATE;
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}
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@ -2673,7 +2673,7 @@ static u32 XDp_TxAdjVswingPreemp(XDp *InstancePtr)
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/* Verify that the voltage swing and pre-emphasis combination is
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* allowed. Some combinations will result in a differential peak-to-peak
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* voltage that is outside the permissable range. See the VESA
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* voltage that is outside the permissible range. See the VESA
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* DisplayPort v1.2 Specification, section 3.1.5.2.
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* The valid combinations are:
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* PE=0 PE=1 PE=2 PE=3
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@ -168,7 +168,7 @@
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* depending on whether a an HPD event on an HPD pulse event occurred.
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*
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* The DisplayPort TX's XDP_TX_INTERRUPT_STATUS register indicates the type of
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* interrupt that has occured, and the XDp_TxInterruptHandler will use this
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* interrupt that has occurred, and the XDp_TxInterruptHandler will use this
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* information to decide which handler to call. An HPD event is identified if
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* bit XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is
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* identified from the XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.
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@ -323,7 +323,7 @@ u32 XDp_TxGetDispIdDataBlock(u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr)
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for (Index = XDP_TX_DISPID_PAYLOAD_START; Index < DispIdSize; Index++) {
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DataBlock = &DisplayIdRaw[Index];
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/* Check if the tag mataches the current section data block. */
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/* Check if the tag matches the current section data block. */
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if (DataBlock[XDP_TX_DISPID_DB_SEC_TAG] == SectionTag) {
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*DataBlockPtr = DataBlock;
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return XST_SUCCESS;
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@ -122,14 +122,14 @@
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#define XDP_TX_USER_FIFO_OVERFLOW 0x110 /**< Indicates an overflow in
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user FIFO. */
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#define XDP_TX_INTERRUPT_SIG_STATE 0x130 /**< The raw signal values for
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interupt events. */
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interrupt events. */
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#define XDP_TX_AUX_REPLY_DATA 0x134 /**< Reply data received during
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the AUX reply. */
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#define XDP_TX_AUX_REPLY_CODE 0x138 /**< Reply code received from
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the most recent AUX
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command. */
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#define XDP_TX_AUX_REPLY_COUNT 0x13C /**< Number of reply
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transactions receieved
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transactions received
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over AUX. */
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#define XDP_TX_INTERRUPT_STATUS 0x140 /**< Status for interrupt
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events. */
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@ -265,7 +265,7 @@
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#define XDP_TX_PHY_POSTCURSOR_LANE_3 0x258 /**< Controls the post-cursor
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level. */
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#define XDP_TX_PHY_STATUS 0x280 /**< Current PHY status. */
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#define XDP_TX_GT_DRP_COMMAND 0x2A0 /**< Provides acces to the GT
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#define XDP_TX_GT_DRP_COMMAND 0x2A0 /**< Provides access to the GT
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DRP ports. */
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#define XDP_TX_GT_DRP_READ_DATA 0x2A4 /**< Provides access to GT DRP
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read data. */
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@ -1292,7 +1292,7 @@
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updated internally. */
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#define XDP_RX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK \
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0x2 /**< When set, the long I2C
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write data transfwers
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write data transfers
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are responded to using
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DEFER instead of partial
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ACKs. */
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@ -1749,7 +1749,7 @@
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0x40000000 /**< Configure RX_PHY_POLARITY
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for lane 3. */
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#define XDP_RX_PHY_CONFIG_GT_ALL_RESET_MASK \
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0x00000003 /**< Rest GT and PHY. */
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0x00000003 /**< Reset GT and PHY. */
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/* 0x208: PHY_STATUS */
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#define XDP_RX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \
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0x00000003 /**< Reset done for lanes
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@ -1792,17 +1792,17 @@
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0x00008000 /**< RX voltage low on lane
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3. */
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#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK \
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0x00010000 /**< Lane aligment status for
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lane 0. */
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0x00010000 /**< Lane alignment status
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for lane 0. */
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#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK \
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0x00020000 /**< Lane aligment status for
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lane 1. */
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0x00020000 /**< Lane alignment status
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for lane 1. */
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#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK \
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0x00040000 /**< Lane aligment status for
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lane 2. */
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0x00040000 /**< Lane alignment status
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for lane 2. */
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#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK \
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0x00080000 /**< Lane aligment status for
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lane 3. */
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0x00080000 /**< Lane alignment status
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for lane 3. */
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#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_0_MASK \
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0x00100000 /**< Symbol lock status for
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lane 0. */
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@ -94,7 +94,7 @@ typedef struct
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message in the transaction. */
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u8 EndOfMsgTransaction; /**< This message is the last sideband
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message in the transaction. */
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u8 MsgSequenceNum; /**< Identifies invidiual message
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u8 MsgSequenceNum; /**< Identifies individual message
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transactions to a given
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DisplayPort device. */
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u8 Crc; /**< The cyclic-redundancy check (CRC)
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@ -2892,7 +2892,7 @@ static u32 XDp_RxSetRemoteIicReadReply(XDp *InstancePtr, XDp_SidebandMsg *Msg)
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/******************************************************************************/
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/**
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* This function will set and format a sideband message structure for replying
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* with a NAK
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* with a NACK.
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*
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* @param Msg is a pointer to the message to be formatted.
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*
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@ -886,7 +886,7 @@ static void XDp_TxCalculateTs(XDp *InstancePtr, u8 Stream, u8 BitsPerPixel)
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((double)BitsPerPixel / 8);
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LinkBw = (LinkConfig->LaneCount * LinkConfig->LinkRate * 27);
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/* Calculate the payload bandiwdth number (PBN). */
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/* Calculate the payload bandwidth number (PBN). */
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InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstPbn =
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1.006 * PeakPixelBw * ((double)64 / 54);
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/* Ceil - round up if required, avoiding overhead of math.h. */
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