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vphy: Added input pixels per clock configuration parameter.

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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-10-20 23:41:39 -07:00 • committed by Nava kishore Manne
parent 67d77a7b52
commit 085aabda2c
3 changed files with 7 additions and 4 deletions
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6
XilinxProcessorIPLib/drivers/vphy/data/vphy.tcl
View file

@ -31,9 +31,9 @@
##*****************************************************************************/
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "XVPHY" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "Transceiver" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL"
::hsi::utils::define_config_file $drv_handle "xvphy_g.c" "XVphy" "DEVICE_ID" "C_BASEADDR" "TRANSCEIVER" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL"
xdefine_canonical_xpars $drv_handle "xparameters.h" "VPHY" "DEVICE_ID" "C_BASEADDR" "Transceiver" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL"
xdefine_include_file $drv_handle "xparameters.h" "XVPHY" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "Transceiver" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL" "C_INPUT_PIXELS_PER_CLOCK"
::hsi::utils::define_config_file $drv_handle "xvphy_g.c" "XVphy" "DEVICE_ID" "C_BASEADDR" "TRANSCEIVER" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL" "C_INPUT_PIXELS_PER_CLOCK"
xdefine_canonical_xpars $drv_handle "xparameters.h" "VPHY" "DEVICE_ID" "C_BASEADDR" "Transceiver" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL" "C_INPUT_PIXELS_PER_CLOCK"
}
#

2
XilinxProcessorIPLib/drivers/vphy/src/xvphy.h
View file

@ -508,6 +508,8 @@ typedef struct {
u8 DruIsPresent; /**< A data recovery unit (DRU) exists
in the design .*/
XVphy_PllRefClkSelType DruRefClkSel; /**< DRU REFCLK selection. */
XVidC_PixelsPerClock Ppc; /**< Number of input pixels per
clock. */
} XVphy_Config;
/* Forward declaration. */

3
XilinxProcessorIPLib/drivers/vphy/src/xvphy_g.c
View file

@ -59,6 +59,7 @@ XVphy_Config XVphy_ConfigTable[] =
XPAR_VID_PHY_CONTROLLER_0_TX_PLL_SELECTION,
XPAR_VID_PHY_CONTROLLER_0_RX_PLL_SELECTION,
XPAR_VID_PHY_CONTROLLER_0_NIDRU,
XPAR_VID_PHY_CONTROLLER_0_NIDRU_REFCLK_SEL
XPAR_VID_PHY_CONTROLLER_0_NIDRU_REFCLK_SEL,
XPAR_VID_PHY_CONTROLLER_0_INPUT_PIXELS_PER_CLOCK
}
};