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vphy: gt: Modified CDR configuration.

Browse source 
For:
- GTHE3 (DisplayPort), and
- GTHE2.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-11-06 01:25:08 -07:00 • committed by Nava kishore Manne
parent 6ff35ba5b2
commit 0b34da9303
2 changed files with 15 additions and 21 deletions
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25
XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe2.c
View file

@ -169,6 +169,7 @@ const XVphy_GtConfig Gthe2Config = {
u32 XVphy_Gthe2CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
XVphy_Channel *ChPtr;
u32 PllClkInFreqHz;
/* Set CDR values only for CPLLs. */
if ((ChId < XVPHY_CHANNEL_ID_CH1) || (ChId > XVPHY_CHANNEL_ID_CH4)) {
@ -176,22 +177,20 @@ u32 XVphy_Gthe2CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
}
ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];
PllClkInFreqHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId,
ChPtr->CpllRefClkSel);
/* Update the RXCDR_CFG2 settings. */
ChPtr->PllParams.Cdr[0] = 0x0020;
ChPtr->PllParams.Cdr[1] = 0x07FE;
ChPtr->PllParams.Cdr[3] = (ChPtr->RxOutDiv == 1) ? 0xC208 : 0xC220;
ChPtr->PllParams.Cdr[4] = 0x0018;
/* RxOutDiv = 1 => Cdr[2] = 0x2000
* RxOutDiv = 2 => Cdr[2] = 0x1000
* RxOutDiv = 4 => Cdr[2] = 0x0800
* RxOutDiv = 8 => Cdr[2] = 0x0400 */
u8 RxOutDiv = ChPtr->RxOutDiv;
ChPtr->PllParams.Cdr[2] = 0x2000;
while (RxOutDiv >>= 1) {
ChPtr->PllParams.Cdr[2] >>= 1;
ChPtr->PllParams.Cdr[0] = 0x0018;
if (PllClkInFreqHz == 270000000) {
ChPtr->PllParams.Cdr[1] = 0xC208;
}
else {
ChPtr->PllParams.Cdr[1] = 0xC220;
}
ChPtr->PllParams.Cdr[2] = 0x1000;
ChPtr->PllParams.Cdr[3] = 0x07FE;
ChPtr->PllParams.Cdr[4] = 0x0020;
return XST_SUCCESS;
}

11
XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe3.c
View file

@ -183,20 +183,15 @@ u32 XVphy_Gthe3CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_DP) {
PllClkInFreqHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId,
ChPtr->CpllRefClkSel);
if ((ChPtr->RxOutDiv == 1) && (PllClkInFreqHz == 270000000)) {
if (PllClkInFreqHz == 270000000) {
ChPtr->PllParams.Cdr[2] = 0x0766;
}
else if ((ChPtr->RxOutDiv == 2) &&
(PllClkInFreqHz == 135000000)) {
else if (PllClkInFreqHz == 135000000) {
ChPtr->PllParams.Cdr[2] = 0x0756;
}
/* RBR does not use DP159 forwarded clock and expects 162MHz. */
else if (ChPtr->RxOutDiv == 2) {
ChPtr->PllParams.Cdr[2] = 0x0721;
}
else {
Status = XST_FAILURE;
ChPtr->PllParams.Cdr[2] = 0x0721;
}
}
else if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_HDMI) {