v_hdmitx: Improved stability.
Contributions from Marco Groeneveld (mgroenev@xilinx.com). Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com> Acked-by: Srikanth Vemula <svemula@xilinx.com>
This commit is contained in:
parent
c351438007
commit
13ae615fea
9 changed files with 1580 additions and 1582 deletions
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@ -32,18 +32,18 @@
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proc generate {drv_handle} {
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xdefine_include_file $drv_handle "xparameters.h" "XV_HdmiTx" \
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"NUM_INSTANCES" \
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"DEVICE_ID" \
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"C_BASEADDR" \
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"C_HIGHADDR"
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"NUM_INSTANCES" \
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"DEVICE_ID" \
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"C_BASEADDR" \
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"C_HIGHADDR"
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xdefine_config_file $drv_handle "xv_hdmitx_g.c" "XV_HdmiTx" \
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"DEVICE_ID" \
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"C_BASEADDR"
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"DEVICE_ID" \
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"C_BASEADDR"
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xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_HdmiTx" \
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"NUM_INSTANCES" \
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"DEVICE_ID" \
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"C_BASEADDR" \
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"C_HIGHADDR"
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}
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"NUM_INSTANCES" \
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"DEVICE_ID" \
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"C_BASEADDR" \
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"C_HIGHADDR"
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}
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12
XilinxProcessorIPLib/drivers/v_hdmitx/src/Makefile
Executable file → Normal file
12
XilinxProcessorIPLib/drivers/v_hdmitx/src/Makefile
Executable file → Normal file
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@ -16,13 +16,13 @@ OUTS = *.o
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libs:
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echo "Compiling v_hdmitx"
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$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
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$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
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make clean
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echo "Compiling v_hdmitx"
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$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
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$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
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make clean
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include:
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${CP} ${INCLUDEFILES} ${INCLUDEDIR}
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${CP} ${INCLUDEFILES} ${INCLUDEDIR}
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clean:
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rm -rf ${OUTS}
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rm -rf ${OUTS}
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1875
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.c
Executable file → Normal file
1875
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.c
Executable file → Normal file
File diff suppressed because it is too large
Load diff
508
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.h
Executable file → Normal file
508
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.h
Executable file → Normal file
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@ -126,8 +126,8 @@
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*
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******************************************************************************/
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#ifndef XV_HDMITX_H_
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#define XV_HDMITX_H_ /**< Prevent circular inclusions
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* by using protection macros */
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#define XV_HDMITX_H_ /**< Prevent circular inclusions
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* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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@ -154,10 +154,10 @@ extern "C" {
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* interrupt requests from peripheral.
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*/
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typedef enum {
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XV_HDMITX_HANDLER_CONNECT = 1, // Handler for connect
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XV_HDMITX_HANDLER_VS, // Handler for vsync
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XV_HDMITX_HANDLER_STREAM_DOWN, // Handler for stream down
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XV_HDMITX_HANDLER_STREAM_UP // Handler for stream up
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XV_HDMITX_HANDLER_CONNECT = 1, // Handler for connect
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XV_HDMITX_HANDLER_VS, // Handler for vsync
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XV_HDMITX_HANDLER_STREAM_DOWN, // Handler for stream down
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XV_HDMITX_HANDLER_STREAM_UP // Handler for stream up
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} XV_HdmiTx_HandlerType;
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/*@}*/
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@ -165,8 +165,8 @@ typedef enum {
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* @{
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*/
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typedef enum {
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XV_HDMITX_STATE_STREAM_DOWN, // Stream down
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XV_HDMITX_STATE_STREAM_UP // Stream up
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XV_HDMITX_STATE_STREAM_DOWN, // Stream down
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XV_HDMITX_STATE_STREAM_UP // Stream up
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} XV_HdmiTx_State;
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/**
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@ -174,91 +174,91 @@ typedef enum {
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* Each HDMI TX device should have a configuration structure associated.
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*/
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typedef struct {
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u16 DeviceId; /**< DeviceId is the unique ID of the HDMI TX core */
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u32 BaseAddress; /**< BaseAddress is the physical
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* base address of the core's registers */
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u16 DeviceId; /**< DeviceId is the unique ID of the HDMI TX core */
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u32 BaseAddress; /**< BaseAddress is the physical
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* base address of the core's registers */
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} XV_HdmiTx_Config;
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/**
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* This typedef contains Video identification information in tabular form.
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*/
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typedef struct {
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XVidC_VideoMode VmId; /**< Video mode/Resolution ID */
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u8 Vic; /**< Video Identification code */
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XVidC_VideoMode VmId; /**< Video mode/Resolution ID */
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u8 Vic; /**< Video Identification code */
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} XV_HdmiTx_VicTable;
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/**
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* This typedef contains Video identification information in tabular form.
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*/
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typedef struct {
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XVidC_VideoMode VmId; /**< Video mode/Resolution ID */
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XVidC_VideoTiming Timing; /**< Video Timing*/
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XVidC_VideoMode VmId; /**< Video mode/Resolution ID */
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XVidC_VideoTiming Timing; /**< Video Timing*/
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} XV_HdmiTx_ReducedBlankingTable;
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/**
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* This typedef contains audio stream specific data structure
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*/
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typedef struct {
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u8 Channels; //< Video Identification code */
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u8 Channels; //< Video Identification code */
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} XV_HdmiTx_AudioStream;
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/**
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* This typedef contains HDMI TX stream specific data structure.
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*/
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typedef struct {
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XVidC_VideoStream Video; /**< Video stream for HDMI TX */
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XV_HdmiTx_AudioStream Audio; /**< Audio stream for HDMI TX */
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u8 Vic; /**< Video Identification code
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flag */
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u8 IsHdmi; /**< HDMI flag. 1 - HDMI Stream,
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0 - DVI Stream */
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u8 IsHdmi20; /**< HDMI 2.0 flag */
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u8 IsScrambled; /**< Scrambler flag
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1 - scrambled data , 0 - non scrambled data */
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u32 TMDSClock; /**< TMDS clock */
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u8 TMDSClockRatio; /**< TMDS clock ration
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0 - 1/10, 1 - 1/40 */
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u32 PixelClk; /**< Pixel Clock */
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XV_HdmiTx_State State; /**< State */
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u8 IsConnected; /**< Connected flag.
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This flag is set when the cable is connected */
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u8 SampleRate; /**< Sample rate */
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XVidC_VideoStream Video; /**< Video stream for HDMI TX */
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XV_HdmiTx_AudioStream Audio; /**< Audio stream for HDMI TX */
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u8 Vic; /**< Video Identification code
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flag */
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u8 IsHdmi; /**< HDMI flag. 1 - HDMI Stream,
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0 - DVI Stream */
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u8 IsHdmi20; /**< HDMI 2.0 flag */
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u8 IsScrambled; /**< Scrambler flag
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1 - scrambled data , 0 - non scrambled data */
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u32 TMDSClock; /**< TMDS clock */
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u8 TMDSClockRatio; /**< TMDS clock ration
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0 - 1/10, 1 - 1/40 */
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u32 PixelClk; /**< Pixel Clock */
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XV_HdmiTx_State State; /**< State */
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u8 IsConnected; /**< Connected flag.
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This flag is set when the cable is connected */
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u8 SampleRate; /**< Sample rate */
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} XV_HdmiTx_Stream;
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/**
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* This typedef contains Auxiliary header information for infoframe.
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*/
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typedef union {
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u32 Data; /**< AUX header data field */
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u8 Byte[4]; /**< AUX header byte field */
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u32 Data; /**< AUX header data field */
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u8 Byte[4]; /**< AUX header byte field */
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} XV_HdmiTx_AuxHeader;
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/**
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* This typedef contains Auxiliary data information for infoframe.
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*/
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typedef union {
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u32 Data[8]; /**< AUX data field */
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u8 Byte[32]; /**< AUX data byte field */
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u32 Data[8]; /**< AUX data field */
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u8 Byte[32]; /**< AUX data byte field */
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} XV_HdmiTx_AuxData;
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/**
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* This typedef holds HDMI TX's Auxiliary peripheral specific data structure.
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*/
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typedef struct {
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XV_HdmiTx_AuxHeader Header; /**< AUX header field */
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XV_HdmiTx_AuxData Data; /**< AUX data field */
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XV_HdmiTx_AuxHeader Header; /**< AUX header field */
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XV_HdmiTx_AuxData Data; /**< AUX data field */
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} XV_HdmiTx_Aux;
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/**
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* Callback type for Vsync event interrupt.
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*
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* @param CallbackRef is a callback reference passed in by the upper
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* layer when setting the callback functions, and passed back to
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* the upper layer when the callback is invoked.
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* @param CallbackRef is a callback reference passed in by the upper
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* layer when setting the callback functions, and passed back to
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* the upper layer when the callback is invoked.
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*
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* @return None.
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* @return None.
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*
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* @note None.
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* @note None.
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*
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*/
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typedef void (*XV_HdmiTx_Callback)(void *CallbackRef);
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* HDMI TX core in use.
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*/
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typedef struct {
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XV_HdmiTx_Config Config; /**< Hardware Configuration */
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u32 IsReady; /**< Core and the driver instance are initialized */
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XV_HdmiTx_Config Config; /**< Hardware Configuration */
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u32 IsReady; /**< Core and the driver instance are initialized */
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/* Callbacks */
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XV_HdmiTx_Callback ConnectCallback; /**< Callback for connect event
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interrupt */
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void *ConnectRef; /**< To be passed to the connect
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interrupt callback */
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u32 IsConnectCallbackSet; /**< Set flag. This flag is set
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to true when the callback has been registered */
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/* Callbacks */
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XV_HdmiTx_Callback ConnectCallback; /**< Callback for connect event
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interrupt */
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void *ConnectRef; /**< To be passed to the connect
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interrupt callback */
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u32 IsConnectCallbackSet; /**< Set flag. This flag is set
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to true when the callback has been registered */
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XV_HdmiTx_Callback VsCallback; /**< Callback for Vsync event
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interrupt */
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void *VsRef; /**< To be passed to the Vsync
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interrupt callback */
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u32 IsVsCallbackSet; /**< Set flag. This flag is set to
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true when the callback has been registered */
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XV_HdmiTx_Callback VsCallback; /**< Callback for Vsync event
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interrupt */
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void *VsRef; /**< To be passed to the Vsync
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interrupt callback */
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u32 IsVsCallbackSet; /**< Set flag. This flag is set to
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true when the callback has been registered */
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XV_HdmiTx_Callback StreamDownCallback; /**< Callback for stream down
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callback */
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void *StreamDownRef; /**< To be passed to the stream
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down callback */
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u32 IsStreamDownCallbackSet; /**< Set flag. This flag is set to
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true when the callback has been registered */
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XV_HdmiTx_Callback StreamDownCallback; /**< Callback for stream down
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callback */
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void *StreamDownRef; /**< To be passed to the stream
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down callback */
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u32 IsStreamDownCallbackSet; /**< Set flag. This flag is set to
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true when the callback has been registered */
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XV_HdmiTx_Callback StreamUpCallback; /**< Callback for stream up
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callback */
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void *StreamUpRef; /**< To be passed to the stream up
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callback */
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u32 IsStreamUpCallbackSet; /**< Set flag. This flag is set to
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true when the callback has been registered */
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XV_HdmiTx_Callback StreamUpCallback; /**< Callback for stream up
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callback */
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void *StreamUpRef; /**< To be passed to the stream up
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callback */
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u32 IsStreamUpCallbackSet; /**< Set flag. This flag is set to
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true when the callback has been registered */
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/* Aux peripheral specific */
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volatile XV_HdmiTx_Aux Aux; /**< AUX peripheral information */
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/* Aux peripheral specific */
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volatile XV_HdmiTx_Aux Aux; /**< AUX peripheral information */
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/* HDMI TX stream */
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XV_HdmiTx_Stream Stream; /**< HDMI TX stream information */
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u32 CpuClkFreq; /**< CPU Clock frequency */
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/* HDMI TX stream */
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XV_HdmiTx_Stream Stream; /**< HDMI TX stream information */
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u32 CpuClkFreq; /* CPU Clock frequency */
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} XV_HdmiTx;
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*
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* This macro asserts or releases the HDMI TX reset.
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*
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* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
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* @param Reset specifies TRUE/FALSE value to either assert or
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* release HDMI TX reset.
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* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
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* @param Reset specifies TRUE/FALSE value to either assert or
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* release HDMI TX reset.
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*
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* @return None.
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* @return None.
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*
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* @note The reset output of the PIO is inverted. When the system is
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* in reset, the PIO output is cleared and this will reset the
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* HDMI RX. Therefore, clearing the PIO reset output will assert
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* the HDMI link and video reset.
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* C-style signature:
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* void XV_HdmiTx_Reset(XV_HdmiTx *InstancePtr, u8 Reset)
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* @note The reset output of the PIO is inverted. When the system is
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* in reset, the PIO output is cleared and this will reset the
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* HDMI RX. Therefore, clearing the PIO reset output will assert
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* the HDMI link and video reset.
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* C-style signature:
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* void XV_HdmiTx_Reset(XV_HdmiTx *InstancePtr, u8 Reset)
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*
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******************************************************************************/
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#define XV_HdmiTx_Reset(InstancePtr, Reset) \
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{ \
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if (Reset) { \
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_OUT_CLR_OFFSET), (XV_HDMITX_PIO_OUT_RST_MASK)); \
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} \
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else { \
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_RST_MASK)); \
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} \
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if (Reset) { \
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_OUT_CLR_OFFSET), (XV_HDMITX_PIO_OUT_RST_MASK)); \
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} \
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else { \
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_RST_MASK)); \
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} \
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}
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/*****************************************************************************/
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*
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* This macro controls the HDMI TX Scrambler.
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*
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* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
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* @param SetClr specifies TRUE/FALSE value to either set ON or clear
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* Scrambler.
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* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
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* @param SetClr specifies TRUE/FALSE value to either set ON or clear
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* Scrambler.
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*
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* @return None.
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* @return None.
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*
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* @note C-style signature:
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* void XV_HdmiTx_SetScrambler(XV_HdmiTx *InstancePtr, u8 SetClr)
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* @note C-style signature:
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* void XV_HdmiTx_SetScrambler(XV_HdmiTx *InstancePtr, u8 SetClr)
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*
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******************************************************************************/
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#define XV_HdmiTx_SetScrambler(InstancePtr, SetClr) \
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{ \
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if (SetClr) { \
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_SCRM_MASK)); \
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(InstancePtr)->Stream.IsScrambled = (TRUE); \
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} \
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else { \
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_OUT_CLR_OFFSET), (XV_HDMITX_PIO_OUT_SCRM_MASK)); \
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(InstancePtr)->Stream.IsScrambled = (FALSE); \
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} \
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if (SetClr) { \
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_SCRM_MASK)); \
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(InstancePtr)->Stream.IsScrambled = (TRUE); \
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} \
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else { \
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_OUT_CLR_OFFSET), (XV_HDMITX_PIO_OUT_SCRM_MASK)); \
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(InstancePtr)->Stream.IsScrambled = (FALSE); \
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} \
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}
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/*****************************************************************************/
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@ -391,388 +391,388 @@ typedef struct {
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*
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* This macro enables the HDMI TX PIO peripheral.
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*
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* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
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* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
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*
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* @return None.
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* @return None.
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*
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* @note C-style signature:
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* void XV_HdmiTx_PioEnable(XV_HdmiTx *InstancePtr)
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* @note C-style signature:
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* void XV_HdmiTx_PioEnable(XV_HdmiTx *InstancePtr)
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*
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******************************************************************************/
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#define XV_HdmiTx_PioEnable(InstancePtr) \
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_CTRL_SET_OFFSET), (XV_HDMITX_PIO_CTRL_RUN_MASK))
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XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
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(XV_HDMITX_PIO_CTRL_SET_OFFSET), (XV_HDMITX_PIO_CTRL_RUN_MASK))
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/*****************************************************************************/
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/**
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*
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* This macro disables the HDMI TX PIO peripheral.
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*
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* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_PioDisable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_PioDisable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_PioDisable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_CTRL_CLR_OFFSET), (XV_HDMITX_PIO_CTRL_RUN_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_CTRL_CLR_OFFSET), (XV_HDMITX_PIO_CTRL_RUN_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro enables interrupt in the HDMI TX PIO peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_PioIntrEnable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_PioIntrEnable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_PioIntrEnable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_CTRL_SET_OFFSET), (XV_HDMITX_PIO_CTRL_IE_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_CTRL_SET_OFFSET), (XV_HDMITX_PIO_CTRL_IE_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro disables interrupt in the HDMI TX PIO peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_PioIntrDisable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_PioIntrDisable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_PioIntrDisable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_CTRL_CLR_OFFSET), (XV_HDMITX_PIO_CTRL_IE_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_CTRL_CLR_OFFSET), (XV_HDMITX_PIO_CTRL_IE_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro clears HDMI TX PIO interrupt.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_PioIntrClear(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_PioIntrClear(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_PioIntrClear(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_STA_OFFSET), (XV_HDMITX_PIO_STA_IRQ_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_STA_OFFSET), (XV_HDMITX_PIO_STA_IRQ_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro enables the HDMI TX Display Data Channel (DDC) peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcEnable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcEnable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_DdcEnable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_CTRL_SET_OFFSET), (XV_HDMITX_DDC_CTRL_RUN_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_CTRL_SET_OFFSET), (XV_HDMITX_DDC_CTRL_RUN_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro disables the HDMI TX Display Data Channel (DDC) peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcDisable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcDisable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_DdcDisable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_CTRL_CLR_OFFSET), (XV_HDMITX_DDC_CTRL_RUN_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_CTRL_CLR_OFFSET), (XV_HDMITX_DDC_CTRL_RUN_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro enables interrupt in the HDMI TX DDC peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcIntrEnable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcIntrEnable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_DdcIntrEnable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_CTRL_SET_OFFSET), (XV_HDMITX_DDC_CTRL_IE_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_CTRL_SET_OFFSET), (XV_HDMITX_DDC_CTRL_IE_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro disables interrupt in the HDMI TX DDC peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcIntrDisable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcIntrDisable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_DdcIntrDisable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_CTRL_CLR_OFFSET), (XV_HDMITX_DDC_CTRL_IE_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_CTRL_CLR_OFFSET), (XV_HDMITX_DDC_CTRL_IE_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro clears HDMI TX DDC interrupt.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcIntrClear(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_DdcIntrClear(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_DdcIntrClear(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_STA_OFFSET), (XV_HDMITX_DDC_STA_IRQ_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_DDC_STA_OFFSET), (XV_HDMITX_DDC_STA_IRQ_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro enables the HDMI TX Auxiliary (AUX) peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AuxEnable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AuxEnable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_AuxEnable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUX_CTRL_SET_OFFSET), (XV_HDMITX_AUX_CTRL_RUN_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUX_CTRL_SET_OFFSET), (XV_HDMITX_AUX_CTRL_RUN_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro disables the HDMI TX Auxiliary (AUX) peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AuxDisable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AuxDisable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_AuxDisable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUX_CTRL_CLR_OFFSET), (XV_HDMITX_AUX_CTRL_RUN_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUX_CTRL_CLR_OFFSET), (XV_HDMITX_AUX_CTRL_RUN_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro enables interrupt in the HDMI TX AUX peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AuxIntrEnable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AuxIntrEnable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_AuxIntrEnable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUX_CTRL_SET_OFFSET), (XV_HDMITX_AUX_CTRL_IE_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUX_CTRL_SET_OFFSET), (XV_HDMITX_AUX_CTRL_IE_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro disables interrupt in the HDMI TX AUX peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AuxIntrDisable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AuxIntrDisable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_AuxIntrDisable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUX_CTRL_CLR_OFFSET), (XV_HDMITX_AUX_CTRL_IE_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUX_CTRL_CLR_OFFSET), (XV_HDMITX_AUX_CTRL_IE_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro enables audio in HDMI TX core.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AudioEnable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AudioEnable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_AudioEnable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro disables audio in HDMI TX core.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AudioDisable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AudioDisable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_AudioDisable(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro unmutes audio in HDMI TX core.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AudioEnable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AudioEnable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_AudioUnmute(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro mutes audio in HDMI TX core.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AudioDisable(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_AudioDisable(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_AudioMute(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro sets the mode to operate in.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_SetMode(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_SetMode(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_SetMode(InstancePtr) \
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_MODE_MASK))
|
||||
XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_MODE_MASK))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro provides the current mode.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return Current mode.
|
||||
* 0 = DVI
|
||||
* 1 = HDMI
|
||||
* @return Current mode.
|
||||
* 0 = DVI
|
||||
* 1 = HDMI
|
||||
*
|
||||
* @note C-style signature:
|
||||
* u8 XV_HdmiTx_GetMode(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* u8 XV_HdmiTx_GetMode(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_GetMode(InstancePtr) \
|
||||
XV_HdmiTx_ReadReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_OUT_OFFSET)) & (XV_HDMITX_PIO_OUT_MODE_MASK)
|
||||
XV_HdmiTx_ReadReg((InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_OUT_OFFSET)) & (XV_HDMITX_PIO_OUT_MODE_MASK)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro provides the current sample rate.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return Sample rate
|
||||
* @return Sample rate
|
||||
*
|
||||
* @note C-style signature:
|
||||
* u8 XV_HdmiTx_GetMode(XV_HdmiTx *InstancePtr)
|
||||
* @note C-style signature:
|
||||
* u8 XV_HdmiTx_GetMode(XV_HdmiTx *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_GetSampleRate(InstancePtr) \
|
||||
(InstancePtr)->Stream.SampleRate
|
||||
(InstancePtr)->Stream.SampleRate
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro provides the active audio channels.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return Audio channels
|
||||
* @return Audio channels
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_GetAudioChannels(InstancePtr) \
|
||||
(InstancePtr)->Stream.Audio.Channels
|
||||
(InstancePtr)->Stream.Audio.Channels
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro provides the current pixel packing phase.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return Pixel packing phase.
|
||||
* @return Pixel packing phase.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_GetPixelPackingPhase(InstancePtr) \
|
||||
( ( (XV_HdmiTx_ReadReg( (InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_IN_OFFSET) ) ) >> (XV_HDMITX_PIO_IN_PPP_SHIFT)) \
|
||||
& (XV_HDMITX_PIO_IN_PPP_MASK))
|
||||
( ( (XV_HdmiTx_ReadReg( (InstancePtr)->Config.BaseAddress, \
|
||||
(XV_HDMITX_PIO_IN_OFFSET) ) ) >> (XV_HDMITX_PIO_IN_PPP_SHIFT)) \
|
||||
& (XV_HDMITX_PIO_IN_PPP_MASK))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
@ -781,16 +781,16 @@ XV_HdmiTx_Config *XV_HdmiTx_LookupConfig(u16 DeviceId);
|
|||
|
||||
/* Initialization and control functions in xv_hdmitx.c */
|
||||
int XV_HdmiTx_CfgInitialize(XV_HdmiTx *InstancePtr,
|
||||
XV_HdmiTx_Config *CfgPtr,
|
||||
u32 EffectiveAddr);
|
||||
XV_HdmiTx_Config *CfgPtr,
|
||||
u32 EffectiveAddr);
|
||||
void XV_HdmiTx_Clear(XV_HdmiTx *InstancePtr);
|
||||
u8 XV_HdmiTx_GetVic(XVidC_VideoMode VideoMode);
|
||||
XVidC_VideoMode XV_HdmiTx_GetVideoModeFromVic(u8 Vic);
|
||||
u32 XV_HdmiTx_SetStream(XV_HdmiTx *InstancePtr,
|
||||
XVidC_VideoMode VideoMode,
|
||||
XVidC_ColorFormat ColorFormat,
|
||||
XVidC_ColorDepth Bpc,
|
||||
XVidC_PixelsPerClock Ppc);
|
||||
XVidC_VideoMode VideoMode,
|
||||
XVidC_ColorFormat ColorFormat,
|
||||
XVidC_ColorDepth Bpc,
|
||||
XVidC_PixelsPerClock Ppc);
|
||||
u32 XV_HdmiTx_SetStreamReducedBlanking(XV_HdmiTx *InstancePtr);
|
||||
void XV_HdmiTx_SetPixelRate(XV_HdmiTx *InstancePtr);
|
||||
void XV_HdmiTx_SetSampleRate(XV_HdmiTx *InstancePtr, u8 SampleRate);
|
||||
|
@ -800,9 +800,9 @@ int XV_HdmiTx_IsStreamScrambled(XV_HdmiTx *InstancePtr);
|
|||
int XV_HdmiTx_IsStreamConnected(XV_HdmiTx *InstancePtr);
|
||||
void XV_HdmiTx_DdcInit(XV_HdmiTx *InstancePtr, u32 Frequency);
|
||||
int XV_HdmiTx_DdcWrite(XV_HdmiTx *InstancePtr, u8 Slave, u16 Length,
|
||||
u8 *Buffer, u8 Stop);
|
||||
u8 *Buffer, u8 Stop);
|
||||
int XV_HdmiTx_DdcRead(XV_HdmiTx *InstancePtr, u8 Slave, u16 Length,
|
||||
u8 *Buffer, u8 Stop);
|
||||
u8 *Buffer, u8 Stop);
|
||||
int XV_HdmiTx_AuxSend(XV_HdmiTx *InstancePtr);
|
||||
int XV_HdmiTx_Scrambler(XV_HdmiTx *InstancePtr);
|
||||
int XV_HdmiTx_ClockRatio(XV_HdmiTx *InstancePtr);
|
||||
|
@ -817,7 +817,7 @@ int XV_HdmiTx_SelfTest(XV_HdmiTx *InstancePtr);
|
|||
/* Interrupt related functions in xv_hdmitx_intr.c */
|
||||
void XV_HdmiTx_IntrHandler(void *InstancePtr);
|
||||
int XV_HdmiTx_SetCallback(XV_HdmiTx *InstancePtr, u32 HandlerType,
|
||||
void *CallbackFunc, void *CallbackRef);
|
||||
void *CallbackFunc, void *CallbackRef);
|
||||
|
||||
/************************** Variable Declarations ****************************/
|
||||
|
||||
|
|
9
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_g.c
Executable file → Normal file
9
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_g.c
Executable file → Normal file
|
@ -46,8 +46,9 @@
|
|||
|
||||
XV_HdmiTx_Config XV_HdmiTx_ConfigTable[] =
|
||||
{
|
||||
{
|
||||
XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_DEVICE_ID,
|
||||
XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_BASEADDR
|
||||
}
|
||||
{
|
||||
XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_DEVICE_ID,
|
||||
XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_BASEADDR,
|
||||
XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_S_AXI_FREQUENCY
|
||||
}
|
||||
};
|
||||
|
|
358
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_hw.h
Executable file → Normal file
358
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_hw.h
Executable file → Normal file
|
@ -51,8 +51,8 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
#ifndef XV_HDMITX_HW_H_
|
||||
#define XV_HDMITX_HW_H_ /**< Prevent circular inclusions
|
||||
* by using protection macros */
|
||||
#define XV_HDMITX_HW_H_ /**< Prevent circular inclusions
|
||||
* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
@ -66,202 +66,202 @@ extern "C" {
|
|||
|
||||
/**< VER (Version Interface) peripheral register offsets */
|
||||
/**< The VER is the first peripheral on the local bus */
|
||||
#define XV_HDMITX_VER_BASE (0*64)
|
||||
#define XV_HDMITX_VER_ID_OFFSET ((XV_HDMITX_VER_BASE)+(0*4))/**<
|
||||
* VER Identification * Register offset */
|
||||
#define XV_HDMITX_VER_VERSION_OFFSET ((XV_HDMITX_VER_BASE)+(1*4))/**<
|
||||
* VER Version Register * offset */
|
||||
#define XV_HDMITX_VER_BASE (0*64)
|
||||
#define XV_HDMITX_VER_ID_OFFSET ((XV_HDMITX_VER_BASE)+(0*4))/**<
|
||||
* VER Identification * Register offset */
|
||||
#define XV_HDMITX_VER_VERSION_OFFSET ((XV_HDMITX_VER_BASE)+(1*4))/**<
|
||||
* VER Version Register * offset */
|
||||
|
||||
/**< PIO (Parallel Interface) peripheral register offsets */
|
||||
/**< The PIO is the first peripheral on the local bus */
|
||||
#define XV_HDMITX_PIO_BASE (1*64)
|
||||
#define XV_HDMITX_PIO_ID_OFFSET ((XV_HDMITX_PIO_BASE)+(0*4))/**< PIO
|
||||
* Identification * Register offset */
|
||||
#define XV_HDMITX_PIO_CTRL_OFFSET ((XV_HDMITX_PIO_BASE)+(1*4))/**< PIO
|
||||
* Control Register * offset */
|
||||
#define XV_HDMITX_PIO_CTRL_SET_OFFSET ((XV_HDMITX_PIO_BASE)+(2*4))/**< PIO
|
||||
* Control Register Set * offset */
|
||||
#define XV_HDMITX_PIO_CTRL_CLR_OFFSET ((XV_HDMITX_PIO_BASE)+(3*4))/**< PIO
|
||||
* Control Register Clear * offset */
|
||||
#define XV_HDMITX_PIO_STA_OFFSET ((XV_HDMITX_PIO_BASE)+(4*4))/**< PIO
|
||||
* Status Register * offset */
|
||||
#define XV_HDMITX_PIO_OUT_OFFSET ((XV_HDMITX_PIO_BASE)+(5*4))/**< PIO
|
||||
* Out Register offset */
|
||||
#define XV_HDMITX_PIO_OUT_SET_OFFSET ((XV_HDMITX_PIO_BASE)+(6*4))/**< PIO
|
||||
* Out Register Set * offset */
|
||||
#define XV_HDMITX_PIO_OUT_CLR_OFFSET ((XV_HDMITX_PIO_BASE)+(7*4))/**< PIO
|
||||
* Out Register Clear * offset */
|
||||
#define XV_HDMITX_PIO_OUT_MSK_OFFSET ((XV_HDMITX_PIO_BASE)+(8*4))/**< PIO
|
||||
* Out Mask Register * offset */
|
||||
#define XV_HDMITX_PIO_IN_OFFSET ((XV_HDMITX_PIO_BASE)+(9*4))/**< PIO
|
||||
* In Register offset */
|
||||
#define XV_HDMITX_PIO_IN_EVT_OFFSET ((XV_HDMITX_PIO_BASE)+(10*4))/**< PIO
|
||||
* In Event Register * offset */
|
||||
#define XV_HDMITX_PIO_IN_EVT_RE_OFFSET ((XV_HDMITX_PIO_BASE)+(11*4))/**< PIO
|
||||
* In Event Rising Edge * Register offset */
|
||||
#define XV_HDMITX_PIO_IN_EVT_FE_OFFSET ((XV_HDMITX_PIO_BASE)+(12*4))/**< PIO
|
||||
* In Event Falling Edge * Register offset */
|
||||
#define XV_HDMITX_PIO_BASE (1*64)
|
||||
#define XV_HDMITX_PIO_ID_OFFSET ((XV_HDMITX_PIO_BASE)+(0*4))/**< PIO
|
||||
* Identification * Register offset */
|
||||
#define XV_HDMITX_PIO_CTRL_OFFSET ((XV_HDMITX_PIO_BASE)+(1*4))/**< PIO
|
||||
* Control Register * offset */
|
||||
#define XV_HDMITX_PIO_CTRL_SET_OFFSET ((XV_HDMITX_PIO_BASE)+(2*4))/**< PIO
|
||||
* Control Register Set * offset */
|
||||
#define XV_HDMITX_PIO_CTRL_CLR_OFFSET ((XV_HDMITX_PIO_BASE)+(3*4))/**< PIO
|
||||
* Control Register Clear * offset */
|
||||
#define XV_HDMITX_PIO_STA_OFFSET ((XV_HDMITX_PIO_BASE)+(4*4))/**< PIO
|
||||
* Status Register * offset */
|
||||
#define XV_HDMITX_PIO_OUT_OFFSET ((XV_HDMITX_PIO_BASE)+(5*4))/**< PIO
|
||||
* Out Register offset */
|
||||
#define XV_HDMITX_PIO_OUT_SET_OFFSET ((XV_HDMITX_PIO_BASE)+(6*4))/**< PIO
|
||||
* Out Register Set * offset */
|
||||
#define XV_HDMITX_PIO_OUT_CLR_OFFSET ((XV_HDMITX_PIO_BASE)+(7*4))/**< PIO
|
||||
* Out Register Clear * offset */
|
||||
#define XV_HDMITX_PIO_OUT_MSK_OFFSET ((XV_HDMITX_PIO_BASE)+(8*4))/**< PIO
|
||||
* Out Mask Register * offset */
|
||||
#define XV_HDMITX_PIO_IN_OFFSET ((XV_HDMITX_PIO_BASE)+(9*4))/**< PIO
|
||||
* In Register offset */
|
||||
#define XV_HDMITX_PIO_IN_EVT_OFFSET ((XV_HDMITX_PIO_BASE)+(10*4))/**< PIO
|
||||
* In Event Register * offset */
|
||||
#define XV_HDMITX_PIO_IN_EVT_RE_OFFSET ((XV_HDMITX_PIO_BASE)+(11*4))/**< PIO
|
||||
* In Event Rising Edge * Register offset */
|
||||
#define XV_HDMITX_PIO_IN_EVT_FE_OFFSET ((XV_HDMITX_PIO_BASE)+(12*4))/**< PIO
|
||||
* In Event Falling Edge * Register offset */
|
||||
|
||||
// PIO peripheral Control register masks
|
||||
#define XV_HDMITX_PIO_CTRL_RUN_MASK (1<<0) /**< PIO Control Run mask */
|
||||
#define XV_HDMITX_PIO_CTRL_IE_MASK (1<<1) /**< PIO Control Interrupt
|
||||
* Enable mask */
|
||||
#define XV_HDMITX_PIO_CTRL_RUN_MASK (1<<0) /**< PIO Control Run mask */
|
||||
#define XV_HDMITX_PIO_CTRL_IE_MASK (1<<1) /**< PIO Control Interrupt
|
||||
* Enable mask */
|
||||
|
||||
// PIO peripheral Status register masks
|
||||
#define XV_HDMITX_PIO_STA_IRQ_MASK (1<<0) /**< PIO Status Interrupt mask */
|
||||
#define XV_HDMITX_PIO_STA_EVT_MASK (1<<1) /**< PIO Status Event mask */
|
||||
#define XV_HDMITX_PIO_STA_IRQ_MASK (1<<0) /**< PIO Status Interrupt mask */
|
||||
#define XV_HDMITX_PIO_STA_EVT_MASK (1<<1) /**< PIO Status Event mask */
|
||||
|
||||
// PIO peripheral PIO Out register masks and shifts
|
||||
#define XV_HDMITX_PIO_OUT_RST_MASK (1<<0) /**< PIO Out Reset mask */
|
||||
#define XV_HDMITX_PIO_OUT_MODE_MASK (1<<3) /**< PIO Out Mode mask */
|
||||
#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_MASK 0x30 /**< PIO Out Color Depth
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_PIXEL_RATE_MASK 0xC0 /**< PIO Out Pixel Rate
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_MASK 0x300 /**< PIO Out Sample Rate
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_COLOR_SPACE_MASK 0xC00 /**< PIO Out Color Space
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_SCRM_MASK (1<<12) /**< PIO Out Scrambler
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_SHIFT 4 /**< PIO Out Color Depth
|
||||
* shift */
|
||||
#define XV_HDMITX_PIO_OUT_PIXEL_RATE_SHIFT 6 /**< PIO Out Pixel Rate
|
||||
* shift */
|
||||
#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_SHIFT 8 /**< PIO Out Sample Rate
|
||||
* shift */
|
||||
#define XV_HDMITX_PIO_OUT_COLOR_SPACE_SHIFT 10 /**< PIO Out Color Space
|
||||
* shift */
|
||||
#define XV_HDMITX_PIO_OUT_RST_MASK (1<<0) /**< PIO Out Reset mask */
|
||||
#define XV_HDMITX_PIO_OUT_MODE_MASK (1<<3) /**< PIO Out Mode mask */
|
||||
#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_MASK 0x30 /**< PIO Out Color Depth
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_PIXEL_RATE_MASK 0xC0 /**< PIO Out Pixel Rate
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_MASK 0x300 /**< PIO Out Sample Rate
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_COLOR_SPACE_MASK 0xC00 /**< PIO Out Color Space
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_SCRM_MASK (1<<12) /**< PIO Out Scrambler
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_SHIFT 4 /**< PIO Out Color Depth
|
||||
* shift */
|
||||
#define XV_HDMITX_PIO_OUT_PIXEL_RATE_SHIFT 6 /**< PIO Out Pixel Rate
|
||||
* shift */
|
||||
#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_SHIFT 8 /**< PIO Out Sample Rate
|
||||
* shift */
|
||||
#define XV_HDMITX_PIO_OUT_COLOR_SPACE_SHIFT 10 /**< PIO Out Color Space
|
||||
* shift */
|
||||
|
||||
// PIO peripheral PIO In register masks
|
||||
#define XV_HDMITX_PIO_IN_LNK_RDY_MASK (1<<0) /**< PIO In link ready
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_IN_VID_RDY_MASK (1<<1) /**< PIO In video ready
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_IN_HPD_MASK (1<<2) /**< PIO In HPD mask */
|
||||
#define XV_HDMITX_PIO_IN_VS_MASK (1<<3) /**< PIO In Vsync mask */
|
||||
#define XV_HDMITX_PIO_IN_PPP_MASK 0x07 /**< PIO In Pixel packing
|
||||
* phase mask */
|
||||
#define XV_HDMITX_PIO_IN_PPP_SHIFT 5 /**< PIO In Pixel packing
|
||||
* phase shift */
|
||||
#define XV_HDMITX_PIO_IN_LNK_RDY_MASK (1<<0) /**< PIO In link ready
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_IN_VID_RDY_MASK (1<<1) /**< PIO In video ready
|
||||
* mask */
|
||||
#define XV_HDMITX_PIO_IN_HPD_MASK (1<<2) /**< PIO In HPD mask */
|
||||
#define XV_HDMITX_PIO_IN_VS_MASK (1<<3) /**< PIO In Vsync mask */
|
||||
#define XV_HDMITX_PIO_IN_PPP_MASK 0x07 /**< PIO In Pixel packing
|
||||
* phase mask */
|
||||
#define XV_HDMITX_PIO_IN_PPP_SHIFT 5 /**< PIO In Pixel packing
|
||||
* phase shift */
|
||||
|
||||
/**< DDC (Display Data Channel) peripheral register offsets */
|
||||
/**< The DDC is the second peripheral on the local bus */
|
||||
#define XV_HDMITX_DDC_BASE (2*64)
|
||||
#define XV_HDMITX_DDC_ID_OFFSET ((XV_HDMITX_DDC_BASE)+(0*4))/**< DDC
|
||||
* Identification * Register offset */
|
||||
#define XV_HDMITX_DDC_CTRL_OFFSET ((XV_HDMITX_DDC_BASE)+(1*4))/**< DDC
|
||||
* Control Register * offset */
|
||||
#define XV_HDMITX_DDC_CTRL_SET_OFFSET ((XV_HDMITX_DDC_BASE)+(2*4))/**< DDC
|
||||
* Control Register Set * offset */
|
||||
#define XV_HDMITX_DDC_CTRL_CLR_OFFSET ((XV_HDMITX_DDC_BASE)+(3*4))/**< DDC
|
||||
* Control Register Clear * offset */
|
||||
#define XV_HDMITX_DDC_STA_OFFSET ((XV_HDMITX_DDC_BASE)+(4*4))/**< DDC
|
||||
* Status Register * offset */
|
||||
#define XV_HDMITX_DDC_CMD_OFFSET ((XV_HDMITX_DDC_BASE)+(5*4))/**< DDC
|
||||
* Command Register * offset */
|
||||
#define XV_HDMITX_DDC_DAT_OFFSET ((XV_HDMITX_DDC_BASE)+(6*4))/**< DDC
|
||||
* Data Register * offset */
|
||||
#define XV_HDMITX_DDC_BASE (2*64)
|
||||
#define XV_HDMITX_DDC_ID_OFFSET ((XV_HDMITX_DDC_BASE)+(0*4))/**< DDC
|
||||
* Identification * Register offset */
|
||||
#define XV_HDMITX_DDC_CTRL_OFFSET ((XV_HDMITX_DDC_BASE)+(1*4))/**< DDC
|
||||
* Control Register * offset */
|
||||
#define XV_HDMITX_DDC_CTRL_SET_OFFSET ((XV_HDMITX_DDC_BASE)+(2*4))/**< DDC
|
||||
* Control Register Set * offset */
|
||||
#define XV_HDMITX_DDC_CTRL_CLR_OFFSET ((XV_HDMITX_DDC_BASE)+(3*4))/**< DDC
|
||||
* Control Register Clear * offset */
|
||||
#define XV_HDMITX_DDC_STA_OFFSET ((XV_HDMITX_DDC_BASE)+(4*4))/**< DDC
|
||||
* Status Register * offset */
|
||||
#define XV_HDMITX_DDC_CMD_OFFSET ((XV_HDMITX_DDC_BASE)+(5*4))/**< DDC
|
||||
* Command Register * offset */
|
||||
#define XV_HDMITX_DDC_DAT_OFFSET ((XV_HDMITX_DDC_BASE)+(6*4))/**< DDC
|
||||
* Data Register * offset */
|
||||
|
||||
// DDC peripheral Control register masks and shift
|
||||
#define XV_HDMITX_DDC_CTRL_RUN_MASK (1<<0) /**< DDC Control Run mask */
|
||||
#define XV_HDMITX_DDC_CTRL_IE_MASK (1<<1) /**< DDC Control Interrupt
|
||||
* Enable mask */
|
||||
#define XV_HDMITX_DDC_CTRL_CLK_DIV_MASK 0xFFFF /**< DDC Control Clock
|
||||
* Divider mask */
|
||||
#define XV_HDMITX_DDC_CTRL_CLK_DIV_SHIFT 16 /**< DDC Control Clock
|
||||
*Divider shift */ /*@}*/
|
||||
#define XV_HDMITX_DDC_CTRL_RUN_MASK (1<<0) /**< DDC Control Run mask */
|
||||
#define XV_HDMITX_DDC_CTRL_IE_MASK (1<<1) /**< DDC Control Interrupt
|
||||
* Enable mask */
|
||||
#define XV_HDMITX_DDC_CTRL_CLK_DIV_MASK 0xFFFF /**< DDC Control Clock
|
||||
* Divider mask */
|
||||
#define XV_HDMITX_DDC_CTRL_CLK_DIV_SHIFT 16 /**< DDC Control Clock
|
||||
*Divider shift */ /*@}*/
|
||||
|
||||
// DDC peripheral Status register masks
|
||||
#define XV_HDMITX_DDC_STA_IRQ_MASK (1<<0) /**< DDC Status IRQ mask */
|
||||
#define XV_HDMITX_DDC_STA_EVT_MASK (1<<1) /**< DDC Status Event mask */
|
||||
#define XV_HDMITX_DDC_STA_BUSY_MASK (1<<2) /**< DDC Status Busy mask */
|
||||
#define XV_HDMITX_DDC_STA_DONE_MASK (1<<3) /**< DDC Status Busy mask */
|
||||
#define XV_HDMITX_DDC_STA_TIMEOUT_MASK (1<<4) /**< DDC Status Timeout mask */
|
||||
#define XV_HDMITX_DDC_STA_ACK_MASK (1<<5) /**< DDC Status ACK mask */
|
||||
#define XV_HDMITX_DDC_STA_SCL_MASK (1<<6) /**< DDC State of SCL Input
|
||||
* mask */
|
||||
#define XV_HDMITX_DDC_STA_SDA_MASK (1<<7) /**< DDC State of SDA Input
|
||||
* mask */
|
||||
#define XV_HDMITX_DDC_STA_CMD_FULL (1<<8) /**< Command fifo full */
|
||||
#define XV_HDMITX_DDC_STA_DAT_EMPTY (1<<9) /**< Data fifo empty */
|
||||
#define XV_HDMITX_DDC_STA_CMD_WRDS_MASK 0xFF /**< Command fifo words mask*/
|
||||
#define XV_HDMITX_DDC_STA_CMD_WRDS_SHIFT 16 /**< Command fifo words shift */
|
||||
#define XV_HDMITX_DDC_STA_DAT_WRDS_MASK 0xFF /**< Data fifo words mask */
|
||||
#define XV_HDMITX_DDC_STA_DAT_WRDS_SHIFT 24 /**< Data fifo words shift */
|
||||
#define XV_HDMITX_DDC_STA_IRQ_MASK (1<<0) /**< DDC Status IRQ mask */
|
||||
#define XV_HDMITX_DDC_STA_EVT_MASK (1<<1) /**< DDC Status Event mask */
|
||||
#define XV_HDMITX_DDC_STA_BUSY_MASK (1<<2) /**< DDC Status Busy mask */
|
||||
#define XV_HDMITX_DDC_STA_DONE_MASK (1<<3) /**< DDC Status Busy mask */
|
||||
#define XV_HDMITX_DDC_STA_TIMEOUT_MASK (1<<4) /**< DDC Status Timeout mask */
|
||||
#define XV_HDMITX_DDC_STA_ACK_MASK (1<<5) /**< DDC Status ACK mask */
|
||||
#define XV_HDMITX_DDC_STA_SCL_MASK (1<<6) /**< DDC State of SCL Input
|
||||
* mask */
|
||||
#define XV_HDMITX_DDC_STA_SDA_MASK (1<<7) /**< DDC State of SDA Input
|
||||
* mask */
|
||||
#define XV_HDMITX_DDC_STA_CMD_FULL (1<<8) /**< Command fifo full */
|
||||
#define XV_HDMITX_DDC_STA_DAT_EMPTY (1<<9) /**< Data fifo empty */
|
||||
#define XV_HDMITX_DDC_STA_CMD_WRDS_MASK 0xFF /**< Command fifo words mask*/
|
||||
#define XV_HDMITX_DDC_STA_CMD_WRDS_SHIFT 16 /**< Command fifo words shift */
|
||||
#define XV_HDMITX_DDC_STA_DAT_WRDS_MASK 0xFF /**< Data fifo words mask */
|
||||
#define XV_HDMITX_DDC_STA_DAT_WRDS_SHIFT 24 /**< Data fifo words shift */
|
||||
|
||||
// DDC peripheral token
|
||||
#define XV_HDMITX_DDC_CMD_STR_TOKEN (0x100) /**< Start token */
|
||||
#define XV_HDMITX_DDC_CMD_STP_TOKEN (0x101) /**< Stop token */
|
||||
#define XV_HDMITX_DDC_CMD_RD_TOKEN (0x102) /**< Read token */
|
||||
#define XV_HDMITX_DDC_CMD_WR_TOKEN (0x103) /**< Write token */
|
||||
#define XV_HDMITX_DDC_CMD_STR_TOKEN (0x100) /**< Start token */
|
||||
#define XV_HDMITX_DDC_CMD_STP_TOKEN (0x101) /**< Stop token */
|
||||
#define XV_HDMITX_DDC_CMD_RD_TOKEN (0x102) /**< Read token */
|
||||
#define XV_HDMITX_DDC_CMD_WR_TOKEN (0x103) /**< Write token */
|
||||
|
||||
// Auxiliary (AUX) peripheral register offsets
|
||||
// The AUX is the third peripheral on the local bus
|
||||
#define XV_HDMITX_AUX_BASE (3*64)
|
||||
#define XV_HDMITX_AUX_ID_OFFSET ((XV_HDMITX_AUX_BASE)+(0*4)) /**< AUX
|
||||
* Identification * Register offset */
|
||||
#define XV_HDMITX_AUX_CTRL_OFFSET ((XV_HDMITX_AUX_BASE)+(1*4)) /**< AUX
|
||||
* Control Register * offset */
|
||||
#define XV_HDMITX_AUX_CTRL_SET_OFFSET ((XV_HDMITX_AUX_BASE)+(2*4)) /**< AUX
|
||||
* Control Register Set * offset */
|
||||
#define XV_HDMITX_AUX_CTRL_CLR_OFFSET ((XV_HDMITX_AUX_BASE)+(3*4)) /**< AUX
|
||||
* Control Register Clear * offset */
|
||||
#define XV_HDMITX_AUX_STA_OFFSET ((XV_HDMITX_AUX_BASE)+(4*4)) /**< AUX
|
||||
* Status Register * offset */
|
||||
#define XV_HDMITX_AUX_DAT_OFFSET ((XV_HDMITX_AUX_BASE)+(5*4)) /**< AUX
|
||||
* Data Register * offset */
|
||||
#define XV_HDMITX_AUX_BASE (3*64)
|
||||
#define XV_HDMITX_AUX_ID_OFFSET ((XV_HDMITX_AUX_BASE)+(0*4)) /**< AUX
|
||||
* Identification * Register offset */
|
||||
#define XV_HDMITX_AUX_CTRL_OFFSET ((XV_HDMITX_AUX_BASE)+(1*4)) /**< AUX
|
||||
* Control Register * offset */
|
||||
#define XV_HDMITX_AUX_CTRL_SET_OFFSET ((XV_HDMITX_AUX_BASE)+(2*4)) /**< AUX
|
||||
* Control Register Set * offset */
|
||||
#define XV_HDMITX_AUX_CTRL_CLR_OFFSET ((XV_HDMITX_AUX_BASE)+(3*4)) /**< AUX
|
||||
* Control Register Clear * offset */
|
||||
#define XV_HDMITX_AUX_STA_OFFSET ((XV_HDMITX_AUX_BASE)+(4*4)) /**< AUX
|
||||
* Status Register * offset */
|
||||
#define XV_HDMITX_AUX_DAT_OFFSET ((XV_HDMITX_AUX_BASE)+(5*4)) /**< AUX
|
||||
* Data Register * offset */
|
||||
|
||||
// Auxiliary peripheral Control register masks
|
||||
#define XV_HDMITX_AUX_CTRL_RUN_MASK (1<<0) /**< AUX Control Run mask */
|
||||
#define XV_HDMITX_AUX_CTRL_IE_MASK (1<<1) /**< AUX Control Interrupt
|
||||
* Enable mask */
|
||||
#define XV_HDMITX_AUX_CTRL_RUN_MASK (1<<0) /**< AUX Control Run mask */
|
||||
#define XV_HDMITX_AUX_CTRL_IE_MASK (1<<1) /**< AUX Control Interrupt
|
||||
* Enable mask */
|
||||
|
||||
// Auxiliary peripheral Status register masks and shift
|
||||
#define XV_HDMITX_AUX_STA_IRQ_MASK (1<<0) /**< AUX Status Interrupt
|
||||
* mask */
|
||||
#define XV_HDMITX_AUX_STA_FIFO_EMT_MASK (1<<1) /**< AUX Status FIFO Empty
|
||||
* mask */
|
||||
#define XV_HDMITX_AUX_STA_FIFO_FUL_MASK (1<<2) /**< AUX Status FIFO Full
|
||||
* mask */
|
||||
#define XV_HDMITX_AUX_STA_FREE_PKTS_MASK 0x0F /**< AUX Status Free Packets
|
||||
* mask */
|
||||
#define XV_HDMITX_AUX_STA_FREE_PKTS_SHIFT 15 /**< AUX Status Free
|
||||
* Packets shift */
|
||||
#define XV_HDMITX_AUX_STA_IRQ_MASK (1<<0) /**< AUX Status Interrupt
|
||||
* mask */
|
||||
#define XV_HDMITX_AUX_STA_FIFO_EMT_MASK (1<<1) /**< AUX Status FIFO Empty
|
||||
* mask */
|
||||
#define XV_HDMITX_AUX_STA_FIFO_FUL_MASK (1<<2) /**< AUX Status FIFO Full
|
||||
* mask */
|
||||
#define XV_HDMITX_AUX_STA_FREE_PKTS_MASK 0x0F /**< AUX Status Free Packets
|
||||
* mask */
|
||||
#define XV_HDMITX_AUX_STA_FREE_PKTS_SHIFT 15 /**< AUX Status Free
|
||||
* Packets shift */
|
||||
|
||||
|
||||
// Audio (AUD) peripheral register offsets
|
||||
// The AUD is the forth peripheral on the local bus
|
||||
#define XV_HDMITX_AUD_BASE (4*64)
|
||||
#define XV_HDMITX_AUD_ID_OFFSET ((XV_HDMITX_AUD_BASE)+(0*4)) /**< AUD
|
||||
* Identification * Register offset */
|
||||
#define XV_HDMITX_AUD_CTRL_OFFSET ((XV_HDMITX_AUD_BASE)+(1*4)) /**< AUD
|
||||
* Control Register * offset */
|
||||
#define XV_HDMITX_AUD_CTRL_SET_OFFSET ((XV_HDMITX_AUD_BASE)+(2*4)) /**< AUD
|
||||
* Control Register Set * offset */
|
||||
#define XV_HDMITX_AUD_CTRL_CLR_OFFSET ((XV_HDMITX_AUD_BASE)+(3*4)) /**< AUD
|
||||
* Control Register Clear * offset */
|
||||
#define XV_HDMITX_AUD_STA_OFFSET ((XV_HDMITX_AUD_BASE)+(4*4)) /**< AUD
|
||||
* Status Register * offset */
|
||||
#define XV_HDMITX_AUD_ACR_CTS_OFFSET ((XV_HDMITX_AUD_BASE)+(5*4)) /**< AUD
|
||||
* Clock Regeneration CTS * Register offset */
|
||||
#define XV_HDMITX_AUD_ACR_N_OFFSET ((XV_HDMITX_AUD_BASE)+(6*4)) /**< AUD
|
||||
* Clock Regeneration N * Register offset */
|
||||
#define XV_HDMITX_AUD_BASE (4*64)
|
||||
#define XV_HDMITX_AUD_ID_OFFSET ((XV_HDMITX_AUD_BASE)+(0*4)) /**< AUD
|
||||
* Identification * Register offset */
|
||||
#define XV_HDMITX_AUD_CTRL_OFFSET ((XV_HDMITX_AUD_BASE)+(1*4)) /**< AUD
|
||||
* Control Register * offset */
|
||||
#define XV_HDMITX_AUD_CTRL_SET_OFFSET ((XV_HDMITX_AUD_BASE)+(2*4)) /**< AUD
|
||||
* Control Register Set * offset */
|
||||
#define XV_HDMITX_AUD_CTRL_CLR_OFFSET ((XV_HDMITX_AUD_BASE)+(3*4)) /**< AUD
|
||||
* Control Register Clear * offset */
|
||||
#define XV_HDMITX_AUD_STA_OFFSET ((XV_HDMITX_AUD_BASE)+(4*4)) /**< AUD
|
||||
* Status Register * offset */
|
||||
#define XV_HDMITX_AUD_ACR_CTS_OFFSET ((XV_HDMITX_AUD_BASE)+(5*4)) /**< AUD
|
||||
* Clock Regeneration CTS * Register offset */
|
||||
#define XV_HDMITX_AUD_ACR_N_OFFSET ((XV_HDMITX_AUD_BASE)+(6*4)) /**< AUD
|
||||
* Clock Regeneration N * Register offset */
|
||||
|
||||
// Audio peripheral Control register masks
|
||||
#define XV_HDMITX_AUD_CTRL_RUN_MASK (1<<0) /**< AUD Control Run mask */
|
||||
#define XV_HDMITX_AUD_CTRL_IE_MASK (1<<1) /**< AUD Control Interrupt
|
||||
* Enable mask */
|
||||
#define XV_HDMITX_AUD_CTRL_CH_MASK 0x03 /**< AUD Control channels mask */
|
||||
#define XV_HDMITX_AUD_CTRL_CH_SHIFT 2 /**< AUD Control channels mask */
|
||||
#define XV_HDMITX_AUD_CTRL_RUN_MASK (1<<0) /**< AUD Control Run mask */
|
||||
#define XV_HDMITX_AUD_CTRL_IE_MASK (1<<1) /**< AUD Control Interrupt
|
||||
* Enable mask */
|
||||
#define XV_HDMITX_AUD_CTRL_CH_MASK 0x03 /**< AUD Control channels mask */
|
||||
#define XV_HDMITX_AUD_CTRL_CH_SHIFT 2 /**< AUD Control channels mask */
|
||||
|
||||
// Audio peripheral Status register masks
|
||||
#define XV_HDMITX_AUD_STA_IRQ_MASK (1<<0) /**< AUD Status Interrupt mask */
|
||||
#define XV_HDMITX_AUD_STA_IRQ_MASK (1<<0) /**< AUD Status Interrupt mask */
|
||||
|
||||
// Peripheral ID and General shift values.
|
||||
#define XV_HDMITX_SHIFT_16 16 /**< 16 shift value */
|
||||
#define XV_HDMITX_MASK_16 0xFFFF /**< 16 bit mask value */
|
||||
#define XV_HDMITX_PIO_ID 0x2200 /**< TX's PIO ID */
|
||||
#define XV_HDMITX_SHIFT_16 16 /**< 16 shift value */
|
||||
#define XV_HDMITX_MASK_16 0xFFFF /**< 16 bit mask value */
|
||||
#define XV_HDMITX_PIO_ID 0x2200 /**< TX's PIO ID */
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
|
@ -269,8 +269,8 @@ extern "C" {
|
|||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
// Register access macro definition
|
||||
#define XV_HdmiTx_In32 Xil_In32 /**< Input Operations */
|
||||
#define XV_HdmiTx_Out32 Xil_Out32 /**< Output Operations */
|
||||
#define XV_HdmiTx_In32 Xil_In32 /**< Input Operations */
|
||||
#define XV_HdmiTx_Out32 Xil_Out32 /**< Output Operations */
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
|
@ -280,18 +280,18 @@ extern "C" {
|
|||
* significant data is read from the register. The most significant data
|
||||
* will be read as 0.
|
||||
*
|
||||
* @param BaseAddress is the base address of the HDMI TX core instance.
|
||||
* @param RegOffset is the register offset of the register (defined at
|
||||
* the top of this file).
|
||||
* @param BaseAddress is the base address of the HDMI TX core instance.
|
||||
* @param RegOffset is the register offset of the register (defined at
|
||||
* the top of this file).
|
||||
*
|
||||
* @return The 32-bit value of the register.
|
||||
* @return The 32-bit value of the register.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* u32 XV_HdmiTx_ReadReg(u32 BaseAddress, u32 RegOffset)
|
||||
* @note C-style signature:
|
||||
* u32 XV_HdmiTx_ReadReg(u32 BaseAddress, u32 RegOffset)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_ReadReg(BaseAddress, RegOffset) \
|
||||
XV_HdmiTx_In32((BaseAddress) + ((u32)RegOffset))
|
||||
XV_HdmiTx_In32((BaseAddress) + ((u32)RegOffset))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
|
@ -300,19 +300,19 @@ extern "C" {
|
|||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is written.
|
||||
*
|
||||
* @param BaseAddress is the base address of the HDMI TX core instance.
|
||||
* @param RegOffset is the register offset of the register (defined at
|
||||
* the top of this file) to be written.
|
||||
* @param Data is the 32-bit value to write into the register.
|
||||
* @param BaseAddress is the base address of the HDMI TX core instance.
|
||||
* @param RegOffset is the register offset of the register (defined at
|
||||
* the top of this file) to be written.
|
||||
* @param Data is the 32-bit value to write into the register.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
|
||||
* @note C-style signature:
|
||||
* void XV_HdmiTx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XV_HdmiTx_WriteReg(BaseAddress, RegOffset, Data) \
|
||||
XV_HdmiTx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
|
||||
XV_HdmiTx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
|
||||
/*@}*/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
@ -325,4 +325,4 @@ extern "C" {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
#endif /* end of protection macro */
|
||||
|
|
300
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_intr.c
Executable file → Normal file
300
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_intr.c
Executable file → Normal file
|
@ -86,44 +86,44 @@ static void HdmiTx_DdcIntrHandler(XV_HdmiTx *InstancePtr);
|
|||
* XV_HdmiTx_SetCallback() during initialization phase. An example delivered
|
||||
* with this driver demonstrates how this could be done.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx instance that just
|
||||
* interrupted.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx instance that just
|
||||
* interrupted.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XV_HdmiTx_IntrHandler(void *InstancePtr)
|
||||
{
|
||||
u32 Data;
|
||||
XV_HdmiTx *HdmiTxPtr = (XV_HdmiTx *)InstancePtr;
|
||||
u32 Data;
|
||||
XV_HdmiTx *HdmiTxPtr = (XV_HdmiTx *)InstancePtr;
|
||||
|
||||
/* Verify arguments */
|
||||
Xil_AssertVoid(HdmiTxPtr != NULL);
|
||||
Xil_AssertVoid(HdmiTxPtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
/* Verify arguments */
|
||||
Xil_AssertVoid(HdmiTxPtr != NULL);
|
||||
Xil_AssertVoid(HdmiTxPtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/* PIO */
|
||||
Data = XV_HdmiTx_ReadReg(HdmiTxPtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_STA_OFFSET)) &
|
||||
(XV_HDMITX_PIO_STA_IRQ_MASK);
|
||||
/* PIO */
|
||||
Data = XV_HdmiTx_ReadReg(HdmiTxPtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_STA_OFFSET)) &
|
||||
(XV_HDMITX_PIO_STA_IRQ_MASK);
|
||||
|
||||
/* Check for IRQ flag set */
|
||||
if (Data) {
|
||||
/* Jump to PIO handler */
|
||||
HdmiTx_PioIntrHandler(HdmiTxPtr);
|
||||
}
|
||||
/* Check for IRQ flag set */
|
||||
if (Data) {
|
||||
/* Jump to PIO handler */
|
||||
HdmiTx_PioIntrHandler(HdmiTxPtr);
|
||||
}
|
||||
|
||||
/* DDC */
|
||||
Data = XV_HdmiTx_ReadReg(HdmiTxPtr->Config.BaseAddress,
|
||||
(XV_HDMITX_DDC_STA_OFFSET)) &
|
||||
(XV_HDMITX_DDC_STA_IRQ_MASK);
|
||||
/* DDC */
|
||||
Data = XV_HdmiTx_ReadReg(HdmiTxPtr->Config.BaseAddress,
|
||||
(XV_HDMITX_DDC_STA_OFFSET)) &
|
||||
(XV_HDMITX_DDC_STA_IRQ_MASK);
|
||||
|
||||
/* Check for IRQ flag set */
|
||||
if (Data) {
|
||||
/* Jump to DDC handler */
|
||||
HdmiTx_DdcIntrHandler(HdmiTxPtr);
|
||||
}
|
||||
/* Check for IRQ flag set */
|
||||
if (Data) {
|
||||
/* Jump to DDC handler */
|
||||
HdmiTx_DdcIntrHandler(HdmiTxPtr);
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
@ -139,71 +139,71 @@ void XV_HdmiTx_IntrHandler(void *InstancePtr)
|
|||
* (XV_HDMITX_HANDLER_VS) VsCallback
|
||||
* </pre>
|
||||
*
|
||||
* @param InstancePtr is a pointer to the HDMI TX core instance.
|
||||
* @param HandlerType specifies the type of handler.
|
||||
* @param CallbackFunc is the address of the callback function.
|
||||
* @param CallbackRef is a user data item that will be passed to the
|
||||
* callback function when it is invoked.
|
||||
* @param InstancePtr is a pointer to the HDMI TX core instance.
|
||||
* @param HandlerType specifies the type of handler.
|
||||
* @param CallbackFunc is the address of the callback function.
|
||||
* @param CallbackRef is a user data item that will be passed to the
|
||||
* callback function when it is invoked.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if callback function installed successfully.
|
||||
* - XST_INVALID_PARAM when HandlerType is invalid.
|
||||
* - XST_SUCCESS if callback function installed successfully.
|
||||
* - XST_INVALID_PARAM when HandlerType is invalid.
|
||||
*
|
||||
* @note Invoking this function for a handler that already has been
|
||||
* installed replaces it with the new handler.
|
||||
* @note Invoking this function for a handler that already has been
|
||||
* installed replaces it with the new handler.
|
||||
*
|
||||
******************************************************************************/
|
||||
int XV_HdmiTx_SetCallback(XV_HdmiTx *InstancePtr,
|
||||
u32 HandlerType,
|
||||
void *CallbackFunc,
|
||||
void *CallbackRef)
|
||||
u32 HandlerType,
|
||||
void *CallbackFunc,
|
||||
void *CallbackRef)
|
||||
{
|
||||
u32 Status;
|
||||
u32 Status;
|
||||
|
||||
/* Verify arguments. */
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(HandlerType >= (XV_HDMITX_HANDLER_CONNECT));
|
||||
Xil_AssertNonvoid(CallbackFunc != NULL);
|
||||
Xil_AssertNonvoid(CallbackRef != NULL);
|
||||
/* Verify arguments. */
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(HandlerType >= (XV_HDMITX_HANDLER_CONNECT));
|
||||
Xil_AssertNonvoid(CallbackFunc != NULL);
|
||||
Xil_AssertNonvoid(CallbackRef != NULL);
|
||||
|
||||
/* Check for handler type */
|
||||
switch (HandlerType) {
|
||||
case (XV_HDMITX_HANDLER_CONNECT):
|
||||
InstancePtr->ConnectCallback = (XV_HdmiTx_Callback)CallbackFunc;
|
||||
InstancePtr->ConnectRef = CallbackRef;
|
||||
InstancePtr->IsConnectCallbackSet = (TRUE);
|
||||
Status = (XST_SUCCESS);
|
||||
break;
|
||||
/* Check for handler type */
|
||||
switch (HandlerType) {
|
||||
case (XV_HDMITX_HANDLER_CONNECT):
|
||||
InstancePtr->ConnectCallback = (XV_HdmiTx_Callback)CallbackFunc;
|
||||
InstancePtr->ConnectRef = CallbackRef;
|
||||
InstancePtr->IsConnectCallbackSet = (TRUE);
|
||||
Status = (XST_SUCCESS);
|
||||
break;
|
||||
|
||||
case (XV_HDMITX_HANDLER_VS):
|
||||
InstancePtr->VsCallback = (XV_HdmiTx_Callback)CallbackFunc;
|
||||
InstancePtr->VsRef = CallbackRef;
|
||||
InstancePtr->IsVsCallbackSet = (TRUE);
|
||||
Status = (XST_SUCCESS);
|
||||
break;
|
||||
case (XV_HDMITX_HANDLER_VS):
|
||||
InstancePtr->VsCallback = (XV_HdmiTx_Callback)CallbackFunc;
|
||||
InstancePtr->VsRef = CallbackRef;
|
||||
InstancePtr->IsVsCallbackSet = (TRUE);
|
||||
Status = (XST_SUCCESS);
|
||||
break;
|
||||
|
||||
// Stream down
|
||||
case (XV_HDMITX_HANDLER_STREAM_DOWN):
|
||||
InstancePtr->StreamDownCallback = (XV_HdmiTx_Callback)CallbackFunc;
|
||||
InstancePtr->StreamDownRef = CallbackRef;
|
||||
InstancePtr->IsStreamDownCallbackSet = (TRUE);
|
||||
Status = (XST_SUCCESS);
|
||||
break;
|
||||
// Stream down
|
||||
case (XV_HDMITX_HANDLER_STREAM_DOWN):
|
||||
InstancePtr->StreamDownCallback = (XV_HdmiTx_Callback)CallbackFunc;
|
||||
InstancePtr->StreamDownRef = CallbackRef;
|
||||
InstancePtr->IsStreamDownCallbackSet = (TRUE);
|
||||
Status = (XST_SUCCESS);
|
||||
break;
|
||||
|
||||
// Stream up
|
||||
case (XV_HDMITX_HANDLER_STREAM_UP):
|
||||
InstancePtr->StreamUpCallback = (XV_HdmiTx_Callback)CallbackFunc;
|
||||
InstancePtr->StreamUpRef = CallbackRef;
|
||||
InstancePtr->IsStreamUpCallbackSet = (TRUE);
|
||||
Status = (XST_SUCCESS);
|
||||
break;
|
||||
// Stream up
|
||||
case (XV_HDMITX_HANDLER_STREAM_UP):
|
||||
InstancePtr->StreamUpCallback = (XV_HdmiTx_Callback)CallbackFunc;
|
||||
InstancePtr->StreamUpRef = CallbackRef;
|
||||
InstancePtr->IsStreamUpCallbackSet = (TRUE);
|
||||
Status = (XST_SUCCESS);
|
||||
break;
|
||||
|
||||
default:
|
||||
Status = (XST_INVALID_PARAM);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
Status = (XST_INVALID_PARAM);
|
||||
break;
|
||||
}
|
||||
|
||||
return Status;
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
@ -215,95 +215,95 @@ int XV_HdmiTx_SetCallback(XV_HdmiTx *InstancePtr,
|
|||
* register. It determines the source of the interrupts and calls according
|
||||
* callbacks.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the HDMI TX core instance.
|
||||
* @param InstancePtr is a pointer to the HDMI TX core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void HdmiTx_PioIntrHandler(XV_HdmiTx *InstancePtr)
|
||||
{
|
||||
u32 Event;
|
||||
u32 Data;
|
||||
u32 Event;
|
||||
u32 Data;
|
||||
|
||||
/* Read PIO IN Event register.*/
|
||||
Event = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_IN_EVT_OFFSET));
|
||||
/* Read PIO IN Event register.*/
|
||||
Event = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_IN_EVT_OFFSET));
|
||||
|
||||
/* Clear event flags */
|
||||
XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_IN_EVT_OFFSET),
|
||||
(Event));
|
||||
/* Clear event flags */
|
||||
XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_IN_EVT_OFFSET),
|
||||
(Event));
|
||||
|
||||
/* Read data */
|
||||
Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_IN_OFFSET));
|
||||
/* Read data */
|
||||
Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_IN_OFFSET));
|
||||
|
||||
/* HPD event has occurred */
|
||||
if ((Event) & (XV_HDMITX_PIO_IN_HPD_MASK)) {
|
||||
/* HPD event has occurred */
|
||||
if ((Event) & (XV_HDMITX_PIO_IN_HPD_MASK)) {
|
||||
|
||||
// Check the HPD status
|
||||
if ((Data) & (XV_HDMITX_PIO_IN_HPD_MASK))
|
||||
InstancePtr->Stream.IsConnected = (TRUE); // Set connected flag
|
||||
else
|
||||
InstancePtr->Stream.IsConnected = (FALSE); // Clear connected flag
|
||||
// Check the HPD status
|
||||
if ((Data) & (XV_HDMITX_PIO_IN_HPD_MASK))
|
||||
InstancePtr->Stream.IsConnected = (TRUE); // Set connected flag
|
||||
else
|
||||
InstancePtr->Stream.IsConnected = (FALSE); // Clear connected flag
|
||||
|
||||
// Check if user callback has been registered
|
||||
if (InstancePtr->IsConnectCallbackSet) {
|
||||
InstancePtr->ConnectCallback(InstancePtr->ConnectRef);
|
||||
}
|
||||
}
|
||||
// Check if user callback has been registered
|
||||
if (InstancePtr->IsConnectCallbackSet) {
|
||||
InstancePtr->ConnectCallback(InstancePtr->ConnectRef);
|
||||
}
|
||||
}
|
||||
|
||||
/* Vsync event has occurred */
|
||||
if ((Event) & (XV_HDMITX_PIO_IN_VS_MASK)) {
|
||||
/* Vsync event has occurred */
|
||||
if ((Event) & (XV_HDMITX_PIO_IN_VS_MASK)) {
|
||||
|
||||
// Check if user callback has been registered
|
||||
if (InstancePtr->IsVsCallbackSet) {
|
||||
InstancePtr->VsCallback(InstancePtr->VsRef);
|
||||
}
|
||||
}
|
||||
// Check if user callback has been registered
|
||||
if (InstancePtr->IsVsCallbackSet) {
|
||||
InstancePtr->VsCallback(InstancePtr->VsRef);
|
||||
}
|
||||
}
|
||||
|
||||
/* Link ready event has occurred */
|
||||
if ((Event) & (XV_HDMITX_PIO_IN_LNK_RDY_MASK)) {
|
||||
/* Link ready event has occurred */
|
||||
if ((Event) & (XV_HDMITX_PIO_IN_LNK_RDY_MASK)) {
|
||||
|
||||
// Check the link status
|
||||
if ((Data) & (XV_HDMITX_PIO_IN_LNK_RDY_MASK)) {
|
||||
// Set stream status to up
|
||||
InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_UP;
|
||||
// Check the link status
|
||||
if ((Data) & (XV_HDMITX_PIO_IN_LNK_RDY_MASK)) {
|
||||
// Set stream status to up
|
||||
InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_UP;
|
||||
|
||||
/* Enable the AUX peripheral */
|
||||
XV_HdmiTx_AuxEnable(InstancePtr);
|
||||
/* Enable the AUX peripheral */
|
||||
XV_HdmiTx_AuxEnable(InstancePtr);
|
||||
|
||||
/* Enable the AUX peripheral interrupt */
|
||||
XV_HdmiTx_AuxIntrEnable(InstancePtr);
|
||||
/* Enable the AUX peripheral interrupt */
|
||||
XV_HdmiTx_AuxIntrEnable(InstancePtr);
|
||||
|
||||
/* Enable audio */
|
||||
//XV_HdmiTx_AudioEnable(InstancePtr);
|
||||
/* Enable audio */
|
||||
//XV_HdmiTx_AudioEnable(InstancePtr);
|
||||
|
||||
// Check if user callback has been registered
|
||||
if (InstancePtr->IsStreamUpCallbackSet) {
|
||||
InstancePtr->StreamUpCallback(InstancePtr->StreamUpRef);
|
||||
}
|
||||
}
|
||||
// Check if user callback has been registered
|
||||
if (InstancePtr->IsStreamUpCallbackSet) {
|
||||
InstancePtr->StreamUpCallback(InstancePtr->StreamUpRef);
|
||||
}
|
||||
}
|
||||
|
||||
// Link down
|
||||
else {
|
||||
// Set stream status to down
|
||||
InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_DOWN;
|
||||
// Link down
|
||||
else {
|
||||
// Set stream status to down
|
||||
InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_DOWN;
|
||||
|
||||
/* Disable Audio */
|
||||
XV_HdmiTx_AudioDisable(InstancePtr);
|
||||
/* Disable Audio */
|
||||
XV_HdmiTx_AudioDisable(InstancePtr);
|
||||
|
||||
/* Disable AUX */
|
||||
XV_HdmiTx_AuxDisable(InstancePtr);
|
||||
/* Disable AUX */
|
||||
XV_HdmiTx_AuxDisable(InstancePtr);
|
||||
|
||||
// Check if user callback has been registered
|
||||
if (InstancePtr->IsStreamDownCallbackSet) {
|
||||
InstancePtr->StreamDownCallback(InstancePtr->StreamDownRef);
|
||||
}
|
||||
}
|
||||
}
|
||||
// Check if user callback has been registered
|
||||
if (InstancePtr->IsStreamDownCallbackSet) {
|
||||
InstancePtr->StreamDownCallback(InstancePtr->StreamDownRef);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
@ -315,18 +315,18 @@ static void HdmiTx_PioIntrHandler(XV_HdmiTx *InstancePtr)
|
|||
* determines the state and based on that performs required operation.
|
||||
*
|
||||
*
|
||||
* @param InstancePtr is a pointer to the HDMI TX core instance.
|
||||
* @param InstancePtr is a pointer to the HDMI TX core instance.
|
||||
*
|
||||
* @return None.
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void HdmiTx_DdcIntrHandler(XV_HdmiTx *InstancePtr)
|
||||
{
|
||||
u32 Data;
|
||||
u32 Data;
|
||||
|
||||
/* Read DDC Status register */
|
||||
Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_DDC_STA_OFFSET));
|
||||
/* Read DDC Status register */
|
||||
Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_DDC_STA_OFFSET));
|
||||
}
|
||||
|
|
32
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_selftest.c
Executable file → Normal file
32
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_selftest.c
Executable file → Normal file
|
@ -73,32 +73,32 @@
|
|||
*
|
||||
* This function reads ID of HDMI TX PIO peripheral.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
* @param InstancePtr is a pointer to the XV_HdmiTx core instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if PIO ID was matched.
|
||||
* - XST_FAILURE if PIO ID was mismatched.
|
||||
* - XST_SUCCESS if PIO ID was matched.
|
||||
* - XST_FAILURE if PIO ID was mismatched.
|
||||
*
|
||||
* @note None.
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
int XV_HdmiTx_SelfTest(XV_HdmiTx *InstancePtr)
|
||||
{
|
||||
u32 RegValue;
|
||||
u32 Status = (XST_SUCCESS);
|
||||
u32 RegValue;
|
||||
u32 Status = (XST_SUCCESS);
|
||||
|
||||
/* Verify argument. */
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
/* Verify argument. */
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
|
||||
/* Read PIO peripheral Identification register */
|
||||
RegValue = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_ID_OFFSET));
|
||||
/* Read PIO peripheral Identification register */
|
||||
RegValue = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
(XV_HDMITX_PIO_ID_OFFSET));
|
||||
|
||||
RegValue = ((RegValue) >> (XV_HDMITX_SHIFT_16)) & (XV_HDMITX_MASK_16);
|
||||
RegValue = ((RegValue) >> (XV_HDMITX_SHIFT_16)) & (XV_HDMITX_MASK_16);
|
||||
|
||||
if (RegValue != (XV_HDMITX_PIO_ID)) {
|
||||
Status = (XST_FAILURE);
|
||||
}
|
||||
if (RegValue != (XV_HDMITX_PIO_ID)) {
|
||||
Status = (XST_FAILURE);
|
||||
}
|
||||
|
||||
return Status;
|
||||
return Status;
|
||||
}
|
||||
|
|
46
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_sinit.c
Executable file → Normal file
46
XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_sinit.c
Executable file → Normal file
|
@ -76,35 +76,35 @@
|
|||
* on the core id, <i>DeviceId</i>. The return value will refer to an entry in
|
||||
* the device configuration table defined in the xv_hdmitx_g.c file.
|
||||
*
|
||||
* @param DeviceId is the unique core ID of the HDMI TX core for the
|
||||
* lookup operation.
|
||||
* @param DeviceId is the unique core ID of the HDMI TX core for the
|
||||
* lookup operation.
|
||||
*
|
||||
* @return XV_HdmiTx_LookupConfig returns a reference to a config record
|
||||
* in the configuration table (in xv_hdmitx_g.c) corresponding
|
||||
* to <i>DeviceId</i>, or NULL if no match is found.
|
||||
* @return XV_HdmiTx_LookupConfig returns a reference to a config record
|
||||
* in the configuration table (in xv_hdmitx_g.c) corresponding
|
||||
* to <i>DeviceId</i>, or NULL if no match is found.
|
||||
*
|
||||
* @note None.
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
XV_HdmiTx_Config *XV_HdmiTx_LookupConfig(u16 DeviceId)
|
||||
{
|
||||
extern XV_HdmiTx_Config
|
||||
XV_HdmiTx_ConfigTable[XPAR_XV_HDMITX_NUM_INSTANCES];
|
||||
XV_HdmiTx_Config *CfgPtr = NULL;
|
||||
u32 Index;
|
||||
extern XV_HdmiTx_Config
|
||||
XV_HdmiTx_ConfigTable[XPAR_XV_HDMITX_NUM_INSTANCES];
|
||||
XV_HdmiTx_Config *CfgPtr = NULL;
|
||||
u32 Index;
|
||||
|
||||
/* Checking for device id for which instance it is matching */
|
||||
for (Index = (u32)0x0; Index < (u32)(XPAR_XV_HDMITX_NUM_INSTANCES);
|
||||
Index++) {
|
||||
/* Checking for device id for which instance it is matching */
|
||||
for (Index = (u32)0x0; Index < (u32)(XPAR_XV_HDMITX_NUM_INSTANCES);
|
||||
Index++) {
|
||||
|
||||
/* Assigning address of config table if both device ids
|
||||
* are matched
|
||||
*/
|
||||
if (XV_HdmiTx_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XV_HdmiTx_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Assigning address of config table if both device ids
|
||||
* are matched
|
||||
*/
|
||||
if (XV_HdmiTx_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XV_HdmiTx_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (XV_HdmiTx_Config *)CfgPtr;
|
||||
}
|
||||
return (XV_HdmiTx_Config *)CfgPtr;
|
||||
}
|
||||
|
|
Loading…
Add table
Reference in a new issue