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xilskey: Added DFT control bits

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DFT control bits of efusePS for Zynq Platform is
added.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
VNSL Durga 2015-10-09 22:44:48 +05:30 • committed by Nava kishore Manne
parent 41169b9bfd
commit 1553beac28
4 changed files with 51 additions and 1 deletions
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8
lib/sw_services/xilskey/src/include/xilskey_eps.h
View file

@ -81,6 +81,14 @@ typedef struct {
* Enable the ROM code 128K crc eFUSE Bit
*/
u32 EnableRom128Crc;
/**
* Disable DFT JTAG
*/
u32 DisableDftJtag;
/**
* Disable DFT Mode
*/
u32 DisableDftMode;
/**
* EnableRsaKeyHash: Enabling this RsaKeyHashValue[32] is written to
* eFUSE array

3
lib/sw_services/xilskey/src/include/xilskey_utils.h
View file

@ -495,6 +495,9 @@ typedef enum {
XSK_EFUSEPS_ERROR_WRITE_WRITE_PROTECT_BIT=0x9600,
XSK_EFUSEPS_ERROR_READ_HASH_BEFORE_PROGRAMMING=0x9700,
XSK_EFUSEPS_ERROR_WRTIE_DFT_JTAG_DIS_BIT = 0x9800,
XSK_EFUSEPS_ERROR_WRTIE_DFT_MODE_DIS_BIT = 0x9900,
/**
* XSKEfusePs_Read() error codes
*/

28
lib/sw_services/xilskey/src/xilskey_eps.c
View file

@ -46,6 +46,8 @@
* 2.00 hk 23/01/14 Changed PS efuse error codes for voltage out of range.
* 2.1 sk 04/03/15 Initialized RSAKeyReadback with Zeros CR# 829723.
* 3.00 vns 31/07/15 Removed redundant code to initialise timer.
* 4.00 vns 09/10/15 Added DFT control bits programming fecility for
* eFuse PS on Zynq. PR#862778
*
*****************************************************************************/
@ -117,7 +119,11 @@ u32 XilSKey_EfusePs_Write(XilSKey_EPs *InstancePtr)
((InstancePtr->EnableRom128Crc != TRUE) &&
(InstancePtr->EnableRom128Crc != FALSE)) ||
((InstancePtr->EnableRsaKeyHash != TRUE) &&
(InstancePtr->EnableRsaKeyHash != FALSE)) ) {
(InstancePtr->EnableRsaKeyHash != FALSE)) ||
((InstancePtr->DisableDftJtag != TRUE) &&
(InstancePtr->DisableDftJtag != FALSE)) ||
((InstancePtr->DisableDftMode != TRUE) &&
(InstancePtr->DisableDftMode != FALSE))) {
return XSK_EFUSEPS_ERROR_PS_PARAMETER_WRONG;
}
@ -265,6 +271,26 @@ u32 XilSKey_EfusePs_Write(XilSKey_EPs *InstancePtr)
}
}
/* Programs 0xC eFuse bit to disable DFT JTAG */
if (InstancePtr->DisableDftJtag) {
Status = XilSKey_EfusePs_WriteWithXadcCheckAndVerify(
XSK_EFUSEPS_APB_DFT_JTAG_DISABLE, RefClk);
if (Status != XST_SUCCESS) {
RetValue = XSK_EFUSEPS_ERROR_WRTIE_DFT_JTAG_DIS_BIT + Status;
goto ExitCtrlResetStatus;
}
}
/* Programs 0xD eFuse bit to disable DFT Mode */
if (InstancePtr->DisableDftMode) {
Status = XilSKey_EfusePs_WriteWithXadcCheckAndVerify(
XSK_EFUSEPS_APB_DFT_MODE_DISABLE, RefClk);
if (Status != XST_SUCCESS) {
RetValue = XSK_EFUSEPS_ERROR_WRTIE_DFT_MODE_DIS_BIT + Status;
goto ExitCtrlResetStatus;
}
}
ExitCtrlResetStatus:
/**
* Disable Programming, write and read

13
lib/sw_services/xilskey/src/xilskey_epshw.h
View file

@ -42,6 +42,7 @@
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 1.00a rpoolla 04/26/13 First release
* 4.00 vns 09/10/15 Added DFT control bits addresses
*
*****************************************************************************/
@ -262,6 +263,14 @@ extern "C" {
* eFUSE APB address for RSA authentication enable offset
*/
#define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET (0x2C)
/**
* eFUSE DFT JTAG disable
*/
#define XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET (0x30)
/**
* eFUSE DFT mode disable
*/
#define XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET (0x34)
/**
* eFUSE APB address for RSA uart status enable on MIO48 offset
*/
@ -365,6 +374,10 @@ extern "C" {
* eFUSE APB address for RSA authentication enable
*/
#define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET)
/* eFuse DFT JTAG disable */
#define XSK_EFUSEPS_APB_DFT_JTAG_DISABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET)
/* eFuse DFT mode disable */
#define XSK_EFUSEPS_APB_DFT_MODE_DISABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET)
/*
* eFUSE APB address for RSA uart status enable on MIO48
*/