vdma: Add support for 64 bit vdma
This patch adds support for 64 bit vdma. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
This commit is contained in:
Anurag Kumar Vulisha
Nava kishore Manne
parent
187e18e3dc
commit
1728d93515
8 changed files with 83 additions and 54 deletions
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@ -37,7 +37,7 @@ BEGIN driver axivdma
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OPTION supported_peripherals = (axi_vdma_v[4-9]_[0-9][0-9]_[a-z] axi_vdma_v[4-9]_[0-9]);
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OPTION driver_state = ACTIVE;
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OPTION copyfiles = all;
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OPTION VERSION = 5.1;
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OPTION VERSION = 6.0;
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OPTION NAME = axivdma;
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END driver
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@ -59,9 +59,9 @@
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#uses "xillib.tcl"
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proc generate {drv_handle} {
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xdefine_vdma_include_file $drv_handle "xparameters.h" "XAxiVdma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_AXI_MM2S_ACLK_FREQ_HZ" "C_AXI_S2MM_ACLK_FREQ_HZ" "C_MM2S_GENLOCK_MODE" "C_MM2S_GENLOCK_NUM_MASTERS" "C_S2MM_GENLOCK_MODE" "C_S2MM_GENLOCK_NUM_MASTERS" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL"
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xdefine_vdma_canonical_xpars $drv_handle "xparameters.h" "AxiVdma" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_AXI_MM2S_ACLK_FREQ_HZ" "C_AXI_S2MM_ACLK_FREQ_HZ" "C_MM2S_GENLOCK_MODE" "C_MM2S_GENLOCK_NUM_MASTERS" "C_S2MM_GENLOCK_MODE" "C_S2MM_GENLOCK_NUM_MASTERS" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL"
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::hsi::utils::define_config_file $drv_handle "xaxivdma_g.c" "XAxiVdma" "DEVICE_ID" "C_BASEADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_MM2S_GENLOCK_MODE" "C_S2MM_GENLOCK_MODE" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL"
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xdefine_vdma_include_file $drv_handle "xparameters.h" "XAxiVdma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_AXI_MM2S_ACLK_FREQ_HZ" "C_AXI_S2MM_ACLK_FREQ_HZ" "C_MM2S_GENLOCK_MODE" "C_MM2S_GENLOCK_NUM_MASTERS" "C_S2MM_GENLOCK_MODE" "C_S2MM_GENLOCK_NUM_MASTERS" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL" "c_addr_width"
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xdefine_vdma_canonical_xpars $drv_handle "xparameters.h" "AxiVdma" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_AXI_MM2S_ACLK_FREQ_HZ" "C_AXI_S2MM_ACLK_FREQ_HZ" "C_MM2S_GENLOCK_MODE" "C_MM2S_GENLOCK_NUM_MASTERS" "C_S2MM_GENLOCK_MODE" "C_S2MM_GENLOCK_NUM_MASTERS" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL" "c_addr_width"
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::hsi::utils::define_config_file $drv_handle "xaxivdma_g.c" "XAxiVdma" "DEVICE_ID" "C_BASEADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_MM2S_GENLOCK_MODE" "C_S2MM_GENLOCK_MODE" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL" "c_addr_width"
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}
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@ -121,8 +121,8 @@
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#else
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#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
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DEFAULT SET TO 0x01000000
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#define DDR_BASE_ADDR 0x01000000
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#define DDR_HIGH_ADDR 0x0F000000
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#define DDR_BASE_ADDR 0x10000000
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#define DDR_HIGH_ADDR 0x20000000
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#endif
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/* Memory space for the frame buffers
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@ -172,9 +172,9 @@
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* Note that SUBFRAME_HORIZONTAL_SIZE and SUBFRAME_VERTICAL_SIZE must ensure
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* to be inside the frame.
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*/
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#define SUBFRAME_START_OFFSET (FRAME_HORIZONTAL_LEN * 5 + 32)
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#define SUBFRAME_HORIZONTAL_SIZE 100
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#define SUBFRAME_VERTICAL_SIZE 100
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#define SUBFRAME_START_OFFSET (FRAME_HORIZONTAL_LEN * 5 + 64)
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#define SUBFRAME_HORIZONTAL_SIZE 0x100
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#define SUBFRAME_VERTICAL_SIZE 0x100
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/* Number of frames to work on, this is to set the frame count threshold
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*
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@ -214,11 +214,11 @@ static XScuGic Intc; /* Instance of the Interrupt Controller */
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*
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* Read and write sub-frame use the same settings
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*/
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static u32 ReadFrameAddr;
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static u32 WriteFrameAddr;
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static u32 BlockStartOffset;
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static u32 BlockHoriz;
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static u32 BlockVert;
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static UINTPTR ReadFrameAddr;
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static UINTPTR WriteFrameAddr;
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static UINTPTR BlockStartOffset;
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static UINTPTR BlockHoriz;
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static UINTPTR BlockVert;
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/* DMA channel setup
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*/
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@ -441,6 +441,13 @@ int main(void)
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/* Enable your video IP interrupts if needed
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*/
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/* Enable DMA read and write channel interrupts
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*
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* If interrupts overwhelms the system, please do not enable interrupt
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*/
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XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_WRITE);
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XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_READ);
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/* Start the DMA engine to transfer
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*/
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Status = StartTransfer(&AxiVdma);
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@ -450,13 +457,6 @@ int main(void)
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return XST_FAILURE;
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}
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/* Enable DMA read and write channel interrupts
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*
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* If interrupts overwhelms the system, please do not enable interrupt
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*/
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XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_WRITE);
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XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_READ);
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/* Every set of frame buffer finish causes a completion interrupt
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*/
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while ((WriteDone < NUM_TEST_FRAME_SETS) && !ReadError &&
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@ -503,7 +503,7 @@ int main(void)
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static int ReadSetup(XAxiVdma *InstancePtr)
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{
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int Index;
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u32 Addr;
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UINTPTR Addr;
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int Status;
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ReadCfg.VertSizeInput = SUBFRAME_VERTICAL_SIZE;
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@ -569,7 +569,7 @@ static int ReadSetup(XAxiVdma *InstancePtr)
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static int WriteSetup(XAxiVdma * InstancePtr)
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{
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int Index;
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u32 Addr;
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UINTPTR Addr;
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int Status;
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WriteCfg.VertSizeInput = SUBFRAME_VERTICAL_SIZE;
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@ -163,6 +163,7 @@ int XAxiVdma_CfgInitialize(XAxiVdma *InstancePtr, XAxiVdma_Config *CfgPtr,
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InstancePtr->HasS2Mm = CfgPtr->HasS2Mm;
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InstancePtr->UseFsync = CfgPtr->UseFsync;
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InstancePtr->InternalGenLock = CfgPtr->InternalGenLock;
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InstancePtr->AddrWidth = CfgPtr->AddrWidth;
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if (XAxiVdma_Major(InstancePtr) < 3) {
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InstancePtr->HasSG = 1;
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@ -205,6 +206,7 @@ int XAxiVdma_CfgInitialize(XAxiVdma *InstancePtr, XAxiVdma_Config *CfgPtr,
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RdChannel->HasDRE = CfgPtr->HasMm2SDRE;
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RdChannel->WordLength = CfgPtr->Mm2SWordLen >> 3;
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RdChannel->StreamWidth = CfgPtr->Mm2SStreamWidth >> 3;
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RdChannel->AddrWidth = InstancePtr->AddrWidth;
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/* Internal GenLock */
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RdChannel->GenLock = CfgPtr->Mm2SGenLock;
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@ -266,6 +268,7 @@ int XAxiVdma_CfgInitialize(XAxiVdma *InstancePtr, XAxiVdma_Config *CfgPtr,
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WrChannel->StartAddrBase = InstancePtr->BaseAddr +
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XAXIVDMA_S2MM_ADDR_OFFSET;
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WrChannel->NumFrames = CfgPtr->MaxFrameStoreNum;
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WrChannel->AddrWidth = InstancePtr->AddrWidth;
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/* Flush on Sync */
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WrChannel->FlushonFsync = CfgPtr->FlushonFsync;
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@ -1007,7 +1010,7 @@ int XAxiVdma_DmaConfig(XAxiVdma *InstancePtr, u16 Direction,
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*
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*****************************************************************************/
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int XAxiVdma_DmaSetBufferAddr(XAxiVdma *InstancePtr, u16 Direction,
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u32 *BufferAddrSet)
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UINTPTR *BufferAddrSet)
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{
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XAxiVdma_Channel *Channel;
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@ -396,7 +396,7 @@ typedef void (*XAxiVdma_ErrorCallBack) (void *CallBackRef, u32 ErrorMask);
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*/
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typedef struct {
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u16 DeviceId; /**< DeviceId is the unique ID of the device */
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u32 BaseAddress; /**< BaseAddress is the physical base address of the
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UINTPTR BaseAddress; /**< BaseAddress is the physical base address of the
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* device's registers */
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u16 MaxFrameStoreNum; /**< The maximum number of Frame Stores */
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int HasMm2S; /**< Whether hw build has read channel */
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@ -447,6 +447,7 @@ typedef struct {
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int EnableAllDbgFeatures;/**< Enable all Debug features
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This corresponds to C_ENABLE_DEBUG_ALL
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configuration parameter */
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int AddrWidth; /**< Address Width */
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} XAxiVdma_Config;
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/**
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@ -464,7 +465,7 @@ typedef struct {
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int EnableSync; /**< Gen-Lock Mode? */
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int PointNum; /**< Master we synchronize with */
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int EnableFrameCounter; /**< Frame Counter Enable */
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u32 FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE];
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UINTPTR FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE];
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/**< Start Addresses of Frame Store Buffers. */
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int FixedFrameStoreAddr;/**< Fixed Frame Store Address index */
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int GenLockRepeat; /**< Gen-Lock Repeat? */
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@ -497,7 +498,7 @@ typedef struct {
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* The XAxiVdma driver instance data.
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*/
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typedef struct {
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u32 BaseAddr; /**< Memory address for this device */
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UINTPTR BaseAddr; /**< Memory address for this device */
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int HasSG; /**< Whether hardware has SG engine */
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int IsReady; /**< Whether driver is initialized */
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@ -516,6 +517,7 @@ typedef struct {
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XAxiVdma_Channel ReadChannel; /**< Channel to read from memory */
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XAxiVdma_Channel WriteChannel; /**< Channel to write to memory */
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int AddrWidth; /**< Address Width */
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} XAxiVdma;
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@ -571,7 +573,7 @@ int XAxiVdma_StartReadFrame(XAxiVdma *InstancePtr,
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int XAxiVdma_DmaConfig(XAxiVdma *InstancePtr, u16 Direction,
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XAxiVdma_DmaSetup *DmaConfigPtr);
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int XAxiVdma_DmaSetBufferAddr(XAxiVdma *InstancePtr, u16 Direction,
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u32 *BufferAddrSet);
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UINTPTR *BufferAddrSet);
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int XAxiVdma_DmaStart(XAxiVdma *InstancePtr, u16 Direction);
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void XAxiVdma_DmaStop(XAxiVdma *InstancePtr, u16 Direction);
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void XAxiVdma_DmaRegisterDump(XAxiVdma *InstancePtr, u16 Direction);
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@ -595,4 +597,3 @@ int XAxiVdma_Selftest(XAxiVdma * InstancePtr);
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#endif
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#endif /* end of protection macro */
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/** @} */
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@ -207,7 +207,7 @@ void XAxiVdma_ChannelInit(XAxiVdma_Channel *Channel)
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}
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XAxiVdma_BdSetNextPtr(BdPtr,
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XAXIVDMA_VIRT_TO_PHYS((u32)NextBdPtr));
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XAXIVDMA_VIRT_TO_PHYS((UINTPTR)NextBdPtr));
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}
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Channel->AllCnt = NumFrames;
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@ -215,11 +215,11 @@ void XAxiVdma_ChannelInit(XAxiVdma_Channel *Channel)
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/* Setup the BD addresses so that access the head/tail BDs fast
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*
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*/
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Channel->HeadBdAddr = (u32)FirstBdPtr;
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Channel->HeadBdPhysAddr = XAXIVDMA_VIRT_TO_PHYS((u32)FirstBdPtr);
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Channel->HeadBdAddr = (UINTPTR)FirstBdPtr;
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Channel->HeadBdPhysAddr = XAXIVDMA_VIRT_TO_PHYS((UINTPTR)FirstBdPtr);
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Channel->TailBdAddr = (u32)LastBdPtr;
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Channel->TailBdPhysAddr = XAXIVDMA_VIRT_TO_PHYS((u32)LastBdPtr);
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Channel->TailBdAddr = (UINTPTR)LastBdPtr;
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Channel->TailBdPhysAddr = XAXIVDMA_VIRT_TO_PHYS((UINTPTR)LastBdPtr);
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Channel->IsValid = 1;
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@ -492,13 +492,13 @@ void XAxiVdma_ChannelStartFrmCntEnable(XAxiVdma_Channel *Channel)
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* to hold all the BDs.
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*
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*****************************************************************************/
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int XAxiVdma_ChannelSetBdAddrs(XAxiVdma_Channel *Channel, u32 BdAddrPhys,
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u32 BdAddrVirt)
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int XAxiVdma_ChannelSetBdAddrs(XAxiVdma_Channel *Channel, UINTPTR BdAddrPhys,
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UINTPTR BdAddrVirt)
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{
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int NumFrames = Channel->AllCnt;
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int i;
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u32 NextPhys = BdAddrPhys;
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u32 CurrVirt = BdAddrVirt;
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UINTPTR NextPhys = BdAddrPhys;
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UINTPTR CurrVirt = BdAddrVirt;
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if (Channel->HasSG && XAxiVdma_ChannelIsBusy(Channel)) {
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xdbg_printf(XDBG_DEBUG_ERROR,
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@ -851,12 +851,17 @@ int XAxiVdma_ChannelConfig(XAxiVdma_Channel *Channel,
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*
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*****************************************************************************/
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int XAxiVdma_ChannelSetBufferAddr(XAxiVdma_Channel *Channel,
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u32 *BufferAddrSet, int NumFrames)
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UINTPTR *BufferAddrSet, int NumFrames)
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{
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int i;
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u32 WordLenBits;
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int HiFrmAddr = 0;
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int FrmBound = (XAXIVDMA_MAX_FRAMESTORE)/2 - 1;
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int FrmBound;
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if (Channel->AddrWidth > 32) {
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FrmBound = (XAXIVDMA_MAX_FRAMESTORE_64)/2 - 1;
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} else {
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FrmBound = (XAXIVDMA_MAX_FRAMESTORE)/2 - 1;
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}
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int Loop16 = 0;
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if (!Channel->IsValid) {
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@ -896,10 +901,25 @@ int XAxiVdma_ChannelSetBufferAddr(XAxiVdma_Channel *Channel,
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Loop16 = 0;
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}
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XAxiVdma_WriteReg(Channel->StartAddrBase,
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XAXIVDMA_START_ADDR_OFFSET +
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Loop16 * XAXIVDMA_START_ADDR_LEN,
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BufferAddrSet[i]);
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if (Channel->AddrWidth > 32) {
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/* For a 40-bit address XAXIVDMA_MAX_FRAMESTORE
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* value should be set to 16 */
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XAxiVdma_WriteReg(Channel->StartAddrBase,
|
||||
XAXIVDMA_START_ADDR_OFFSET +
|
||||
Loop16 * XAXIVDMA_START_ADDR_LEN + i*4,
|
||||
LOWER_32_BITS(BufferAddrSet[i]));
|
||||
|
||||
XAxiVdma_WriteReg(Channel->StartAddrBase,
|
||||
XAXIVDMA_START_ADDR_MSB_OFFSET +
|
||||
Loop16 * XAXIVDMA_START_ADDR_LEN + i*4,
|
||||
UPPER_32_BITS((u64)BufferAddrSet[i]));
|
||||
} else {
|
||||
XAxiVdma_WriteReg(Channel->StartAddrBase,
|
||||
XAXIVDMA_START_ADDR_OFFSET +
|
||||
Loop16 * XAXIVDMA_START_ADDR_LEN,
|
||||
BufferAddrSet[i]);
|
||||
}
|
||||
|
||||
|
||||
if ((NumFrames > FrmBound) && (i == (NumFrames - 1)))
|
||||
XAxiVdma_ChannelHiFrmAddrDisable(Channel);
|
||||
|
|
@ -1309,7 +1329,7 @@ u32 XAxiVdma_ChannelGetEnabledIntr(XAxiVdma_Channel *Channel)
|
|||
*****************************************************************************/
|
||||
static u32 XAxiVdma_BdRead(XAxiVdma_Bd *BdPtr, int Offset)
|
||||
{
|
||||
return (*(u32 *)((u32)BdPtr + Offset));
|
||||
return (*(u32 *)((UINTPTR)(void *)BdPtr + Offset));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
|
@ -1326,7 +1346,7 @@ static u32 XAxiVdma_BdRead(XAxiVdma_Bd *BdPtr, int Offset)
|
|||
*****************************************************************************/
|
||||
static void XAxiVdma_BdWrite(XAxiVdma_Bd *BdPtr, int Offset, u32 Value)
|
||||
{
|
||||
*(u32 *)((u32)BdPtr + Offset) = Value;
|
||||
*(u32 *)((UINTPTR)(void *)BdPtr + Offset) = Value;
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -96,6 +96,8 @@ extern "C" {
|
|||
*/
|
||||
#define XAXIVDMA_MAX_FRAMESTORE 32 /**< Maximum # of the frame store */
|
||||
|
||||
#define XAXIVDMA_MAX_FRAMESTORE_64 16 /**< Maximum # of the frame store for 64 bit*/
|
||||
|
||||
/*@}*/
|
||||
|
||||
/** @name Maximum transfer length
|
||||
|
|
@ -164,6 +166,8 @@ extern "C" {
|
|||
#define XAXIVDMA_STRD_FRMDLY_OFFSET 0x00000008 /**< Horizontal size */
|
||||
#define XAXIVDMA_START_ADDR_OFFSET 0x0000000C /**< Start of address */
|
||||
#define XAXIVDMA_START_ADDR_LEN 0x00000004 /**< Each entry is 4 bytes */
|
||||
#define XAXIVDMA_START_ADDR_MSB_OFFSET 0x00000010 /**< Start of address */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/** @name Bitmasks of the XAXIVDMA_CR_OFFSET register
|
||||
|
|
|
|||
|
|
@ -100,10 +100,10 @@ typedef struct {
|
|||
int WordLength; /* Word length */
|
||||
int NumFrames; /* Number of frames to work on */
|
||||
|
||||
u32 HeadBdPhysAddr; /* Physical address of the first BD */
|
||||
u32 HeadBdAddr; /* Virtual address of the first BD */
|
||||
u32 TailBdPhysAddr; /* Physical address of the last BD */
|
||||
u32 TailBdAddr; /* Virtual address of the last BD */
|
||||
UINTPTR HeadBdPhysAddr; /* Physical address of the first BD */
|
||||
UINTPTR HeadBdAddr; /* Virtual address of the first BD */
|
||||
UINTPTR TailBdPhysAddr; /* Physical address of the last BD */
|
||||
UINTPTR TailBdAddr; /* Virtual address of the last BD */
|
||||
int Hsize; /* Horizontal size */
|
||||
int Vsize; /* Vertical size saved for no-sg mode hw start */
|
||||
|
||||
|
|
@ -115,6 +115,7 @@ typedef struct {
|
|||
XAxiVdma_Bd BDs[XAXIVDMA_MAX_FRAMESTORE] __attribute__((__aligned__(32)));
|
||||
/*Statically allocated BDs */
|
||||
u32 DbgFeatureFlags; /* Debug Parameter Flags */
|
||||
int AddrWidth;
|
||||
}XAxiVdma_Channel;
|
||||
|
||||
/* Duplicate layout of XAxiVdma_DmaSetup
|
||||
|
|
@ -131,7 +132,7 @@ typedef struct {
|
|||
int EnableSync; /**< Gen-Lock Mode? */
|
||||
int PointNum; /**< Master we synchronize with */
|
||||
int EnableFrameCounter; /**< Frame Counter Enable */
|
||||
u32 FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE];
|
||||
UINTPTR FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE];
|
||||
/**< Start Addresses of Frame Store Buffers. */
|
||||
int FixedFrameStoreAddr;/**< Fixed Frame Store Address index */
|
||||
int GenLockRepeat; /**< Gen-Lock Repeat? */
|
||||
|
|
@ -159,11 +160,11 @@ u32 XAxiVdma_ChannelGetEnabledIntr(XAxiVdma_Channel *Channel);
|
|||
void XAxiVdma_ChannelIntrClear(XAxiVdma_Channel *Channel, u32 IntrType);
|
||||
int XAxiVdma_ChannelStartTransfer(XAxiVdma_Channel *Channel,
|
||||
XAxiVdma_ChannelSetup *ChannelCfgPtr);
|
||||
int XAxiVdma_ChannelSetBdAddrs(XAxiVdma_Channel *Channel, u32 BdAddrPhys,
|
||||
u32 BdAddrVirt);
|
||||
int XAxiVdma_ChannelSetBdAddrs(XAxiVdma_Channel *Channel, UINTPTR BdAddrPhys,
|
||||
UINTPTR BdAddrVirt);
|
||||
int XAxiVdma_ChannelConfig(XAxiVdma_Channel *Channel,
|
||||
XAxiVdma_ChannelSetup *ChannelCfgPtr);
|
||||
int XAxiVdma_ChannelSetBufferAddr(XAxiVdma_Channel *Channel, u32 *AddrSet,
|
||||
int XAxiVdma_ChannelSetBufferAddr(XAxiVdma_Channel *Channel, UINTPTR *AddrSet,
|
||||
int NumFrames);
|
||||
int XAxiVdma_ChannelStart(XAxiVdma_Channel *Channel);
|
||||
void XAxiVdma_ChannelStop(XAxiVdma_Channel *Channel);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue