dptx: Reduced the RX capability read to 16 bytes.

No need to read and store unused capability information by the driver.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-01-07 12:07:51 -08:00 committed by Suneel Garapati
parent ede61d44cf
commit 1c9f00c076
2 changed files with 13 additions and 16 deletions

View file

@ -325,7 +325,7 @@ u32 XDptx_GetRxCapabilities(XDptx *InstancePtr)
}
Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_RECEIVER_CAP_FIELD_START,
XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE, Dpcd);
16, Dpcd);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}

View file

@ -351,21 +351,18 @@ typedef struct {
* This typedef contains configuration information about the RX device.
*/
typedef struct {
u8 DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE];
/**< The raw capabilities field
of the RX device's DisplayPort
Configuration Data (DPCD). */
u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the
RX device's status registers.
The first 4 bytes correspond to
the lane status associated with
clock recovery, channel
equalization, symbol lock, and
interlane alignment. The
remaining 2 bytes represent the
pre-emphasis and voltage swing
level adjustments requested by
the RX device. */
u8 DpcdRxCapsField[16]; /**< The first 16 bytes of the raw capabilities
field of the RX device's DisplayPort
Configuration Data (DPCD). */
u8 LaneStatusAdjReqs[6];/**< This is a raw read of the RX device's
status registers. The first 4 bytes
correspond to the lane status associated
with clock recovery, channel
equalization, symbol lock, and interlane
alignment. The remaining 2 bytes
represent the pre-emphasis and voltage
swing level adjustments requested by the
RX device. */
} XDptx_SinkConfig;
/**