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PMUFW: PM: master: Using unique ipiMask to encode master's bitfield in IPI

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-Every master has unique bitfield in all IPI registers
-PMU power management accesses status, trigger and enable registers
 for a master using the unique master's ipiMask now

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
This commit is contained in:
Mirela Simonovic 2015-05-21 17:51:23 +02:00 • committed by Nava kishore Manne
parent 1bd06b620c
commit 245017b13c
4 changed files with 4 additions and 9 deletions
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6
lib/sw_apps/zynqmp_pmufw/src/pm_callbacks.c
View file

@ -59,7 +59,7 @@ void PmAcknowledgeCb(const PmMaster* const master, const PmNodeId nodeId,
status);
XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 3 * PAYLOAD_ELEM_SIZE,
oppoint);
XPfw_Write32(IPI_PMU_0_TRIG, master->ipiTrigMask);
XPfw_Write32(IPI_PMU_0_TRIG, master->ipiMask);
}
/**
@ -78,7 +78,7 @@ void PmNotifyCb(const PmMaster* const master, const PmNodeId nodeId,
event);
XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 3 * PAYLOAD_ELEM_SIZE,
oppoint);
XPfw_Write32(IPI_PMU_0_TRIG, master->ipiTrigMask);
XPfw_Write32(IPI_PMU_0_TRIG, master->ipiMask);
}
/**
@ -107,5 +107,5 @@ void PmInitSuspendCb(const PmMaster* const master, const PmNodeId nodeId,
state);
XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 5 * PAYLOAD_ELEM_SIZE,
timeout);
XPfw_Write32(IPI_PMU_0_TRIG, master->ipiTrigMask);
XPfw_Write32(IPI_PMU_0_TRIG, master->ipiMask);
}

3
lib/sw_apps/zynqmp_pmufw/src/pm_master.c
View file

@ -224,7 +224,6 @@ PmMaster pmMasterApu_g = {
.procs = pmApuProcs_g,
.procsCnt = PM_PROC_APU_MAX,
.ipiMask = IPI_PMU_0_IER_APU_MASK,
.ipiTrigMask = IPI_PMU_0_TRIG_APU_MASK,
.pmuBuffer = IPI_BUFFER_PMU_BASE + IPI_BUFFER_TARGET_APU_OFFSET,
.buffer = IPI_BUFFER_APU_BASE + IPI_BUFFER_TARGET_PMU_OFFSET,
.reqs = pmApuReq_g,
@ -240,7 +239,6 @@ PmMaster pmMasterRpu0_g = {
.procs = &pmRpuProcs_g[PM_PROC_RPU_0],
.procsCnt = 1U,
.ipiMask = IPI_PMU_0_IER_RPU_0_MASK,
.ipiTrigMask = IPI_PMU_0_TRIG_RPU_0_MASK,
.pmuBuffer = IPI_BUFFER_PMU_BASE + IPI_BUFFER_TARGET_RPU_0_OFFSET,
.buffer = IPI_BUFFER_RPU_0_BASE + IPI_BUFFER_TARGET_PMU_OFFSET,
.reqs = pmRpu0Req_g,
@ -256,7 +254,6 @@ PmMaster pmMasterRpu1_g = {
.procs = &pmRpuProcs_g[PM_PROC_RPU_1],
.procsCnt = 1U,
.ipiMask = IPI_PMU_0_IER_RPU_1_MASK,
.ipiTrigMask = IPI_PMU_0_TRIG_RPU_1_MASK,
.pmuBuffer = IPI_BUFFER_PMU_BASE + IPI_BUFFER_TARGET_RPU_1_OFFSET,
.buffer = IPI_BUFFER_RPU_1_BASE + IPI_BUFFER_TARGET_PMU_OFFSET,
.reqs = NULL, /* lockstep mode is assumed for now */

2
lib/sw_apps/zynqmp_pmufw/src/pm_master.h
View file

@ -136,7 +136,6 @@ typedef struct {
* @procs Pointer to the array of processors within the master
* @procsCnt Number of processors within the master
* @ipiMask Mask dedicated to the master in IPI registers
* @ipiTrigMask Trigger mask dedicated to the master in IPI registers
* @pmuBuffer IPI buffer address into which PMU can write (PMU's buffer)
* @buffer IPI buffer address into which this master can write
* (master's buffer)
@ -150,7 +149,6 @@ typedef struct PmMaster {
PmProc* const procs;
const u8 procsCnt;
const u32 ipiMask;
const u32 ipiTrigMask;
const u32 pmuBuffer;
const u32 buffer;
PmRequirement* const reqs;

2
lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h
View file

@ -1,4 +1,4 @@
#ifndef ZYNQMP_XPFW_VERSION__H_
#define ZYNQMP_XPFW_VERSION__H_
#define ZYNQMP_XPFW_VERSION "2015.1-swbeta2-33-gaa7ad30df6b5"
#define ZYNQMP_XPFW_VERSION "2015.1-swbeta2-34-gd56779b12d91"
#endif