245017b13c
-Every master has unique bitfield in all IPI registers -PMU power management accesses status, trigger and enable registers for a master using the unique master's ipiMask now Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
111 lines
4.7 KiB
C
111 lines
4.7 KiB
C
/*
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* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*/
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/*********************************************************************
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* PM callbacks interface.
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* Used by the power management to send a message to the PM master and
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* optionally generate interrupt using IPI.
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*********************************************************************/
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#include "pm_callbacks.h"
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#include "pm_defs.h"
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#include "pm_api.h"
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#include "ipi_buffer.h"
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/**
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* PmAcknowledgeCb() - sends acknowledge via callback
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* @master Master who is blocked and waiting for the acknowledge
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* @nodeId Node id of the node in question
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* @status Status of the PM operation
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* @oppoint Operating point of the node in question
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*
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* @note Master is not blocked waiting for this acknowledge. Master
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* acknowledge through the IPI interrupt and registered callback.
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*/
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void PmAcknowledgeCb(const PmMaster* const master, const PmNodeId nodeId,
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const u32 status, const u32 oppoint)
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{
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, PM_ACKNOWLEDGE_CB);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + PAYLOAD_ELEM_SIZE,
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nodeId);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 2 * PAYLOAD_ELEM_SIZE,
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status);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 3 * PAYLOAD_ELEM_SIZE,
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oppoint);
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XPfw_Write32(IPI_PMU_0_TRIG, master->ipiMask);
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}
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/**
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* PmNotifyCb() - notifies a master about an event occurance
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* @nodeId Node id regarding which the event is triggered
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* @event Event to informa master about
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* @oppoint Optionally event is related to some operating point change
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*/
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void PmNotifyCb(const PmMaster* const master, const PmNodeId nodeId,
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const u32 event, const u32 oppoint)
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{
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, PM_NOTIFY_CB);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + PAYLOAD_ELEM_SIZE,
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nodeId);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 2 * PAYLOAD_ELEM_SIZE,
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event);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 3 * PAYLOAD_ELEM_SIZE,
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oppoint);
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XPfw_Write32(IPI_PMU_0_TRIG, master->ipiMask);
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}
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/**
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* PmInitSuspendCb() - request a master to suspend itself
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* @nodeId Node within the master to be suspended
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* @reason The reason of initiating the suspend
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* @latency Not supported
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* @state State to which the master should suspend
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* @timeout How much time the master has to respond
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*/
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void PmInitSuspendCb(const PmMaster* const master, const PmNodeId nodeId,
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const u32 reason, const u32 latency, const u32 state,
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const u32 timeout)
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{
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PmDbg("of %s (%d, %d, %d, %d)\n", PmStrNode(nodeId), reason, latency,
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state, timeout);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, PM_INIT_SUSPEND_CB);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + PAYLOAD_ELEM_SIZE,
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nodeId);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 2 * PAYLOAD_ELEM_SIZE,
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reason);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 3 * PAYLOAD_ELEM_SIZE,
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latency);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 4 * PAYLOAD_ELEM_SIZE,
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state);
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XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 5 * PAYLOAD_ELEM_SIZE,
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timeout);
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XPfw_Write32(IPI_PMU_0_TRIG, master->ipiMask);
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}
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