dptx: Exporting additional IP configuration parameters.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
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37cee8b315
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3 changed files with 41 additions and 13 deletions
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@ -30,9 +30,9 @@
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##
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##*****************************************************************************/
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proc generate {drv_handle} {
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xdefine_include_file $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "S_AXI_ACLK"
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xdefine_config_file $drv_handle "xdptx_g.c" "XDptx" "DEVICE_ID" "C_BASEADDR" "S_AXI_ACLK" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE"
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xdefine_canonical_xpars $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "S_AXI_ACLK"
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xdefine_include_file $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "S_AXI_ACLK"
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xdefine_config_file $drv_handle "xdptx_g.c" "XDptx" "DEVICE_ID" "C_BASEADDR" "S_AXI_ACLK" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION"
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xdefine_canonical_xpars $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "S_AXI_ACLK"
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}
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#
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@ -247,8 +247,23 @@ void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
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InstancePtr->Config.BaseAddr = EffectiveAddr;
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InstancePtr->Config.SAxiClkHz = ConfigPtr->SAxiClkHz;
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InstancePtr->Config.MaxLinkRate = ConfigPtr->MaxLinkRate;
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InstancePtr->Config.MaxLaneCount = ConfigPtr->MaxLaneCount;
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InstancePtr->Config.MaxLinkRate = ConfigPtr->MaxLinkRate;
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InstancePtr->Config.MaxBitsPerColor = ConfigPtr->MaxBitsPerColor;
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InstancePtr->Config.QuadPixelEn = ConfigPtr->QuadPixelEn;
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InstancePtr->Config.DualPixelEn = ConfigPtr->DualPixelEn;
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InstancePtr->Config.YCrCbEn = ConfigPtr->YCrCbEn;
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InstancePtr->Config.YOnlyEn = ConfigPtr->YOnlyEn;
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InstancePtr->Config.PayloadDataWidth = ConfigPtr->PayloadDataWidth;
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InstancePtr->Config.SecondaryChEn = ConfigPtr->SecondaryChEn;
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InstancePtr->Config.NumAudioChs = ConfigPtr->NumAudioChs;
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InstancePtr->Config.MstSupport = ConfigPtr->MstSupport;
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InstancePtr->Config.NumMstStreams = ConfigPtr->NumMstStreams;
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InstancePtr->Config.DpProtocol = ConfigPtr->DpProtocol;
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/* Set the DisplayPort TX's voltage swing and pre-emphasis levels to
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* their defaults. */
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@ -337,23 +337,36 @@ typedef enum {
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*/
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typedef struct {
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u16 DeviceId; /**< Device instance ID. */
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u32 BaseAddr; /**< The base address of the core. */
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u32 SAxiClkHz; /**< The clock frequency of the core's
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u32 BaseAddr; /**< The base address of the core instance. */
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u32 SAxiClkHz; /**< The clock frequency of the core instance's
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S_AXI_ACLK port. */
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u8 MaxLaneCount; /**< The maximum lane count supported by this
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core's instance. */
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core instance. */
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u8 MaxLinkRate; /**< The maximum link rate supported by this
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core's instance. */
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core instance. */
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u8 MaxBitsPerColor; /**< The maximum bits/color supported by this
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core's instance*/
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u8 QuadPixelEn; /**< Quad pixel support by this core's
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core instance*/
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u8 QuadPixelEn; /**< Quad pixel support by this core
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instance. */
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u8 DualPixelEn; /**< Dual pixel support by this core's
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u8 DualPixelEn; /**< Dual pixel support by this core
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instance. */
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u8 YOnlyEn; /**< YOnly format support by this core's
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u8 YCrCbEn; /**< YCrCb format support by this core
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instance. */
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u8 YCrCbEn; /**< YCrCb format support by this core's
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u8 YOnlyEn; /**< YOnly format support by this core
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instance. */
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u8 PayloadDataWidth; /**< The payload data width used by this core
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instance. */
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u8 SecondaryChEn; /**< This core instance supports audio packets
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being sent by the secondary channel. */
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u8 NumAudioChs; /**< The number of audio channels supported by
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this core instance. */
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u8 MstSupport; /**< Multi-stream transport (MST) mode is
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enabled by this core instance. */
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u8 NumMstStreams; /**< The total number of MST streams supported
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by this core instance. */
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u8 DpProtocol; /**< The DisplayPort protocol version that this
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core instance is configured for.
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0 = v1.1a, 1 = v1.2. */
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} XDptx_Config;
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/**
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