gpiops_v3_1 : Convert 3-line comments to 1-liners.
Driverwide, scripted change to convert 3-line comments to single line comments. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This commit is contained in:
parent
3357570898
commit
2ffa12ed7c
7 changed files with 58 additions and 174 deletions
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@ -72,15 +72,11 @@
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#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
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#define GPIO_INTERRUPT_ID XPAR_XGPIOPS_0_INTR
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/*
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* The following constants define the GPIO banks that are used.
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*/
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/* The following constants define the GPIO banks that are used. */
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#define INPUT_BANK XGPIOPS_BANK0 /* Bank 0 of the GPIO Device */
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#define OUTPUT_BANK XGPIOPS_BANK1 /* Bank 1 of the GPIO Device */
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/*
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* The following constants define the positions of the buttons of the GPIO.
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*/
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/* The following constants define the positions of the buttons of the GPIO. */
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#define GPIO_ALL_BUTTONS 0xFFFF
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/*
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@ -174,18 +170,14 @@ int GpioIntrExample(XScuGic *Intc, XGpioPs *Gpio, u16 DeviceId, u16 GpioIntrId)
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XGpioPs_Config *ConfigPtr;
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int Status;
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/*
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* Initialize the Gpio driver.
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*/
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/* Initialize the Gpio driver. */
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ConfigPtr = XGpioPs_LookupConfig(DeviceId);
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if (ConfigPtr == NULL) {
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return XST_FAILURE;
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}
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XGpioPs_CfgInitialize(Gpio, ConfigPtr, ConfigPtr->BaseAddr);
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/*
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* Run a self-test on the GPIO device.
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*/
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/* Run a self-test on the GPIO device. */
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Status = XGpioPs_SelfTest(Gpio);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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@ -247,24 +239,18 @@ static void IntrHandler(void *CallBackRef, u32 Bank, u32 Status)
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XGpioPs *Gpio = (XGpioPs *)CallBackRef;
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static u32 ButtonsChanged;
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/*
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* Do nothing if the intr is generated for a different bank.
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*/
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/* Do nothing if the intr is generated for a different bank. */
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if (Bank != INPUT_BANK) {
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return;
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}
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ButtonsChanged |= Status;
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/*
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* Set the LEDs.
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*/
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/* Set the LEDs. */
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XGpioPs_Write(Gpio, OUTPUT_BANK, ButtonsChanged);
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if (ButtonsChanged == GPIO_EXIT_CONTROL_VALUE) {
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/*
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* Five buttons are pressed to mark the completion of the test.
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*/
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/* Five buttons are pressed to mark the completion of the test. */
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AllButtonsPressed = TRUE;
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ButtonsChanged = 0;
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}
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@ -335,32 +321,22 @@ static int SetupInterruptSystem(XScuGic *GicInstancePtr, XGpioPs *Gpio,
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return Status;
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}
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/*
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* Enable falling edge interrupts for all the pins in bank 0.
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*/
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/* Enable falling edge interrupts for all the pins in bank 0. */
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XGpioPs_SetIntrType(Gpio, INPUT_BANK, 0x00, 0x00, 0x00);
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/*
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* Set the handler for gpio interrupts.
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*/
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/* Set the handler for gpio interrupts. */
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XGpioPs_SetCallbackHandler(Gpio, (void *)Gpio, IntrHandler);
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/*
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* Enable the GPIO interrupts of Bank 0.
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*/
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/* Enable the GPIO interrupts of Bank 0. */
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XGpioPs_IntrEnable(Gpio, INPUT_BANK, 0xFFFFFFFF);
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/*
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* Enable the interrupt for the GPIO device.
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*/
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/* Enable the interrupt for the GPIO device. */
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XScuGic_Enable(GicInstancePtr, GpioIntrId);
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/*
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* Enable interrupts in the Processor.
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*/
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/* Enable interrupts in the Processor. */
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Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
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return XST_SUCCESS;
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@ -91,9 +91,7 @@
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*/
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#define LED_DELAY 10000000
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/*
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* Following constant define the Input and Output pins.
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*/
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/* Following constant define the Input and Output pins. */
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#define OUTPUT_PIN 10 /* Pin connected to LED/Output */
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#define INPUT_PIN 14 /* Pin connected to Switch/Input */
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@ -173,9 +171,7 @@ int GpioPolledExample(u16 DeviceId, u32 *DataRead)
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int Status;
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XGpioPs_Config *ConfigPtr;
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/*
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* Initialize the GPIO driver.
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*/
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/* Initialize the GPIO driver. */
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ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
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Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr,
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ConfigPtr->BaseAddr);
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@ -183,17 +179,13 @@ int GpioPolledExample(u16 DeviceId, u32 *DataRead)
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return XST_FAILURE;
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}
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/*
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* Run the Output Example.
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*/
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/* Run the Output Example. */
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Status = GpioOutputExample();
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/*
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* Run the Input Example.
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*/
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/* Run the Input Example. */
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Status = GpioInputExample(DataRead);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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@ -228,9 +220,7 @@ static int GpioOutputExample(void)
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XGpioPs_SetDirectionPin(&Gpio, OUTPUT_PIN, 1);
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XGpioPs_SetOutputEnablePin(&Gpio, OUTPUT_PIN, 1);
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/*
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* Set the GPIO output to be low.
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*/
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/* Set the GPIO output to be low. */
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XGpioPs_WritePin(&Gpio, OUTPUT_PIN, 0x0);
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@ -238,15 +228,11 @@ static int GpioOutputExample(void)
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#ifndef __SIM__
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/*
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* Wait a small amount of time so the LED is visible.
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*/
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/* Wait a small amount of time so the LED is visible. */
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for (Delay = 0; Delay < LED_DELAY; Delay++);
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#endif
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/*
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* Set the GPIO Output to High.
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*/
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/* Set the GPIO Output to High. */
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XGpioPs_WritePin(&Gpio, OUTPUT_PIN, 0x1);
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/*
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@ -260,16 +246,12 @@ static int GpioOutputExample(void)
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}
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#ifndef __SIM__
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/*
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* Wait a small amount of time so the LED is visible.
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*/
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/* Wait a small amount of time so the LED is visible. */
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for (Delay = 0; Delay < LED_DELAY; Delay++);
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#endif
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/*
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* Clear the GPIO Output.
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*/
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/* Clear the GPIO Output. */
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XGpioPs_WritePin(&Gpio, OUTPUT_PIN, 0x0);
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/*
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@ -303,14 +285,10 @@ static int GpioOutputExample(void)
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static int GpioInputExample(u32 *DataRead)
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{
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/*
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* Set the direction for the specified pin to be input.
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*/
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/* Set the direction for the specified pin to be input. */
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XGpioPs_SetDirectionPin(&Gpio, INPUT_PIN, 0x0);
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/*
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* Read the state of the data so that it can be verified.
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*/
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/* Read the state of the data so that it can be verified. */
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*DataRead = XGpioPs_ReadPin(&Gpio, INPUT_PIN);
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return XST_SUCCESS;
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@ -145,9 +145,7 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
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XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
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}
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/*
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* Indicate the component is now ready to use.
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*/
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/* Indicate the component is now ready to use. */
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InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
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return Status;
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@ -204,9 +202,7 @@ u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
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/*
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* Get the Bank number and Pin number within the bank.
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*/
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/* Get the Bank number and Pin number within the bank. */
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XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
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return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
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@ -271,15 +267,11 @@ void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
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/*
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* Get the Bank number and Pin number within the bank.
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*/
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/* Get the Bank number and Pin number within the bank. */
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XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
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if (PinNumber > 15U) {
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/*
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* There are only 16 data bits in bit maskable register.
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*/
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/* There are only 16 data bits in bit maskable register. */
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PinNumber -= (u8)16;
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RegOffset = XGPIOPS_DATA_MSW_OFFSET;
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} else {
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@ -354,9 +346,7 @@ void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
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Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
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Xil_AssertVoid(Direction <= (u32)1);
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/*
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* Get the Bank number and Pin number within the bank.
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*/
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/* Get the Bank number and Pin number within the bank. */
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XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
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DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
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@ -426,9 +416,7 @@ u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
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/*
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* Get the Bank number and Pin number within the bank.
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*/
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/* Get the Bank number and Pin number within the bank. */
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XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
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return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
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@ -495,9 +483,7 @@ void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
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Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
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Xil_AssertVoid(OpEnable <= (u32)1);
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/*
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* Get the Bank number and Pin number within the bank.
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*/
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/* Get the Bank number and Pin number within the bank. */
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XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
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OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
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@ -567,9 +553,7 @@ u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
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/*
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* Get the Bank number and Pin number within the bank.
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*/
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/* Get the Bank number and Pin number within the bank. */
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XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
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return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
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@ -205,15 +205,11 @@ typedef struct {
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/************************** Function Prototypes ******************************/
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/*
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* Functions in xgpiops.c
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*/
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/* Functions in xgpiops.c */
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s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
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u32 EffectiveAddr);
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/*
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* Bank APIs in xgpiops.c
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*/
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/* Bank APIs in xgpiops.c */
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u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
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void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
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void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
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@ -222,9 +218,7 @@ void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
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u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
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void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
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/*
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* Pin APIs in xgpiops.c
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*/
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/* Pin APIs in xgpiops.c */
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u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
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void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
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void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
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@ -232,17 +226,11 @@ u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
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void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
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u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
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/*
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* Diagnostic functions in xgpiops_selftest.c
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*/
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/* Diagnostic functions in xgpiops_selftest.c */
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s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
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/*
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* Functions in xgpiops_intr.c
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*/
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/*
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* Bank APIs in xgpiops_intr.c
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*/
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/* Functions in xgpiops_intr.c */
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/* Bank APIs in xgpiops_intr.c */
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void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
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void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
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u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
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@ -256,9 +244,7 @@ void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
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XGpioPs_Handler FuncPointer);
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void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
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/*
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* Pin APIs in xgpiops_intr.c
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*/
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/* Pin APIs in xgpiops_intr.c */
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void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
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u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
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@ -268,9 +254,7 @@ u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
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u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
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void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
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/*
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* Functions in xgpiops_sinit.c
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*/
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/* Functions in xgpiops_sinit.c */
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XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
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#ifdef __cplusplus
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@ -89,9 +89,7 @@ void XGpioPs_ResetHw(u32 BaseAddress)
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} else {
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MaxBanks = (u32)4;
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}
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/*
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* Write reset values to all mask data registers
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*/
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/* Write reset values to all mask data registers */
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for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
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XGpioPs_WriteReg(BaseAddress,
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@ -101,9 +99,7 @@ void XGpioPs_ResetHw(u32 BaseAddress)
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((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
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XGPIOPS_DATA_MSW_OFFSET), 0x0U);
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}
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/*
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* Write reset values to all output data registers
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*/
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/* Write reset values to all output data registers */
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for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
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XGpioPs_WriteReg(BaseAddress,
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@ -111,9 +107,7 @@ void XGpioPs_ResetHw(u32 BaseAddress)
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XGPIOPS_DATA_OFFSET), 0x0U);
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}
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/*
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* Reset all registers of all GPIO banks
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*/
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/* Reset all registers of all GPIO banks */
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for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
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XGpioPs_WriteReg(BaseAddress,
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@ -142,40 +136,28 @@ void XGpioPs_ResetHw(u32 BaseAddress)
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XGPIOPS_INTANY_OFFSET), 0x0U);
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}
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/*
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* Bank 0 Int type
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*/
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/* Bank 0 Int type */
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XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
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XGPIOPS_INTTYPE_BANK0_RESET);
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/*
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* Bank 1 Int type
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*/
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/* Bank 1 Int type */
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XGpioPs_WriteReg(BaseAddress,
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((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
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XGPIOPS_INTTYPE_BANK1_RESET);
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/*
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* Bank 2 Int type
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*/
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/* Bank 2 Int type */
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XGpioPs_WriteReg(BaseAddress,
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(((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
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XGPIOPS_INTTYPE_BANK2_RESET);
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/*
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* Bank 3 Int type
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*/
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/* Bank 3 Int type */
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XGpioPs_WriteReg(BaseAddress,
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(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
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XGPIOPS_INTTYPE_BANK3_RESET);
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if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
|
||||
/*
|
||||
* Bank 4 Int type
|
||||
*/
|
||||
/* Bank 4 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
(((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK4_RESET);
|
||||
/*
|
||||
* Bank 5 Int type
|
||||
*/
|
||||
/* Bank 5 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
(((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK5_RESET);
|
||||
|
|
|
@ -119,9 +119,7 @@ void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
|
|||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
|
||||
|
||||
/*
|
||||
* Get the Bank number and Pin number within the bank.
|
||||
*/
|
||||
/* Get the Bank number and Pin number within the bank. */
|
||||
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
|
||||
|
||||
IntrReg = ((u32)1 << (u32)PinNumber);
|
||||
|
@ -183,9 +181,7 @@ void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
|
|||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
|
||||
|
||||
/*
|
||||
* Get the Bank number and Pin number within the bank.
|
||||
*/
|
||||
/* Get the Bank number and Pin number within the bank. */
|
||||
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
|
||||
|
||||
IntrReg = ((u32)1 << (u32)PinNumber);
|
||||
|
@ -252,9 +248,7 @@ u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
|
|||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
|
||||
|
||||
/*
|
||||
* Get the Bank number and Pin number within the bank.
|
||||
*/
|
||||
/* Get the Bank number and Pin number within the bank. */
|
||||
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
|
||||
|
||||
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
|
||||
|
@ -316,9 +310,7 @@ u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
|
|||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
|
||||
|
||||
/*
|
||||
* Get the Bank number and Pin number within the bank.
|
||||
*/
|
||||
/* Get the Bank number and Pin number within the bank. */
|
||||
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
|
||||
|
||||
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
|
||||
|
@ -351,9 +343,7 @@ void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
|
|||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
|
||||
|
||||
/*
|
||||
* Clear the currently pending interrupts.
|
||||
*/
|
||||
/* Clear the currently pending interrupts. */
|
||||
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
|
||||
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTSTS_OFFSET, Mask);
|
||||
|
@ -382,14 +372,10 @@ void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
|
|||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
|
||||
|
||||
/*
|
||||
* Get the Bank number and Pin number within the bank.
|
||||
*/
|
||||
/* Get the Bank number and Pin number within the bank. */
|
||||
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
|
||||
|
||||
/*
|
||||
* Clear the specified pending interrupts.
|
||||
*/
|
||||
/* Clear the specified pending interrupts. */
|
||||
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
|
||||
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTSTS_OFFSET);
|
||||
|
@ -522,9 +508,7 @@ void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
|
|||
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
|
||||
Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
/*
|
||||
* Get the Bank number and Pin number within the bank.
|
||||
*/
|
||||
/* Get the Bank number and Pin number within the bank. */
|
||||
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
|
||||
|
||||
IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
|
||||
|
@ -608,9 +592,7 @@ u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
|
|||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
|
||||
|
||||
/*
|
||||
* Get the Bank number and Pin number within the bank.
|
||||
*/
|
||||
/* Get the Bank number and Pin number within the bank. */
|
||||
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
|
||||
|
||||
IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
|
||||
|
|
|
@ -94,9 +94,7 @@ s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
|
|||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Disable the Interrupts for Bank 0 .
|
||||
*/
|
||||
/* Disable the Interrupts for Bank 0 . */
|
||||
IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
|
||||
XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
|
||||
|
||||
|
|
Loading…
Add table
Reference in a new issue