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emacps: Create new version v3_0 and deprectaed older one

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Create new version v3_0 and deprectaed older one.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This commit is contained in:
Punnaiah Choudary Kalluri 2014-12-09 20:22:20 +05:30 • committed by Suneel Garapati
parent 9a04f2c373
commit 35e0aac333
25 changed files with 12512 additions and 0 deletions
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2
XilinxProcessorIPLib/drivers/emacps/data/dependencies.props Normal file
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xemacps_example_intr_dma.c=xemacps_example_util.c,xemacps_example.h
xemacps_ieee1588_example.c=xemacps_example_util.c,xemacps_example.h,xemacps_ieee1588.c,xemacps_ieee1588.h

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XilinxProcessorIPLib/drivers/emacps/data/emacps.mdd Executable file
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###############################################################################
#
# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
OPTION psf_version = 2.1;
BEGIN driver emacps
OPTION supported_peripherals = (ps7_ethernet);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 3.0;
OPTION NAME = emacps;
END driver

219
XilinxProcessorIPLib/drivers/emacps/data/emacps.tcl Executable file
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###############################################################################
#
# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
##############################################################################
#
# Modification History
#
# Ver Who Date Changes
# ----- ---- -------- -----------------------------------------------
# 1.00a sdm 11/22/11 Created
# 2.0 adk 10/12/13 Updated as per the New Tcl API's
# 2.1 adk 11/08/14 Fixed the CR#811288 when PCS/PMA core is present in the hw
# XPAR_GIGE_PCS_PMA_CORE_PRESENT and phy address values
# should export to the xparameters.h file.
# 2.1 bss 09/08/14 Fixed CR#820349 to export phy address in xparameters.h
# when GMII to RGMII converter is present in hw.
# 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
# 1000BASE-X mode export proper values to the xparameters.h
# file.
#
##############################################################################
#uses "xillib.tcl"
proc generate {drv_handle} {
xdefine_zynq_include_file $drv_handle "xparameters.h" "XEmacPs" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_ENET_CLK_FREQ_HZ" "C_ENET_SLCR_1000Mbps_DIV0" "C_ENET_SLCR_1000Mbps_DIV1" "C_ENET_SLCR_100Mbps_DIV0" "C_ENET_SLCR_100Mbps_DIV1" "C_ENET_SLCR_10Mbps_DIV0" "C_ENET_SLCR_10Mbps_DIV1"
xdefine_zynq_config_file $drv_handle "xemacps_g.c" "XEmacPs" "DEVICE_ID" "C_S_AXI_BASEADDR"
xdefine_zynq_canonical_xpars $drv_handle "xparameters.h" "XEmacPs" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_ENET_CLK_FREQ_HZ" "C_ENET_SLCR_1000Mbps_DIV0" "C_ENET_SLCR_1000Mbps_DIV1" "C_ENET_SLCR_100Mbps_DIV0" "C_ENET_SLCR_100Mbps_DIV1" "C_ENET_SLCR_10Mbps_DIV0" "C_ENET_SLCR_10Mbps_DIV1"
generate_gmii2rgmii_params $drv_handle "xparameters.h"
generate_sgmii_params $drv_handle "xparameters.h"
}
proc generate_gmii2rgmii_params {drv_handle file_name} {
set file_handle [::hsm::utils::open_include_file $file_name]
set ips [get_cells "*"]
foreach ip $ips {
set ipname [get_property NAME $ip]
set periph [get_property IP_NAME $ip]
if { [string compare -nocase $periph "ps7_ethernet"] == 0} {
set phya [is_gmii2rgmii_conv_present $ip]
if { $phya == 0} {
close $file_handle
return 0
}
puts $file_handle "/* Definition for the MDIO address for the GMII2RGMII converter PL IP*/"
if { [string compare -nocase $ipname "ps7_ethernet_0"] == 0} {
puts $file_handle "\#define XPAR_GMII2RGMIICON_0N_ETH0_ADDR $phya"
}
if { [string compare -nocase $ipname "ps7_ethernet_1"] == 0} {
puts $file_handle "\#define XPAR_GMII2RGMIICON_0N_ETH1_ADDR $phya"
}
puts $file_handle "\n/******************************************************************/\n"
}
}
close $file_handle
}
proc is_gmii2rgmii_conv_present {slave} {
set port_value 0
set phy_addr 0
set ipconv 0
set ips [get_cells "*"]
set enetipinstance_name [get_property NAME $slave]
foreach ip $ips {
set convipname [get_property NAME $ip]
set periph [get_property IP_NAME $ip]
if { [string compare -nocase $periph "gmii_to_rgmii"] == 0} {
set ipconv $ip
break
}
}
if { $ipconv != 0 } {
set port_value [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $ipconv gmii_txd]]]
if { $port_value != 0 } {
set tmp [string first "ENET0" $port_value]
if { $tmp >= 0 } {
if { [string compare -nocase $enetipinstance_name "ps7_ethernet_0"] == 0} {
set phyaddr [::hsm::utils::get_param_value $ipconv C_PHYADDR]
set phy_addr [::hsm::utils::convert_binary_to_decimal $phyaddr]
if {[llength $phy_addr] == 0} {
set phy_addr 0
}
}
} else {
set tmp0 [string first "ENET1" $port_value]
if { $tmp0 >= 0 } {
if { [string compare -nocase $enetipinstance_name "ps7_ethernet_1"] == 0} {
set phyaddr [::hsm::utils::get_param_value $ipconv C_PHYADDR]
set phy_addr [::hsm::utils::convert_binary_to_decimal $phyaddr]
if {[llength $phy_addr] == 0} {
set phy_addr 0
}
}
}
}
}
}
return $phy_addr
}
proc generate_sgmii_params {drv_handle file_name} {
set file_handle [::hsm::utils::open_include_file $file_name]
set ips [get_cells "*"]
foreach ip $ips {
set ipname [get_property NAME $ip]
set periph [get_property IP_NAME $ip]
if { [string compare -nocase $periph "gig_ethernet_pcs_pma"] == 0} {
set PhyStandard [get_property CONFIG.Standard $ip]
}
if { [string compare -nocase $ipname "ps7_ethernet_0"] == 0} {
set phya [is_gige_pcs_pma_ip_present $ip]
if { $phya == 0} {
close $file_handle
return 0
}
if { $PhyStandard == "1000BASEX" } {
puts $file_handle "/* Definitions related to PCS PMA PL IP*/"
puts $file_handle "\#define XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT 1"
puts $file_handle "\#define XPAR_PCSPMA_1000BASEX_PHYADDR $phya"
puts $file_handle "\n/******************************************************************/\n"
} else {
puts $file_handle "/* Definitions related to PCS PMA PL IP*/"
puts $file_handle "\#define XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT 1"
puts $file_handle "\#define XPAR_PCSPMA_SGMII_PHYADDR $phya"
puts $file_handle "\n/******************************************************************/\n"
}
}
}
close $file_handle
}
proc is_gige_pcs_pma_ip_present {slave} {
set port_value 0
set phy_addr 0
set ipconv 0
set ips [get_cells "*"]
set enetipinstance_name [get_property IP_NAME $slave]
foreach ip $ips {
set convipname [get_property NAME $ip]
set periph [get_property IP_NAME $ip]
if { [string compare -nocase $periph "gig_ethernet_pcs_pma"] == 0} {
set sgmii_param [get_property CONFIG.c_is_sgmii $ip]
set PhyStandarrd [get_property CONFIG.Standard $ip]
if {$sgmii_param == true || $PhyStandarrd == "1000BASEX"} {
set ipconv $ip
}
break
}
}
if { $ipconv != 0 } {
set port_value [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $ipconv gmii_txd]]]
if { $port_value != 0 } {
set tmp [string first "ENET0" $port_value]
if { $tmp >= 0 } {
if { [string compare -nocase $enetipinstance_name "ps7_ethernet"] == 0} {
set phyaddr [::hsm::utils::get_param_value $ipconv C_PHYADDR]
set phy_addr [::hsm::utils::convert_binary_to_decimal $phyaddr]
if {[llength $phy_addr] == 0} {
set phy_addr 0
}
}
} else {
set tmp0 [string first "ENET1" $port_value]
if { $tmp0 >= 0 } {
if { [string compare -nocase $enetipinstance_name "ps7_ethernet"] == 0} {
set phyaddr [::hsm::utils::get_param_value $ipconv C_PHYADDR]
set phy_addr [::hsm::utils::convert_binary_to_decimal $phyaddr]
puts [format "phy_addr %s phyaddr %s" $phy_addr $phyaddr]
if {[llength $phy_addr] == 0} {
set phy_addr 0
}
}
}
}
}
}
return $phy_addr
}

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XilinxProcessorIPLib/drivers/emacps/data/emacps_header.h Executable file
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/* $Id: tmrctr_header.h,v 1.1.2.1 2010/12/01 07:53:56 svemula Exp $ */
/******************************************************************************
*
* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef EMACPS_HEADER_H /* prevent circular inclusions */
#define EMACPS_HEADER_H /* by using protection macros */
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
int EmacPsDmaIntrExample(XScuGic *IntcInstancePtr,
XEmacPs *EmacPsInstancePtr,
u16 EmacPsDeviceId, u16 EmacPsIntrId);
#endif

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XilinxProcessorIPLib/drivers/emacps/data/emacps_tapp.tcl Executable file
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###############################################################################
#
# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
##############################################################################
#
# Modification History
#
# Ver Who Date Changes
# ----- ---- -------- -----------------------------------------------
# 2.0 adk 10/12/13 Updated as per the New Tcl API's
##############################################################################
# Uses $XILINX_EDK/bin/lib/xillib_sw.tcl
# -----------------------------------------------------------------
# Software Project Types (swproj):
# 0 : MemoryTest - Calls basic memorytest routines from common driver dir
# 1 : PeripheralTest - Calls any existing polled_example and/or selftest
# -----------------------------------------------------------------
# -----------------------------------------------------------------
# TCL Procedures:
# -----------------------------------------------------------------
proc gen_include_files {swproj mhsinst} {
if {$swproj == 0} {
return ""
}
if {$swproj == 1} {
set inc_file_lines {xemacps.h xemacps_example.h emacps_header.h}
}
return $inc_file_lines
}
proc gen_src_files {swproj mhsinst} {
if {$swproj == 0} {
return ""
}
if {$swproj == 1} {
set inc_file_lines {examples/xemacps_example_intr_dma.c examples/xemacps_example_util.c examples/xemacps_example.h data/emacps_header.h}
return $inc_file_lines
}
}
proc gen_testfunc_def {swproj mhsinst} {
return ""
}
proc gen_init_code {swproj mhsinst} {
if {$swproj == 0} {
return ""
}
if {$swproj == 1} {
set ipname [get_property NAME $mhsinst]
set decl " static XEmacPs ${ipname};"
set inc_file_lines $decl
return $inc_file_lines
}
}
proc gen_testfunc_call {swproj mhsinst} {
if {$swproj == 0} {
return ""
}
set ipname [get_property NAME $mhsinst]
set deviceid [::hsm::utils::get_ip_param_name $mhsinst "DEVICE_ID"]
set stdout [get_property CONFIG.STDOUT [get_os]]
if { $stdout == "" || $stdout == "none" } {
set hasStdout 0
} else {
set hasStdout 1
}
set isintr [::hsm::utils::is_ip_interrupting_current_proc $mhsinst]
set intcvar intc
set testfunc_call ""
if {${hasStdout} == 0} {
if {$isintr == 1} {
set intr_id "XPAR_${ipname}_INTR"
set intr_id [string toupper $intr_id]
append testfunc_call "
{
int Status;
Status = EmacPsDmaIntrExample(&${intcvar}, &${ipname}, \\
${deviceid}, \\
${intr_id});
}"
}
} else {
if {$isintr == 1} {
set intr_id "XPAR_${ipname}_INTR"
set intr_id [string toupper $intr_id]
append testfunc_call "
{
int Status;
print(\"\\r\\n Running Interrupt Test for ${ipname}...\\r\\n\");
Status = EmacPsDmaIntrExample(&${intcvar}, &${ipname}, \\
${deviceid}, \\
${intr_id});
if (Status == 0) {
print(\"EmacPsDmaIntrExample PASSED\\r\\n\");
}
else {
print(\"EmacPsDmaIntrExample FAILED\\r\\n\");
}
}"
}
}
return $testfunc_call
}

20
XilinxProcessorIPLib/drivers/emacps/examples/index.html Executable file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
<html>
<head>
<meta http-equiv="Content-Language" content="en-us">
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
<title>Driver example applications</title>
<link rel="stylesheet" type="text/css" href="../help.css">
</head>
<body bgcolor="#FFFFFF">
<h1> Example Applications for the driver emacps_v2_1 </h1>
<HR>
<ul>
<li>xemacps_example_intr_dma.c <a href="xemacps_example_intr_dma.c">(source)</a> </li>
<li>xemacps_example_util.c <a href="xemacps_example_util.c">(source)</a> </li>
<li>xemacps_ieee1588.c <a href="xemacps_ieee1588.c">(source)</a> </li>
<li>xemacps_ieee1588_example.c <a href="xemacps_ieee1588_example.c">(source)</a> </li>
</ul>
<p><font face="Times New Roman" color="#800000">Copyright <20> 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
</body>
</html>

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XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example.h Executable file
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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xemacps_example.h
*
* Defines common data types, prototypes, and includes the proper headers
* for use with the EMACPS example code residing in this directory.
*
* This file along with xemacps_example_util.c are utilized with the specific
* example code in the other source code files provided.
* These examples are designed to be compiled and utilized within the SDK
* standalone BSP development environment.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.01a asa 02/27/12 Hash define added for EMACPS_SLCR_DIV_MASK.
* 1.05a asa 09/22/13 The EthernetFrame is made cache line aligned (32 bytes).
* Fix for CR #663885.
* </pre>
*
*****************************************************************************/
#ifndef XEMACPS_EXAMPLE_H
#define XEMACPS_EXAMPLE_H
/***************************** Include Files ********************************/
#include <stdio.h>
#include <stdlib.h>
#include "sleep.h"
#include "xparameters.h"
#include "xparameters_ps.h" /* defines XPAR values */
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "xil_exception.h"
#include "xpseudo_asm.h"
#include "xil_cache.h"
#include "xil_printf.h"
#include "xscugic.h"
#include "xemacps.h" /* defines XEmacPs API */
/************************** Constant Definitions ****************************/
#define EMACPS_LOOPBACK_SPEED 100 /* 100Mbps */
#define EMACPS_LOOPBACK_SPEED_1G 1000 /* 1000Mbps */
#define EMACPS_PHY_DELAY_SEC 4 /* Amount of time to delay waiting on
PHY to reset */
#define EMACPS_SLCR_DIV_MASK 0xFC0FC0FF
/***************** Macros (Inline Functions) Definitions ********************/
/**************************** Type Definitions ******************************/
/*
* Define an aligned data type for an ethernet frame. This declaration is
* specific to the GNU compiler
*/
typedef char EthernetFrame[XEMACPS_MAX_VLAN_FRAME_SIZE]
__attribute__ ((aligned(32)));
/************************** Function Prototypes *****************************/
/*
* Utility functions implemented in xemacps_example_util.c
*/
void EmacPsUtilSetupUart(void);
void EmacPsUtilFrameHdrFormatMAC(EthernetFrame * FramePtr, char *DestAddr);
void EmacPsUtilFrameHdrFormatType(EthernetFrame * FramePtr, u16 FrameType);
void EmacPsUtilFrameSetPayloadData(EthernetFrame * FramePtr, int PayloadSize);
int EmacPsUtilFrameVerify(EthernetFrame * CheckFrame,
EthernetFrame * ActualFrame);
void EmacPsUtilFrameMemClear(EthernetFrame * FramePtr);
int EmacPsUtilEnterLoopback(XEmacPs * XEmacPsInstancePtr, int Speed);
void EmacPsUtilstrncpy(char *Destination, const char *Source, u32 n);
void EmacPsUtilErrorTrap(const char *Message);
/************************** Variable Definitions ****************************/
extern XEmacPs EmacPsInstance; /* Device instance used throughout examples */
extern char EmacPsMAC[]; /* Local MAC address */
#endif /* XEMACPS_EXAMPLE_H */

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XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_intr_dma.c Executable file
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XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_readme.txt Executable file
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xemacps_ieee1588_example_readme.txt
-----------------------------------
The examples in this directory are provided to give the user some idea of the
following:
- How the EmacPs and its driver are intended to be used.
- How the protocol packets flow and processed for IEEE1588 (PTP).
FILES
Three files are provided to demonstrate the usage of EmacPs and the
driver. They are:
- xemacps_example.h - Top level include for the example.
- xemacps_example_util.c - Provide various utilities for debugging, and
ethernet frame construction.
- xemacps_example_intr_dma.c - Implements the example that uses EmacPs internal
DMA to send and receive packets in loopback mode. It uses interrupts.
The user must include the above three files for building the binary to see how
Ethernet packets are sent and received in PHY loopback mode..
Three files are provided for demonstrating the IEEE1588 protocol. They are:
- xemacps_ieee1588_example.c: The top level C file that has the programe
entry "main". It also has initialization code for EmacPs, Timer etc.
It has initialization code for PTP packets.
- xemacps_ieee1588.h: Include file that contains all function prototypes,
hash defines etc.
- xemacps_ieee1588.c: The protocol packets are processed in this file.
The user must include the above three files for building the binary to see
how IEEE1588 (PTP) works.
SYSTEM REQUIREMENTS
The system containing the EmacPs should have the following capabilities:
- An interrupt controller
- A UART to display messages
- A Timer that is used to send protocol packets at regular intervals
For testing the example in xemacps_example_intr_dma.c which uses PHY loopback,
a single hardware system is sufficient.
To run and test the binary created for IEEE1588 (PTP), the user
needs to have two EmacPs based hardware systems connected back-to-back.
One would act as a Master and other as a slave.
HOW THE IEEE1588 EXAMPLE WORKS
- The example should be run between two boards, both having capability to
time stamp the PTP packets. For example, it can be run between two Zynq
boards, two PEEP boards, one Zynq and one PEEP board etc. Additionally
this example is also tested between a Zynq/PEEP board and a ML605 board.
However, on ML605 board we need to run a slightly modified AVB example
(for AxiEthernet) available in Perforce for AxiEthernet driver.
- To run the example on a PEEP board, please define the flag PEEP in
xemacps_ieee1588.h (or with -DPEEP compile time option).
- The example can be run in PTP MASTER mode or PTP SLAVE mode. To run it in
PTP MASTER mode please define the flag IEEE1588_MASTER
(with -DIEEE1588_MASTER) in the compiler options or just define it in
xemacps_ieee1588.h. If this flag is defined then the software runs in
MASTER mode or else in SLAVE mode.
- The example by default initializes the PHY and GEM for 100 Mbps speed.
Additionally autonegotiation can be used. To use autonegotiation, please
define the flag PHY_AUTONEGOTIATION. However this feature is applicable
only for Zynq boards.
- ScuTimer is used to generate interrupts every 500 mseconds. This timer
interrupt is used to send various protocol packets. For example, Sync/
FollowUp packets are sent every 1 seconds. Announce frames are sent every
5 seconds and PDelay packets are sent every 4 seconds.
- In a typical test setup, 2 Zynq boards are connected back to back. Please
build the SDK projects (with the above 3 files) in MASTER mode and download
the elf to one Zynq board. Then build the SDK project in SLAVE mode and
download and run it in the other board. You can start seeing the console
messages.
- There are two debug levels. By default debug level 1 is defined to see
some of the important PTP messages. For example, the link delay and the
time correction values. The other debug level can be defined to see the
messages from ISR. It can be handy to debug issues if any. To define the
1st debug level, define the flag DEBUG_XEMACPS_LEVEL1 in
xemacps_ieee1588.h. To define the other debug level, define the flag
DEBUG_LEVEL_TWO.
- Signalling frames are not implemented. So at runtime, we cannot change
mode between MASTER and SLAVE. Clock adjustment is implemented, but
clock rate adjustment is not implemented.

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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xemacps_example_util.c
*
* This file implements the utility functions for the XEmacPs example code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.00a asa 01/24/12 A new version of EmacPsUtilEnterLoopback is used for
* Zynq boards. Now there are two versions of
* EmacPsUtilEnterLoopback, one for PEEP and one for Zynq.
* If the example is to be run on a PEEP board, define PEEP
* in xemacps_example.h.
* 1.01a asa 02/27/12 The sleep value after PHY loopback is setup is reduced
* for Zynq.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xemacps_example.h"
#include "sleep.h"
/************************** Variable Definitions ****************************/
XEmacPs EmacPsInstance; /* XEmacPs instance used throughout examples */
/*
* Local MAC address
*/
char EmacPsMAC[] = { 0x00, 0x0a, 0x35, 0x01, 0x02, 0x03 };
/****************************************************************************/
/**
*
* Set the MAC addresses in the frame.
*
* @param FramePtr is the pointer to the frame.
* @param DestAddr is the Destination MAC address.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void EmacPsUtilFrameHdrFormatMAC(EthernetFrame * FramePtr, char *DestAddr)
{
char *Frame = (char *) FramePtr;
char *SourceAddress = EmacPsMAC;
int Index;
/* Destination address */
for (Index = 0; Index < XEMACPS_MAC_ADDR_SIZE; Index++) {
*Frame++ = *DestAddr++;
}
/* Source address */
for (Index = 0; Index < XEMACPS_MAC_ADDR_SIZE; Index++) {
*Frame++ = *SourceAddress++;
}
}
/****************************************************************************/
/**
*
* Set the frame type for the specified frame.
*
* @param FramePtr is the pointer to the frame.
* @param FrameType is the Type to set in frame.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void EmacPsUtilFrameHdrFormatType(EthernetFrame * FramePtr, u16 FrameType)
{
char *Frame = (char *) FramePtr;
/*
* Increment to type field
*/
Frame = Frame + 12;
/*
* Do endian swap from little to big-endian.
*/
FrameType = Xil_EndianSwap16(FrameType);
/*
* Set the type
*/
*(u16 *) Frame = FrameType;
}
/****************************************************************************/
/**
* This function places a pattern in the payload section of a frame. The pattern
* is a 8 bit incrementing series of numbers starting with 0.
* Once the pattern reaches 256, then the pattern changes to a 16 bit
* incrementing pattern:
* <pre>
* 0, 1, 2, ... 254, 255, 00, 00, 00, 01, 00, 02, ...
* </pre>
*
* @param FramePtr is a pointer to the frame to change.
* @param PayloadSize is the number of bytes in the payload that will be set.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void EmacPsUtilFrameSetPayloadData(EthernetFrame * FramePtr, int PayloadSize)
{
unsigned BytesLeft = PayloadSize;
u8 *Frame;
u16 Counter = 0;
/*
* Set the frame pointer to the start of the payload area
*/
Frame = (u8 *) FramePtr + XEMACPS_HDR_SIZE;
/*
* Insert 8 bit incrementing pattern
*/
while (BytesLeft && (Counter < 256)) {
*Frame++ = (u8) Counter++;
BytesLeft--;
}
/*
* Switch to 16 bit incrementing pattern
*/
while (BytesLeft) {
*Frame++ = (u8) (Counter >> 8); /* high */
BytesLeft--;
if (!BytesLeft)
break;
*Frame++ = (u8) Counter++; /* low */
BytesLeft--;
}
}
/****************************************************************************/
/**
* This function verifies the frame data against a CheckFrame.
*
* Validation occurs by comparing the ActualFrame to the header of the
* CheckFrame. If the headers match, then the payload of ActualFrame is
* verified for the same pattern Util_FrameSetPayloadData() generates.
*
* @param CheckFrame is a pointer to a frame containing the 14 byte header
* that should be present in the ActualFrame parameter.
* @param ActualFrame is a pointer to a frame to validate.
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*****************************************************************************/
int EmacPsUtilFrameVerify(EthernetFrame * CheckFrame,
EthernetFrame * ActualFrame)
{
char *CheckPtr = (char *) CheckFrame;
char *ActualPtr = (char *) ActualFrame;
u16 BytesLeft;
u16 Counter;
int Index;
/*
* Compare the headers
*/
for (Index = 0; Index < XEMACPS_HDR_SIZE; Index++) {
if (CheckPtr[Index] != ActualPtr[Index]) {
return XST_FAILURE;
}
}
/*
* Get the length of the payload
*/
BytesLeft = *(u16 *) &ActualPtr[12];
/*
* Do endian swap from big back to little-endian.
*/
BytesLeft = Xil_EndianSwap16(BytesLeft);
/*
* Validate the payload
*/
Counter = 0;
ActualPtr = &ActualPtr[14];
/*
* Check 8 bit incrementing pattern
*/
while (BytesLeft && (Counter < 256)) {
if (*ActualPtr++ != (char) Counter++) {
return XST_FAILURE;
}
BytesLeft--;
}
/*
* Check 16 bit incrementing pattern
*/
while (BytesLeft) {
if (*ActualPtr++ != (char) (Counter >> 8)) { /* high */
return XST_FAILURE;
}
BytesLeft--;
if (!BytesLeft)
break;
if (*ActualPtr++ != (char) Counter++) { /* low */
return XST_FAILURE;
}
BytesLeft--;
}
return XST_SUCCESS;
}
/****************************************************************************/
/**
* This function sets all bytes of a frame to 0.
*
* @param FramePtr is a pointer to the frame itself.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void EmacPsUtilFrameMemClear(EthernetFrame * FramePtr)
{
u32 *Data32Ptr = (u32 *) FramePtr;
u32 WordsLeft = sizeof(EthernetFrame) / sizeof(u32);
/* frame should be an integral number of words */
while (WordsLeft--) {
*Data32Ptr++ = 0xDEADBEEF;
}
}
/****************************************************************************/
/**
*
* This function copys data from source to desitnation for n bytes.
*
* @param Destination is the targeted string to copy to.
* @param Source is the source string to copy from.
* @param n is number of bytes to be copied.
*
* @note This function is similiar to strncpy(), however strncpy will
* stop either at null byte or n bytes is been copied.
* This function will copy n bytes without checking the content.
*
*****************************************************************************/
void EmacPsUtilstrncpy(char *Destination, const char *Source, u32 n)
{
do {
*Destination++ = *Source++;
} while (--n != 0);
}
/****************************************************************************/
/**
*
* This function sets the emacps to loopback mode.
*
* @param EmacPsInstancePtr is the XEmacPs driver instance.
*
* @note None.
*
*****************************************************************************/
void EmacPsUtilEnterLocalLoopback(XEmacPs * EmacPsInstancePtr)
{
u32 reg;
reg = XEmacPs_ReadReg(EmacPsInstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
XEmacPs_WriteReg(EmacPsInstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
reg | XEMACPS_NWCTRL_LOOPEN_MASK);
}
/****************************************************************************/
/**
*
* This function detects the PHY address by looking for successful MII status
* register contents.
*
* @param The XEMACPS driver instance
*
* @return The address of the PHY (defaults to 32 if none detected)
*
* @note None.
*
*****************************************************************************/
#define PHY_DETECT_REG1 2
#define PHY_DETECT_REG2 3
u32 XEmacPsDetectPHY(XEmacPs * EmacPsInstancePtr)
{
u32 PhyAddr;
int Status;
u16 PhyReg1;
u16 PhyReg2;
for (PhyAddr = 0; PhyAddr <= 31; PhyAddr++) {
Status = XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr,
PHY_DETECT_REG1, &PhyReg1);
Status |= XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr,
PHY_DETECT_REG2, &PhyReg2);
if ((Status == XST_SUCCESS) &&
(PhyReg1 > 0x0000) && (PhyReg1 < 0xffff) &&
(PhyReg2 > 0x0000) && (PhyReg2 < 0xffff)) {
/* Found a valid PHY address */
return PhyAddr;
}
}
return PhyAddr; /* default to 32(max of iteration) */
}
/****************************************************************************/
/**
*
* This function sets the PHY to loopback mode.
*
* @param The XEMACPS driver instance
* @param Speed is the loopback speed 10/100 Mbit.
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*
*****************************************************************************/
#ifdef PEEP /* Define PEEP in xemacps_example.h if the example is run on PEEP*/
#define PHY_REG0_RESET 0x8000
#define PHY_REG0_LOOPBACK 0x4000
#define PHY_REG0_10 0x0100
#define PHY_REG0_100 0x2100
#define PHY_REG0_1000 0x0140
#define PHY_R20_DFT_SPD_MASK 0x0070
#define PHY_R20_DFT_SPD_10 0x0040
#define PHY_R20_DFT_SPD_100 0x0050
#define PHY_R20_DFT_SPD_1000 0x0060
int EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, int Speed)
{
int Status;
u16 PhyReg0 = 0;
u16 PhyReg20 = 0;
u32 PhyAddr;
/* Detect the PHY address */
PhyAddr = XEmacPsDetectPHY(EmacPsInstancePtr);
if (PhyAddr >= 32) {
EmacPsUtilErrorTrap("Error detect phy");
return XST_FAILURE;
}
Status = XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 20, &PhyReg20);
Status |= XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 0, &PhyReg0);
PhyReg20 &= ~PHY_R20_DFT_SPD_MASK;
switch (Speed) {
case 10:
PhyReg20 |= PHY_R20_DFT_SPD_10;
break;
case 100:
PhyReg20 |= PHY_R20_DFT_SPD_100;
break;
case 1000:
PhyReg20 |= PHY_R20_DFT_SPD_1000;
break;
default:
EmacPsUtilErrorTrap("Error: speed not recognized ");
return XST_FAILURE;
}
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 20, PhyReg20);
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0,
PhyReg0 | PHY_REG0_RESET);
/* setup speed and duplex */
switch (Speed) {
case 10:
PhyReg0 = PHY_REG0_10;
break;
case 100:
PhyReg0 = PHY_REG0_100;
break;
case 1000:
PhyReg0 = PHY_REG0_1000;
break;
default:
EmacPsUtilErrorTrap("Error: speed not recognized ");
return XST_FAILURE;
}
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0, PhyReg0);
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0,
(PhyReg0 | PHY_REG0_RESET));
sleep(1);
Status |= XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 0, &PhyReg0);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error setup phy speed");
return XST_FAILURE;
}
/* enable loopback */
PhyReg0 |= PHY_REG0_LOOPBACK;
Status = XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0, PhyReg0);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error setup phy loopback");
return XST_FAILURE;
}
return XST_SUCCESS;
}
#else /*For Zynq board*/
#define PHY_REG0_RESET 0x8000
#define PHY_REG0_LOOPBACK 0x4000
#define PHY_REG0_10 0x0100
#define PHY_REG0_100 0x2100
#define PHY_REG0_1000 0x0140
#define PHY_REG21_10 0x0030
#define PHY_REG21_100 0x2030
#define PHY_REG21_1000 0x0070
int EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, int Speed)
{
int Status;
u16 PhyReg0 = 0;
u16 PhyReg21 = 0;
u16 PhyReg22 = 0;
u32 PhyAddr;
/*
* Detect the PHY address
*/
PhyAddr = XEmacPsDetectPHY(EmacPsInstancePtr);
if (PhyAddr >= 32) {
EmacPsUtilErrorTrap("Error detect phy");
return XST_FAILURE;
}
/*
* Setup speed and duplex
*/
switch (Speed) {
case 10:
PhyReg0 |= PHY_REG0_10;
PhyReg21 |= PHY_REG21_10;
break;
case 100:
PhyReg0 |= PHY_REG0_100;
PhyReg21 |= PHY_REG21_100;
break;
case 1000:
PhyReg0 |= PHY_REG0_1000;
PhyReg21 |= PHY_REG21_1000;
break;
default:
EmacPsUtilErrorTrap("Error: speed not recognized ");
return XST_FAILURE;
}
Status = XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0, PhyReg0);
/*
* Make sure new configuration is in effect
*/
Status = XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 0, &PhyReg0);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error setup phy speed");
return XST_FAILURE;
}
/*
* Switching to PAGE2
*/
PhyReg22 = 0x2;
Status = XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 22, PhyReg22);
/*
* Adding Tx and Rx delay. Configuring loopback speed.
*/
Status = XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 21, PhyReg21);
/*
* Make sure new configuration is in effect
*/
Status = XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 21, &PhyReg21);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error setting Reg 21 in Page 2");
return XST_FAILURE;
}
/*
* Switching to PAGE0
*/
PhyReg22 = 0x0;
Status = XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 22, PhyReg22);
/*
* Issue a reset to phy
*/
Status = XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 0, &PhyReg0);
PhyReg0 |= PHY_REG0_RESET;
Status = XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0, PhyReg0);
Status = XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 0, &PhyReg0);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error reset phy");
return XST_FAILURE;
}
/*
* Enable loopback
*/
PhyReg0 |= PHY_REG0_LOOPBACK;
Status = XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0, PhyReg0);
Status = XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 0, &PhyReg0);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error setup phy loopback");
return XST_FAILURE;
}
/*
* Delay loop
*/
sleep(1);
return XST_SUCCESS;
}
#endif /*PEEP*/
/****************************************************************************/
/**
*
* This function is called by example code when an error is detected. It
* can be set as a breakpoint with a debugger or it can be used to print out
* the given message if there is a UART or STDIO device.
*
* @param Message is the text explaining the error
*
* @return None
*
* @note None
*
*****************************************************************************/
void EmacPsUtilErrorTrap(const char *Message)
{
static int Count = 0;
Count++;
#ifdef STDOUT_BASEADDRESS
xil_printf("%s\r\n", Message);
#else
(void) Message;
#endif
}

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/******************************************************************************
*
* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_ieee1588.h
*
* Defines hash defines, common data types and prototypes to be used with the
* PTP standalone example source code residing in this directory.
*
* The PTP standalone example files implement the basic PTPv2 protocol as an
* example application. However the accuracy of clock offset adjustment is
* not guaranted as of now. Also the clock rate adjustment and signalling
* frames are not implemented. Also it may not be implementing all aspects of
* PTPv2 strictly as per specs. Since it is based on AVB driver (which is
* 802.1as based), some aspects of 802.1as which are not there in IEEE1588
* may be there in the protocol implementation inadvertently. The sync frame
* interval, announce frame interval and PDelayReq frame intervals are
* hard-coded.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a asa 09/16/11 First release based on AVB driver
* 1.01a asa 03/03/12 New hashdefines are added and new function prototypes
* are added.
*
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_IEEE1588_H
#define XEMACPS_IEEE1588_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define DEBUG_XEMACPS_LEVEL1 /*
* Error messages which should be printed on
* console. It does not include error messages
* from interrupt service routines.
*/
#undef DEBUG_LEVEL_TWO /*
* Other debug messages, e.g. function names being
* executed, PTP protocl messages etc.
*/
/* PTP Packet Message Type Definitions */
#define XEMACPS_PTP_TYPE_SYNC 0x0
#define XEMACPS_PTP_TYPE_FOLLOW_UP 0x8
#define XEMACPS_PTP_TYPE_PDELAYREQ 0x2
#define XEMACPS_PTP_TYPE_PDELAYRESP 0x3
#define XEMACPS_PTP_TYPE_PDELAYRESP_FOLLOW_UP 0xA
#define XEMACPS_PTP_TYPE_ANNOUNCE 0xB
#define XEMACPS_PTP_TYPE_SIGNALING 0xC
#define XEMACPS_PKT_TYPE_DISABLED 0xffff
#define XEMACPS_PKT_MAX_BUF_LEN 128
/*
* XEMACPS_ANNOUNCE_RECEIPT_TIMEOUT is the number of announce
* intervals without the receipt of an Announce message from
* the GM that are allowed before the GM is assumed to be no
* longer present and BMCA should be run again
*/
#define XEMACPS_ANNOUNCE_RECEIPT_TIMEOUT 5
/*
* XEMACPS_SYNC_RECEIPT_TIMEOUT is the number of sync intervals
* without the receipt of an Sync message from the GM that are
* allowed before the GM is assumed to be no longer present and
* BMCA should be run again
*/
#define XEMACPS_SYNC_RECEIPT_TIMEOUT 5
/*
* XEMACPS_NEIGHBOR_PROP_DELAY_THRESH is the maximum allowed delay
* (in nanosecs) across a full duplex link for which the PTP protocol is
* allowed to function. Although this parameter is defined in the
* IEEE spec, no default is defined.
*/
#define XEMACPS_NEIGHBOR_PROP_DELAY_THRESH 5000
/*
* XEMACPS_ALLOWED_LOST_RESPONSES is the number of Pdelay_Req messages for
* which a valid response is not received, above which the Peer should no
* longer be considered PTPv2 capable.
*/
#define XEMACPS_ALLOWED_LOST_RESPONSES 3
#ifdef PEEP
/*
* Currently the PEEP/GEM is drivern by 50 MHz clock. Which means each
* clock cycle corresponds to 20 nano seconds. Hence the increment
* register should contain a value of 20 (0x14).
*/
#define XEMACPS_1588_INC_VAL 0x00000014
#endif
/* Standard PTP Frame Field Definitions (from IEEE1588 specification) */
#define XEMACPS_PTP_ETHERTYPE 0x88F7
#define XEMACPS_PTP_VERSION_PTP 2
/* Real Time Clock Definitions.*/
#define XEMACPS_ONE_SECOND 1000000000 /* In ns */
/*
* Define how often to re-calculate the RTC Increment This value indicates how
* many good Sync/FollowUp message pairs are received before the
* re-calculation is performed.
*/
#define XEMACPS_NUM_SYNC_FU_PAIR_CALC_RTC_INCREMENT 2
/* PHY register number and register content mask used for PHY detection.*/
#define PHY_DETECT_REG 1
#define PHY_DETECT_MASK 0x1808
/* PHY register 0 and Register 16 masks*/
#define PHY_R0_RESET 0x8000
#define PHY_R0_LOOPBACK 0x4000
#define PHY_R0_AUTONEG_EN 0x1000
#define PHY_R0_AUTONEG_START 0x0200
#define PHY_R0_10 0x0100
#define PHY_R0_100 0x2100
#define PHY_R0_1000 0x0140
#define PHY_R16_FIFO_DEPTH 0xF078
/* Maximum buffer length used to store the PTP pakcets */
#define XEMACPS_PACKET_LEN 1538
/* BD alignment used to allocate the BDs */
#define XEMACPS_IEEE1588_BD_ALIGNMENT 4
/* Number of BDs used in the Tx and Rx paths */
#define XEMACPS_IEEE1588_NO_OF_RX_DESCS 32
#define XEMACPS_IEEE1588_NO_OF_TX_DESCS 32
/* Various offsets in the PTP Ethernet packet and masks to extract contents */
#define XEMACPS_MSGTYP_OFFSET 14
#define XEMACPS_MSGTYP_MASK 0x0F
#define XEMACPS_VERSPTP_OFFSET 15
#define XEMACPS_MSGLENGTH_OFFSET 16
#define XEMACPS_FLAGS_OFFSET 20
#define XEMACPS_CORRFIELD_OFFSET 22
#define XEMACPS_PORTIDENTITY_OFFSET 34
#define XEMACPS_SEQID_OFFSET 44
#define XEMACPS_CONTROL_OFFSET 46
#define XEMACPS_LOGMSG_INTERVAL_OFFSET 47
#define XEMACPS_PRECISE_TS_OFFSET 48
#define XEMACPS_CURRUTCOFFSET_OFFSET 58
#define XEMACPS_GMPRI_ONE_OFFSET 61
#define XEMACPS_GM_CLK_QUALITY_OFFSET 62
#define XEMACPS_GMPRI_TWO_OFFSET 66
#define XEMACPS_GM_IDENTITY_OFFSET 67
#define XEMACPS_STEPS_REMOVED_OFFSET 75
#define XEMACPS_TIMESOURCE_OFFSET 77
#define XEMACPS_TLVTYPE_OFFSET 78
#define XEMACPS_LENGTHFIELD_OFFSET 80
#define XEMACPS_PATHSEQ_OFFSET 82
#define XEMACPS_REQPORTID_OFFSET 58
/*
* The PTP message type, length value, flags value that are
* populated in different PTP frames
*/
#define XEMACPS_SYNCFRM_MSG_TYPE 0x10
#define XEMACPS_SYNCFRM_LENGTH 0x002C
#define XEMACPS_SYNCFRM_FLAGS_VAL 0x0200
#define XEMACPS_FOLLOWUPFRM_MSG_TYPE 0x18
#define XEMACPS_FOLLOWUPFRM_LENGTH 0x004C
#define XEMACPS_PDELAYREQFRM_LENGTH 54
#define XEMACPS_PDELAYREQFRM_FLAGS_VAL 0x0200
#define XEMACPS_PDELAYREQFRM_MSG_TYPE 0x02
#define XEMACPS_PDELAYRESPFRM_MSG_TYPE 0x03
#define XEMACPS_PDELAYRESPFRM_LENGTH 54
#define XEMACPS_PDELAYRESPFOLLOWUPFRM_MSG_TYPE 0x0A
#define XEMACPS_PDELAYRESPFOLLOWUP_LENGTH 54
#define XEMACPS_ANNOUNCEFRM_MSG_TYPE 0x1B
#define XEMACPS_ANNOUNCEFRM_LENGTH 0x0040
#define XEMACPS_ANNOUNCEFRM_FLAGS_VAL 0x0008
/* The total length of various PTP packets */
#define XEMACPS_ANNOUNCEMSG_TOT_LEN 90
#define XEMACPS_SYNCMSG_TOT_LEN 58
#define XEMACPS_FOLLOWUPMSG_TOT_LEN 90
#define XEMACPS_PDELAYREQMSG_TOT_LEN 68
#define XEMACPS_PDELAYRESPMSG_TOT_LEN 68
#define XEMACPS_PDELAYRESPFOLLOWUP_TOT_LEN 68
/*
* The bit field information for different PTP packets in the variable
* PTPSendPacket. This variable controls the sending of PTP packets.
*/
#define SEND_PDELAY_RESP 0x00000001
#define SEND_PDELAY_RESP_FOLLOWUP 0x00000002
#define SEND_PDELAY_REQ 0x00000004
#define SEND_SYNC 0x00000008
#define SEND_FOLLOW_UP 0x00000010
#define NS_PER_SEC 1000000000ULL /* Nanoseconds per second */
#define FP_MULT 1000ULL
/* Advertisement control register. */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_100_AND_10 (ADVERTISE_10FULL | ADVERTISE_100FULL | \
ADVERTISE_10HALF | ADVERTISE_100HALF)
#define ADVERTISE_100 (ADVERTISE_100FULL | ADVERTISE_100HALF)
#define ADVERTISE_10 (ADVERTISE_10FULL | ADVERTISE_10HALF)
#define ADVERTISE_1000 0x0300
#define IEEE_CONTROL_REG_OFFSET 0
#define IEEE_STATUS_REG_OFFSET 1
#define IEEE_AUTONEGO_ADVERTISE_REG 4
#define IEEE_PARTNER_ABILITIES_1_REG_OFFSET 5
#define IEEE_PARTNER_ABILITIES_2_REG_OFFSET 8
#define IEEE_PARTNER_ABILITIES_3_REG_OFFSET 10
#define IEEE_1000_ADVERTISE_REG_OFFSET 9
#define IEEE_SPECIFIC_STATUS_REG 17
#define IEEE_CTRL_1GBPS_LINKSPEED_MASK 0x2040
#define IEEE_CTRL_LINKSPEED_MASK 0x0040
#define IEEE_CTRL_LINKSPEED_1000M 0x0040
#define IEEE_CTRL_LINKSPEED_100M 0x2000
#define IEEE_CTRL_LINKSPEED_10M 0x0000
#define IEEE_CTRL_RESET_MASK 0x8000
#define IEEE_CTRL_AUTONEGOTIATE_ENABLE 0x1000
#define IEEE_STAT_AUTONEGOTIATE_CAPABLE 0x0008
#define IEEE_STAT_AUTONEGOTIATE_COMPLETE 0x0020
#define IEEE_STAT_AUTONEGOTIATE_RESTART 0x0200
#define IEEE_STAT_1GBPS_EXTENSIONS 0x0100
#define IEEE_AN1_ABILITY_MASK 0x1FE0
#define IEEE_AN3_ABILITY_MASK_1GBPS 0x0C00
#define IEEE_AN1_ABILITY_MASK_100MBPS 0x0380
#define IEEE_AN1_ABILITY_MASK_10MBPS 0x0060
#define PHY_REG0_RESET 0x8000
#define PHY_REG0_LOOPBACK 0x4000
#define PHY_REG0_10 0x0100
#define PHY_REG0_100 0x2100
#define PHY_REG0_1000 0x0140
#define PHY_REG21_10 0x0030
#define PHY_REG21_100 0x2030
#define PHY_REG21_1000 0x0070
/* Frequency setting */
#define SLCR_LOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x4)
#define SLCR_UNLOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x8)
#define SLCR_GEM0_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x140)
#define SLCR_GEM1_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x144)
#ifdef PEEP
#define SLCR_GEM_10M_CLK_CTRL_VALUE 0x00103031
#define SLCR_GEM_100M_CLK_CTRL_VALUE 0x00103001
#define SLCR_GEM_1G_CLK_CTRL_VALUE 0x00103011
#endif
#define SLCR_LOCK_KEY_VALUE 0x767B
#define SLCR_UNLOCK_KEY_VALUE 0xDF0D
#define SLCR_ADDR_GEM_RST_CTRL (XPS_SYS_CTRL_BASEADDR + 0x214)
#define EMACPS_SLCR_DIV_MASK 0xFC0FC0FF
/**************************** Type Definitions *******************************/
/*
* This typedef defines the format for a data structure which stores the Port
* Identity information specified in IEEE1588.
*/
typedef struct
{
u8 ClockIdentity[8];
u16 PortNumber;
} XEmacPs_PortIdentity;
/*
* This typedef defines the format for a data structure which stores the Clock
* Identity information specified in IEEE1588.
*/
typedef struct
{
u8 ClockIdentity[8];
} XEmacPs_ClockIdentity;
/*
* This typedef defines the quality of a clock
*/
typedef struct
{
u8 clockClass;
u8 clockAccuracy;
u16 offsetScaledLogVariance;
} XEmacPs_ClockQuality;
/*
* This typedef defines the format for a data structure which stores the
* relevant fields which are captured from Announce Packets.
*/
typedef struct
{
XEmacPs_PortIdentity SourcePortIdentity;
XEmacPs_ClockIdentity GrandmasterIdentity;
u16 StepsRemoved;
XEmacPs_ClockQuality ClockQuality;
u8 GrandmasterPriority1;
u8 GrandmasterPriority2;
u8 IAmTheRtcMaster;
u16 TlvLengthField;
char LogMessageInterval;
u16 AnnounceIntervalDuration;
} XEmacPs_BmcData;
/*
* This typedef defines the format for a data structure which stores
* information relating to the 1588 based PTP timing calculations.
*/
typedef struct
{
u32 Nanosec; /* ns value for sync frame tx request */
u32 SlaveSyncTimestampSec;
u32 SlaveSyncTimestampNSec;
u32 MasterCorrectionField;/* Correction Field from rx'd follow-up */
u32 PDelayTimestampT1; /* T1 :PDelayReq Frame transmission */
u32 PDelayTimestampT2; /* T2 :PDelayReq rx'd at link partner */
u32 PDelayTimestampT3; /* T3 :PDelayResp Frame reception */
u32 PDelayTimestampT4; /* T4 :PDelayResp tx'd by link partner */
u32 LinkDelay; /* Last calculated value of Link Delay */
u32 NewSlaveTime; /* RTC ns at slave for last rx'd sync */
u32 NewMasterTime; /* RTC ns at master for last tx'd sync */
u32 OldSlaveTime; /* Stored RTC slave ns for past sync rx */
u32 OldMasterTime; /* Stored RTC master ns for past sync tx*/
u32 PDelayReqRecdTSNs;
u32 PDelayReqRecdTSSec;
u32 PDelayRespTxedTSNs;
u32 PDelayRespTxedTSSec;
} XEmacPs_PtpStruct;
/*
* This typedef defines the format for a data structure which stores the last
* used sequence ID for all of the PTP timing frames.
*/
typedef struct
{
u16 SyncSequenceId;
u16 FollowUpSequenceId;
u16 PDelayReqSequenceId;
u16 PDelayRespSequenceId;
u16 PDelayFollowUpSequenceId;
u16 OldSyncSequenceId;
u16 NewSyncSequenceId;
} XEmacPs_SequenceIdStruct;
/*
* The Signalling frame defines the delays to be used between Sync Frames, Link
* Delay measurements and Announce Frame events
*/
typedef struct
{
u16 SyncIntervalDuration;
u16 LinkDelayIntervalDuration;
u16 AnnounceIntervalDuration;
} XEmacPs_SignallingFrameData;
/*
* This typedef defines the various counters which have to maintained for the
* PTP operation.
*/
typedef struct
{
u16 CounterSyncInterval;
u16 CounterLinkDelayInterval;
u16 CounterAnnounceInterval;
u8 CounterSyncEvents;
} XEmacPs_Counters;
/*
* Keep track of state machine data to make sure we're fully compliant
* with the spec
*/
typedef struct
{
u8 LostResponses; /* Keep track of the state machine errors */
u8 RcvdPDelayResp; /*
* Received a valid PDelayResp packet since
* PDelayReq was sent
*/
u8 RcvdPDelayRespFollowUp;/*
* Received a valid PDelayFollowUp packet
* since PDelayResp was received
*/
XEmacPs_PortIdentity RespPortIdentity;/*
* SourcePortIdentity of the last
* PDelayResp packet received
*/
XEmacPs_PortIdentity RespReqPortIdentity;/*
* RequestingPortIdentity of
* the last PDelayResp packet
received */
} XEmacPs_StateMachineData;
/*
* This struct captures information from RX'd Sync/FollowUp message pairs in a
* format similiar to the MDSyncReceive structure described in the IEEE1588
* specification.
*/
typedef struct
{
u8 LogMessageInterval;
u16 SyncIntervalDuration;
} XEmacPs_MDSyncReceive;
typedef struct
{
u32 Seconds;
u32 NanoSeconds;
} XEmacPs_RtcFormat;
/*
* The XEmacPs_Ieee1588 driver instance data. The user is required to allocate
* a variable of this type for every PTP device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
/* The Emac Pss instance to be used for accessing the hardware */
XEmacPs *EmacPsInstance;
/* The current port protocol state */
u32 PtpProtocolState;
u32 PtpNewPktRecd;
/* The PTP algorithm can be started and stopped as requested */
u32 PtpIsRunning;
/* The peer must be AS capable before we start full blown PTP */
u32 PeerIeee1588v2Capable;
u32 PTPLocked;
/* Store the info from the latest RX'd Sync/Follow message pair */
XEmacPs_MDSyncReceive LatestMDSyncReceive;
/* Contains the local port Identity information */
XEmacPs_PortIdentity PortIdLocal;
/* Create a data structure for the Best Master Clock Algorithm (BMCA)*/
XEmacPs_BmcData CurrentBmc;
/* Create a data structure for the Precise Timing Protocol (PTP) */
XEmacPs_PtpStruct PtpRecords;
/* Create data structure to record the PTP frames Sequence ID values*/
XEmacPs_SequenceIdStruct SequenceIdRecords;
/* Create a data structure to store the Signalling frame information*/
XEmacPs_SignallingFrameData SignallingFrameData;
/* Create a data structure to store various PTP counters/timers */
XEmacPs_Counters PtpCounters;
/* Create a data structure to store state machine flags */
XEmacPs_StateMachineData StateMachineData;
/* Buffers to store the last recd PTP packet */
u8 LastRecdSyncFrm[XEMACPS_PKT_MAX_BUF_LEN];
u8 LastRecdFollowUpFrm[XEMACPS_PKT_MAX_BUF_LEN];
u8 LastRecdPDelayReqFrm[XEMACPS_PKT_MAX_BUF_LEN];
u8 LastRecdPDelayRespFrm[XEMACPS_PKT_MAX_BUF_LEN];
u8 LastRecdPDelayRespFollowUpFrm[XEMACPS_PKT_MAX_BUF_LEN];
u8 LastRecdSignallingFrm[XEMACPS_PKT_MAX_BUF_LEN];
u8 LastRecdAnnounceFrm[XEMACPS_PKT_MAX_BUF_LEN];
/* Buffers to store the PTP packet to be Txed */
u8 SyncFrmToTx[XEMACPS_PKT_MAX_BUF_LEN];
u8 FollowUpFrmToTx[XEMACPS_PKT_MAX_BUF_LEN];
u8 PDelayReqFrmToTx[XEMACPS_PKT_MAX_BUF_LEN];
u8 PDelayRespFrmToTx[XEMACPS_PKT_MAX_BUF_LEN];
u8 PDelayRespFollowUpFrmToTx[XEMACPS_PKT_MAX_BUF_LEN];
u8 SignallingFrmToTx[XEMACPS_PKT_MAX_BUF_LEN];
u8 AnnounceFrmToTx[XEMACPS_PKT_MAX_BUF_LEN];
} XEmacPs_Ieee1588;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void XEmacPs_PtpTimerInterruptHandler(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_PtpRxInterruptHandler(XEmacPs_Ieee1588 *InstancePtr);
int XEmacPs_PtpTxPacket(XEmacPs_Ieee1588 *InstancePtr, u8 *PacketBuf,
int PacketLen);
u32 XEmacPs_ComparePortIdentity(
XEmacPs_PortIdentity Identity1,
XEmacPs_PortIdentity Identity2);
u32 XEmacPs_CompareClockIdentity(
XEmacPs_ClockIdentity Identity1,
XEmacPs_ClockIdentity Identity2);
void XEmacPs_MasterSendAnnounce(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_MasterSendSync(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_MasterSendFollowUp(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_SendPDelayReq(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_SendPDelayResp(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_SendPDelayRespFollowUp(XEmacPs_Ieee1588 *InstancePtr);
u32 XEmacPs_IsRxFramePTP(u8 *PacketBuf);
void XEmacPs_DecodeRxSync(XEmacPs_Ieee1588 *InstancePtr,u8 *PacketBuf);
void XEmacPs_DecodeRxFollowUp(XEmacPs_Ieee1588 *InstancePtr, u8 *PacketBuf);
void XEmacPs_DecodeRxPDelayResp(XEmacPs_Ieee1588 *InstancePtr, u8 *PacketBuf);
void XEmacPs_DecodeRxPDelayRespFollowUp(XEmacPs_Ieee1588 *InstancePtr,
u8 *PacketBuf);
void XEmacPs_DecodeRxSignaling(XEmacPs_Ieee1588 *InstancePtr, u8 *PacketBuf);
u16 XEmacPs_UpdateIntervalDuration(u16 currentIntervalDuration,
signed char logMeanVal);
u16 XEmacPs_ConvertLogMeanToDuration(signed char logMeanVal);
signed char XEmacPs_ConvertDurationToLogMean(u16 fractionalVal);
void XEmacPs_UpdateLogMeanMessageInterval(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_SetupSourcePortIdentity(XEmacPs_Ieee1588 *InstancePtr,
XEmacPs_PortIdentity systemIdentity);
void XEmacPs_DecodeTxAnnounceFrame(XEmacPs_Ieee1588 *InstancePtr,
u8 *PacketBuf);
void XEmacPs_DecodeRxAnnounceFrame(XEmacPs_Ieee1588 *InstancePtr,
u8 *PacketBuf);
void XEmacPs_ReadAnnounceFrame(u8 *PacketBuf, XEmacPs_BmcData *AnnounceFrame);
void XEmacPs_UpdateBmcRecords(XEmacPs_BmcData *NewMaster,
XEmacPs_BmcData *CurrentBmc);
u32 XEmacPs_BestMasterClockAlgorithm(XEmacPs_BmcData *AnnounceFrame,
XEmacPs_BmcData *CurrentBmc);
void XEmacPs_BecomeRtcMaster(XEmacPs_Ieee1588 *InstancePtr,
u8 txAnnounceHasWon);
void XEmacPs_BecomeRtcSlave(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_ChangePTPLockStatus(XEmacPs_Ieee1588 *InstancePtr, u8 locked);
void XEmacPs_ChangePeerIeee1588v2Capability(XEmacPs_Ieee1588 *InstancePtr,
u8 capable);
void XEmacPs_CalcDelay(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_CalcRtcOffset(XEmacPs_Ieee1588 *InstancePtr);
void XEmacPs_UpdateRtcIncrement(XEmacPs_Ieee1588 *InstancePtr);
u32 XEmacPs_htonll (unsigned long long int n);
u32 XEmacPs_ntohll (long long int n);
u8 XEmacPs_GetMsgType (u8 *PacketBuf);
void XEmacPs_GetPortIdentity(u8 *PacketBuf, XEmacPs_PortIdentity *portID);
u16 XEmacPs_GetSequenceId(u8 *PacketBuf);
u16 XEmacPs_IncSequenceId(u8 *PacketBuf);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor);
unsigned int XEmacPs_TsuCalcClk(u32 Freq);
extern volatile u8 PDelayRespSent;
extern volatile u32 PTPSendPacket;
extern volatile u8 SyncSent;
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

2384
XilinxProcessorIPLib/drivers/emacps/examples/xemacps_ieee1588_example.c Executable file
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40
XilinxProcessorIPLib/drivers/emacps/src/Makefile Executable file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES:=*.c
INCLUDEFILES:=*.h
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
libs: banner xemacps_libs clean
%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling emacps"
xemacps_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: xemacps_includes
xemacps_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

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XilinxProcessorIPLib/drivers/emacps/src/xemacps.c Executable file
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/* $Id: xemacps.c,v 1.1.2.3 2011/05/17 12:00:33 anirudh Exp $ */
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps.c
*
* The XEmacPs driver. Functions in this file are the minimum required functions
* for this driver. See xemacps.h for a detailed description of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* </pre>
******************************************************************************/
/***************************** Include Files *********************************/
#include "xemacps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void XEmacPs_StubHandler(void); /* Default handler routine */
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* Initialize a specific XEmacPs instance/driver. The initialization entails:
* - Initialize fields of the XEmacPs instance structure
* - Reset hardware and apply default options
* - Configure the DMA channels
*
* The PHY is setup independently from the device. Use the MII or whatever other
* interface may be present for setup.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param CfgPtr is the device configuration structure containing required
* hardware build data.
* @param EffectiveAddress is the base address of the device. If address
* translation is not utilized, this parameter can be passed in using
* CfgPtr->Config.BaseAddress to specify the physical base address.
*
* @return
* - XST_SUCCESS if initialization was successful
*
******************************************************************************/
int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
u32 EffectiveAddress)
{
/* Verify arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CfgPtr != NULL);
/* Set device base address and ID */
InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
InstancePtr->Config.BaseAddress = EffectiveAddress;
/* Set callbacks to an initial stub routine */
InstancePtr->SendHandler = (XEmacPs_Handler) XEmacPs_StubHandler;
InstancePtr->RecvHandler = (XEmacPs_Handler) XEmacPs_StubHandler;
InstancePtr->ErrorHandler = (XEmacPs_ErrHandler) XEmacPs_StubHandler;
/* Reset the hardware and set default options */
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
XEmacPs_Reset(InstancePtr);
return (XST_SUCCESS);
}
/*****************************************************************************/
/**
* Start the Ethernet controller as follows:
* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
* - Start the SG DMA send and receive channels and enable the device
* interrupt
*
* @param InstancePtr is a pointer to the instance to be worked on.
*
* @return N/A
*
* @note
* Hardware is configured with scatter-gather DMA, the driver expects to start
* the scatter-gather channels and expects that the user has previously set up
* the buffer descriptor lists.
*
* This function makes use of internal resources that are shared between the
* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
* device options while another is trying to start the device, the user is
* required to provide protection of this shared data (typically using a
* semaphore).
*
* This function must not be preempted by an interrupt that may service the
* device.
*
******************************************************************************/
void XEmacPs_Start(XEmacPs *InstancePtr)
{
u32 Reg;
/* Assert bad arguments and conditions */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
/* If already started, then there is nothing to do */
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
return;
}
/* Start DMA */
/* When starting the DMA channels, both transmit and receive sides
* need an initialized BD list.
*/
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXQBASE_OFFSET,
InstancePtr->RxBdRing.BaseBdAddr);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQBASE_OFFSET,
InstancePtr->TxBdRing.BaseBdAddr);
/* clear any existed int status */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
XEMACPS_IXR_ALL_MASK);
/* Enable transmitter if not already enabled */
if (InstancePtr->Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
if (!(Reg & XEMACPS_NWCTRL_TXEN_MASK)) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
Reg | XEMACPS_NWCTRL_TXEN_MASK);
}
}
/* Enable receiver if not already enabled */
if (InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
if (!(Reg & XEMACPS_NWCTRL_RXEN_MASK)) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
Reg | XEMACPS_NWCTRL_RXEN_MASK);
}
}
/* Enable TX and RX interrupts */
XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
XEMACPS_IXR_RX_ERR_MASK | XEMACPS_IXR_FRAMERX_MASK |
XEMACPS_IXR_TXCOMPL_MASK));
/* Mark as started */
InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
return;
}
/*****************************************************************************/
/**
* Gracefully stop the Ethernet MAC as follows:
* - Disable all interrupts from this device
* - Stop DMA channels
* - Disable the tansmitter and receiver
*
* Device options currently in effect are not changed.
*
* This function will disable all interrupts. Default interrupts settings that
* had been enabled will be restored when XEmacPs_Start() is called.
*
* @param InstancePtr is a pointer to the instance to be worked on.
*
* @note
* This function makes use of internal resources that are shared between the
* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
* setting device options while another is trying to start the device, the user
* is required to provide protection of this shared data (typically using a
* semaphore).
*
* Stopping the DMA channels causes this function to block until the DMA
* operation is complete.
*
******************************************************************************/
void XEmacPs_Stop(XEmacPs *InstancePtr)
{
u32 Reg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Disable all interrupts */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
XEMACPS_IXR_ALL_MASK);
/* Disable the receiver & transmitter */
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg &= ~XEMACPS_NWCTRL_RXEN_MASK;
Reg &= ~XEMACPS_NWCTRL_TXEN_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
/* Mark as stopped */
InstancePtr->IsStarted = 0;
}
/*****************************************************************************/
/**
* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
* transmitter, and the receiver.
*
* Steps to reset
* - Stops transmit and receive channels
* - Stops DMA
* - Configure transmit and receive buffer size to default
* - Clear transmit and receive status register and counters
* - Clear all interrupt sources
* - Clear phy (if there is any previously detected) address
* - Clear MAC addresses (1-4) as well as Type IDs and hash value
*
* All options are placed in their default state. Any frames in the
* descriptor lists will remain in the lists. The side effect of doing
* this is that after a reset and following a restart of the device, frames
* were in the list before the reset may be transmitted or received.
*
* The upper layer software is responsible for re-configuring (if necessary)
* and restarting the MAC after the reset. Note also that driver statistics
* are not cleared on reset. It is up to the upper layer software to clear the
* statistics if needed.
*
* When a reset is required, the driver notifies the upper layer software of
* this need through the ErrorHandler callback and specific status codes.
* The upper layer software is responsible for calling this Reset function
* and then re-configuring the device.
*
* @param InstancePtr is a pointer to the instance to be worked on.
*
******************************************************************************/
void XEmacPs_Reset(XEmacPs *InstancePtr)
{
u32 Reg;
u8 i;
char EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Stop the device and reset hardware */
XEmacPs_Stop(InstancePtr);
InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
/* Setup hardware with default values */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
(XEMACPS_NWCTRL_STATCLR_MASK |
XEMACPS_NWCTRL_MDEN_MASK) &
~XEMACPS_NWCTRL_LOOPEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET,
XEMACPS_NWCFG_100_MASK |
XEMACPS_NWCFG_FDEN_MASK |
XEMACPS_NWCFG_UCASTHASHEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET,
((((XEMACPS_RX_BUF_SIZE / XEMACPS_RX_BUF_UNIT) +
((XEMACPS_RX_BUF_SIZE %
XEMACPS_RX_BUF_UNIT) ? 1 : 0)) <<
XEMACPS_DMACR_RXBUF_SHIFT) &
XEMACPS_DMACR_RXBUF_MASK) |
XEMACPS_DMACR_RXSIZE_MASK |
XEMACPS_DMACR_TXSIZE_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXQBASE_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQBASE_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
XEMACPS_IXR_ALL_MASK);
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_ISR_OFFSET);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
Reg);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_PHYMNTNC_OFFSET, 0x0);
XEmacPs_ClearHash(InstancePtr);
for (i = 1; i < 5; i++) {
XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
XEmacPs_SetTypeIdCheck(InstancePtr, 0x0, i);
}
/* clear all counters */
for (i = 0; i < (XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4;
i++) {
XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_OCTTXL_OFFSET + i * 4);
}
/* Disable the receiver */
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg &= ~XEMACPS_NWCTRL_RXEN_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
/* Sync default options with hardware but leave receiver and
* transmitter disabled. They get enabled with XEmacPs_Start() if
* XEMACPS_TRANSMITTER_ENABLE_OPTION and
* XEMACPS_RECEIVER_ENABLE_OPTION are set.
*/
XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
~(XEMACPS_TRANSMITTER_ENABLE_OPTION |
XEMACPS_RECEIVER_ENABLE_OPTION));
XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
}
/******************************************************************************/
/**
* This is a stub for the asynchronous callbacks. The stub is here in case the
* upper layer forgot to set the handler(s). On initialization, all handlers are
* set to this callback. It is considered an error for this handler to be
* invoked.
*
******************************************************************************/
void XEmacPs_StubHandler(void)
{
Xil_AssertVoidAlways();
}

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XilinxProcessorIPLib/drivers/emacps/src/xemacps.h Executable file
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@ -0,0 +1,719 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xemacps.h
*
* The Xilinx Embedded Processor Block Ethernet driver.
*
* For a full description of XEMACPS features, please see the hardware spec.
* This driver supports the following features:
* - Memory mapped access to host interface registers
* - Statistics counter registers for RMON/MIB
* - API for interrupt driven frame transfers for hardware configured DMA
* - Virtual memory support
* - Unicast, broadcast, and multicast receive address filtering
* - Full and half duplex operation
* - Automatic PAD & FCS insertion and stripping
* - Flow control
* - Support up to four 48bit addresses
* - Address checking for four specific 48bit addresses
* - VLAN frame support
* - Pause frame support
* - Large frame support up to 1536 bytes
* - Checksum offload
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the XEmacPs. The driver handles transmission and reception
* of Ethernet frames, as well as configuration and control. No pre or post
* processing of frame data is performed. The driver does not validate the
* contents of an incoming frame in addition to what has already occurred in
* hardware.
* A single device driver can support multiple devices even when those devices
* have significantly different configurations.
*
* <b>Initialization & Configuration</b>
*
* The XEmacPs_Config structure is used by the driver to configure itself.
* This configuration structure is typically created by the tool-chain based
* on hardware build properties.
*
* The driver instance can be initialized in
*
* - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* The device supports DMA only as current development plan. No FIFO mode is
* supported. The driver expects to start the DMA channels and expects that
* the user has set up the buffer descriptor lists.
*
* <b>Interrupts and Asynchronous Callbacks</b>
*
* The driver has no dependencies on the interrupt controller. When an
* interrupt occurs, the handler will perform a small amount of
* housekeeping work, determine the source of the interrupt, and call the
* appropriate callback function. All callbacks are registered by the user
* level application.
*
* <b>Virtual Memory</b>
*
* All virtual to physical memory mappings must occur prior to accessing the
* driver API.
*
* For DMA transactions, user buffers supplied to the driver must be in terms
* of their physical address.
*
* <b>DMA</b>
*
* The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
* These BDs are typically chained together into a list the hardware follows
* when transferring data in and out of the packet buffers. Each BD describes
* a memory region containing either a full or partial Ethernet packet.
*
* Interrupt coalescing is not suppoted from this built-in DMA engine.
*
* This API requires the user to understand how the DMA operates. The
* following paragraphs provide some explanation, but the user is encouraged
* to read documentation in xemacps_bdring.h as well as study example code
* that accompanies this driver.
*
* The API is designed to get BDs to and from the DMA engine in the most
* efficient means possible. The first step is to establish a memory region
* to contain all BDs for a specific channel. This is done with
* XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
* follow as BDs are processed. The ring will consist of a user defined number
* of BDs which will all be partially initialized. For example on the transmit
* channel, the driver will initialize all BDs' so that they are configured
* for transmit. The more fields that can be permanently setup at
* initialization, then the fewer accesses will be needed to each BD while
* the DMA engine is in operation resulting in better throughput and CPU
* utilization. The best case initialization would require the user to set
* only a frame buffer address and length prior to submitting the BD to the
* engine.
*
* BDs move through the engine with the help of functions
* XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
* and XEmacPs_BdRingFree().
* All these functions handle BDs that are in place. That is, there are no
* copies of BDs kept anywhere and any BD the user interacts with is an actual
* BD from the same ring hardware accesses.
*
* BDs in the ring go through a series of states as follows:
* 1. Idle. The driver controls BDs in this state.
* 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
* reserve BD(s). Once allocated, the user may setup the BD(s) with
* frame buffer address, length, and other attributes. The user controls
* BDs in this state.
* 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
* in this state are either waiting to be processed by hardware, are in
* process, or have been processed. The DMA engine controls BDs in this
* state.
* 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
* user. Once retrieved, the user can examine each BD for the outcome of
* the DMA transfer. The user controls BDs in this state. After examining
* the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
* into state 1.
*
* Each of the four BD accessor functions operate on a set of BDs. A set is
* defined as a segment of the BD ring consisting of one or more BDs. The user
* views the set as a pointer to the first BD along with the number of BDs for
* that set. The set can be navigated by using macros XEmacPs_BdNext(). The
* user must exercise extreme caution when changing BDs in a set as there is
* nothing to prevent doing a mBdNext past the end of the set and modifying a
* BD out of bounds.
*
* XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
* XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
* tandem. The same BD set retrieved with BdRingAlloc should be the same one
* provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
* BdRIngFree.
*
* <b>Alignment & Data Cache Restrictions</b>
*
* Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
* aligned. Please reference xemacps_bd.h for cache related macros.
*
* DMA Tx:
*
* - If frame buffers exist in cached memory, then they must be flushed
* prior to committing them to hardware.
*
* DMA Rx:
*
* - If frame buffers exist in cached memory, then the cache must be
* invalidated for the memory region containing the frame prior to data
* access
*
* Both cache invalidate/flush are taken care of in driver code.
*
* <b>Buffer Copying</b>
*
* The driver is designed for a zero-copy buffer scheme. That is, the driver
* will not copy buffers. This avoids potential throughput bottlenecks within
* the driver. If byte copying is required, then the transfer will take longer
* to complete.
*
* <b>Checksum Offloading</b>
*
* The Embedded Processor Block Ethernet can be configured to perform IP, TCP
* and UDP checksum offloading in both receive and transmit directions.
*
* IP packets contain a 16-bit checksum field, which is the 16-bit 1s
* complement of the 1s complement sum of all 16-bit words in the header.
* TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
* 1s complement of the 1s complement sum of all 16-bit words in the header,
* the data and a conceptual pseudo header.
*
* To calculate these checksums in software requires each byte of the packet
* to be read. For TCP and UDP this can use a large amount of processing power.
* Offloading the checksum calculation to hardware can result in significant
* performance improvements.
*
* The transmit checksum offload is only available to use DMA in packet buffer
* mode. This is because the complete frame to be transmitted must be read
* into the packet buffer memory before the checksum can be calculated and
* written to the header at the beginning of the frame.
*
* For IP, TCP or UDP receive checksum offload to be useful, the operating
* system containing the protocol stack must be aware that this offload is
* available so that it can make use of the fact that the hardware has verified
* the checksum.
*
* When receive checksum offloading is enabled in the hardware, the IP header
* checksum is checked, where the packet meets the following criteria:
*
* 1. If present, the VLAN header must be four octets long and the CFI bit
* must not be set.
* 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
* encoding.
* 3. IP v4 packet.
* 4. IP header is of a valid length.
* 5. Good IP header checksum.
* 6. No IP fragmentation.
* 7. TCP or UDP packet.
*
* When an IP, TCP or UDP frame is received, the receive buffer descriptor
* gives an indication if the hardware was able to verify the checksums.
* There is also an indication if the frame had SNAP encapsulation. These
* indication bits will replace the type ID match indication bits when the
* receive checksum offload is enabled.
*
* If any of the checksums are verified incorrect by the hardware, the packet
* is discarded and the appropriate statistics counter incremented.
*
* <b>PHY Interfaces</b>
*
* RGMII 1.3 is the only interface supported.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on
* parameters. Asserts can be turned off on a system-wide basis by defining,
* at compile time, the NDEBUG identifier. By default, asserts are turned on
* and it is recommended that users leave asserts on during development. For
* deployment use -DNDEBUG compiler switch to remove assert code.
*
* @note
*
* Xilinx drivers are typically composed of two parts, one is the driver
* and the other is the adapter. The driver is independent of OS and processor
* and is intended to be highly portable. The adapter is OS-specific and
* facilitates communication between the driver and an OS.
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, or cache
* control must be satisfied bythe layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Earlier it was checking for
* "BdLimit"(passed argument) number of BDs for finding out
* which BDs are successfully processed. Now one more check
* is added. It looks for BDs till the current BD pointer
* reaches HwTail. By doing this processing time is saved.
* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Now start of packet is
* searched for returning the number of BDs processed.
* 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
* registers. Added a new API to set the bust length.
* Added some new hash-defines.
* 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
* removed. It is expected that all BDs are allocated in
* from uncached area.
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* Made changes in example file xemacps_example.h to fix compilation
* issues with iarcc compiler.
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
* 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
* 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
* address in xparameters.h when GMII to RGMII converter
* is present in hw.
* 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
* 1000BASE-X mode export proper values to the xparameters.h
* file. Changes are made in the driver tcl file.
* </pre>
*
****************************************************************************/
#ifndef XEMACPS_H /* prevent circular inclusions */
#define XEMACPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xemacps_hw.h"
#include "xemacps_bd.h"
#include "xemacps_bdring.h"
/************************** Constant Definitions ****************************/
/*
* Device information
*/
#define XEMACPS_DEVICE_NAME "xemacps"
#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
/** @name Configuration options
*
* Device configuration options. See the XEmacPs_SetOptions(),
* XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
* use options.
*
* The default state of the options are noted and are what the device and
* driver will be set to after calling XEmacPs_Reset() or
* XEmacPs_Initialize().
*
* @{
*/
#define XEMACPS_PROMISC_OPTION 0x00000001
/**< Accept all incoming packets.
* This option defaults to disabled (cleared) */
#define XEMACPS_FRAME1536_OPTION 0x00000002
/**< Frame larger than 1516 support for Tx & Rx.
* This option defaults to disabled (cleared) */
#define XEMACPS_VLAN_OPTION 0x00000004
/**< VLAN Rx & Tx frame support.
* This option defaults to disabled (cleared) */
#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010
/**< Enable recognition of flow control frames on Rx
* This option defaults to enabled (set) */
#define XEMACPS_FCS_STRIP_OPTION 0x00000020
/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
* stripped.
* This option defaults to enabled (set) */
#define XEMACPS_FCS_INSERT_OPTION 0x00000040
/**< Generate FCS field and add PAD automatically for outgoing frames.
* This option defaults to disabled (cleared) */
#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080
/**< Enable Length/Type error checking for incoming frames. When this option is
* set, the MAC will filter frames that have a mismatched type/length field
* and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
* types of frames are encountered. When this option is cleared, the MAC will
* allow these types of frames to be received.
*
* This option defaults to disabled (cleared) */
#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100
/**< Enable the transmitter.
* This option defaults to enabled (set) */
#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200
/**< Enable the receiver
* This option defaults to enabled (set) */
#define XEMACPS_BROADCAST_OPTION 0x00000400
/**< Allow reception of the broadcast address
* This option defaults to enabled (set) */
#define XEMACPS_MULTICAST_OPTION 0x00000800
/**< Allows reception of multicast addresses programmed into hash
* This option defaults to disabled (clear) */
#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000
/**< Enable the RX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000
/**< Enable the TX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_DEFAULT_OPTIONS \
(XEMACPS_FLOW_CONTROL_OPTION | \
XEMACPS_FCS_INSERT_OPTION | \
XEMACPS_FCS_STRIP_OPTION | \
XEMACPS_BROADCAST_OPTION | \
XEMACPS_LENTYPE_ERR_OPTION | \
XEMACPS_TRANSMITTER_ENABLE_OPTION | \
XEMACPS_RECEIVER_ENABLE_OPTION | \
XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
XEMACPS_TX_CHKSUM_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
/** @name Callback identifiers
*
* These constants are used as parameters to XEmacPs_SetHandler()
* @{
*/
#define XEMACPS_HANDLER_DMASEND 1
#define XEMACPS_HANDLER_DMARECV 2
#define XEMACPS_HANDLER_ERROR 3
/*@}*/
/* Constants to determine the configuration of the hardware device. They are
* used to allow the driver to verify it can operate with the hardware.
*/
#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
/* The next few constants help upper layers determine the size of memory
* pools used for Ethernet buffers and descriptor lists.
*/
#define XEMACPS_MAC_ADDR_SIZE 6 /* size of Ethernet header */
#define XEMACPS_MTU 1500 /* max MTU size of Ethernet frame */
#define XEMACPS_HDR_SIZE 14 /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
/* DMACR Bust length hash defines */
#define XEMACPS_SINGLE_BURST 1
#define XEMACPS_4BYTE_BURST 4
#define XEMACPS_8BYTE_BURST 8
#define XEMACPS_16BYTE_BURST 16
/**************************** Type Definitions ******************************/
/** @name Typedefs for callback functions
*
* These callbacks are invoked in interrupt context.
* @{
*/
/**
* Callback invoked when frame(s) have been sent or received in interrupt
* driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
*
* @param CallBackRef is user data assigned when the callback was set.
*
* @note
* See xemacps_hw.h for bitmasks definitions and the device hardware spec for
* further information on their meaning.
*
*/
typedef void (*XEmacPs_Handler) (void *CallBackRef);
/**
* Callback when an asynchronous error occurs. To set this callback, invoke
* XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
* paramter.
*
* @param CallBackRef is user data assigned when the callback was set.
* @param Direction defines either receive or transmit error(s) has occurred.
* @param ErrorWord definition varies with Direction
*
*/
typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
u32 ErrorWord);
/*@}*/
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress;/**< Physical base address of IPIF registers */
} XEmacPs_Config;
/**
* The XEmacPs driver instance data. The user is required to allocate a
* structure of this type for every XEmacPs device in the system. A pointer
* to a structure of this type is then passed to the driver API functions.
*/
typedef struct XEmacPs {
XEmacPs_Config Config; /* Hardware configuration */
u32 IsStarted; /* Device is currently started */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Current options word */
XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
XEmacPs_BdRing RxBdRing; /* Receive BD ring */
XEmacPs_Handler SendHandler;
XEmacPs_Handler RecvHandler;
void *SendRef;
void *RecvRef;
XEmacPs_ErrHandler ErrorHandler;
void *ErrorRef;
} XEmacPs;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* Retrieve the Tx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return TxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
/****************************************************************************/
/**
* Retrieve the Rx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return RxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
(Mask & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
(Mask & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* This macro triggers trasmit circuit to send data currently in TX buffer(s).
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* @note
*
* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_Transmit(InstancePtr) \
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the receive channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsRxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) \
? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the transmit channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsTxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) \
? TRUE : FALSE)
/************************** Function Prototypes *****************************/
/*
* Initialization functions in xemacps.c
*/
int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
u32 EffectiveAddress);
void XEmacPs_Start(XEmacPs *InstancePtr);
void XEmacPs_Stop(XEmacPs *InstancePtr);
void XEmacPs_Reset(XEmacPs *InstancePtr);
/*
* Lookup configuration in xemacps_sinit.c
*/
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
/*
* Interrupt-related functions in xemacps_intr.c
* DMA only and FIFO is not supported. This DMA does not support coalescing.
*/
int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPtr, void *CallBackRef);
void XEmacPs_IntrHandler(void *InstancePtr);
/*
* MAC configuration/control functions in XEmacPs_control.c
*/
int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 *PhyDataPtr);
int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 PhyData);
int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
int XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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XilinxProcessorIPLib/drivers/emacps/src/xemacps_bd.h Executable file
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@ -0,0 +1,728 @@
/* $Id: xemacps_bd.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bd.h
*
* This header provides operations to manage buffer descriptors in support
* of scatter-gather DMA.
*
* The API exported by this header defines abstracted macros that allow the
* user to read/write specific BD fields.
*
* <b>Buffer Descriptors</b>
*
* A buffer descriptor (BD) defines a DMA transaction. The macros defined by
* this header file allow access to most fields within a BD to tailor a DMA
* transaction according to user and hardware requirements. See the hardware
* IP DMA spec for more information on BD fields and how they affect transfers.
*
* The XEmacPs_Bd structure defines a BD. The organization of this structure
* is driven mainly by the hardware for use in scatter-gather DMA transfers.
*
* <b>Performance</b>
*
* Limiting I/O to BDs can improve overall performance of the DMA channel.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* </pre>
*
* ***************************************************************************
*/
#ifndef XEMACPS_BD_H /* prevent circular inclusions */
#define XEMACPS_BD_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include <string.h>
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4
/**
* The XEmacPs_Bd is the type for buffer descriptors (BDs).
*/
#define XEMACPS_BD_NUM_WORDS 2
typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Zero out BD fields
*
* @param BdPtr is the BD pointer to operate on
*
* @return Nothing
*
* @note
* C-style signature:
* void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClear(BdPtr) \
memset((BdPtr), 0, sizeof(XEmacPs_Bd))
/****************************************************************************/
/**
*
* Read the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to read
* @param Offset is the word offset to be read
*
* @return The 32-bit value of the field
*
* @note
* C-style signature:
* u32 XEmacPs_BdRead(u32 BaseAddress, u32 Offset)
*
*****************************************************************************/
#define XEmacPs_BdRead(BaseAddress, Offset) \
(*(u32*)((u32)(BaseAddress) + (u32)(Offset)))
/****************************************************************************/
/**
*
* Write the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to write
* @param Offset is the word offset to be written
* @param Data is the 32-bit value to write to the field
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_BdWrite(u32 BaseAddress, u32 Offset, u32 Data)
*
*****************************************************************************/
#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
(*(u32*)((u32)(BaseAddress) + (u32)(Offset)) = (Data))
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note :
*
* C-style signature:
* void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, u32 Addr)
*
*****************************************************************************/
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr)))
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note : Due to some bits are mixed within recevie BD's address field,
* read-modify-write is performed.
*
* C-style signature:
* void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, u32 Addr)
*
*****************************************************************************/
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | (u32)(Addr)))
/*****************************************************************************/
/**
* Set the BD's Status field (word 1).
*
* @param BdPtr is the BD pointer to operate on
* @param Data is the value to write to BD's status field.
*
* @note
* C-style signature:
* void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, u32 Data)
*
*****************************************************************************/
#define XEmacPs_BdSetStatus(BdPtr, Data) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | Data)
/*****************************************************************************/
/**
* Retrieve the BD's Packet DMA transfer status word (word 1).
*
* @param BdPtr is the BD pointer to operate on
*
* @return Status word
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
*
* Due to the BD bit layout differences in transmit and receive. User's
* caution is required.
*****************************************************************************/
#define XEmacPs_BdGetStatus(BdPtr) \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
/*****************************************************************************/
/**
* Get the address (bits 0..31) of the BD's buffer address (word 0)
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
/*****************************************************************************/
/**
* Set transfer length in bytes for the given BD. The length must be set each
* time a BD is submitted to hardware.
*
* @param BdPtr is the BD pointer to operate on
* @param LenBytes is the number of bytes to transfer.
*
* @note
* C-style signature:
* void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
*
*****************************************************************************/
#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
/*****************************************************************************/
/**
* Retrieve the BD length field.
*
* For Tx channels, the returned value is the same as that written with
* XEmacPs_BdSetLength().
*
* For Rx channels, the returned value is the size of the received packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
* XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
*
*****************************************************************************/
#define XEmacPs_BdGetLength(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_LEN_MASK)
/*****************************************************************************/
/**
* Test whether the given BD has been marked as the last BD of a packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsLast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Tell the DMA engine that the given transmit BD marks the end of the current
* packet to be processed.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Tell the DMA engine that the current packet does not end with the given
* BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Set this bit to mark the last descriptor in the receive buffer descriptor
* list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetRxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
XEMACPS_RXBUF_WRAP_MASK))
/*****************************************************************************/
/**
* Determine the wrap bit of the receive BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_WRAP_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit to mark the last descriptor in the transmit buffer
* descriptor list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_WRAP_MASK))
/*****************************************************************************/
/**
* Determine the wrap bit of the transmit BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_WRAP_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/*
* Must clear this bit to enable the MAC to write data to the receive
* buffer. Hardware sets this bit once it has successfully written a frame to
* memory. Once set, software has to clear the bit before the buffer can be
* used again. This macro clear the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearRxNew(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_NEW_MASK))
/*****************************************************************************/
/**
* Determine the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxNew(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_NEW_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Software sets this bit to disable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro sets this bit of transmit BD to avoid
* confusion.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Software clears this bit to enable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro clears this bit of transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Determine the used bit of the transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUsed(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_USED_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to too many retries.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxRetry(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_RETRY_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to data can not be
* feteched in time or buffers are exhausted.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUrun(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_URUN_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to buffer is exhausted
* mid-frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxExh(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_EXH_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit, no CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* u32 XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Clear this bit, CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* u32 XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Determine the broadcast bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxBcast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_BCAST_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the multicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxMultiHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_MULTIHASH_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the unicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxUniHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_UNIHASH_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame is a VLAN Tagged frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxVlan(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_VLAN_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame has Type ID of 8100h and null VLAN
* identifier(Priority tag).
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxPri(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_PRI_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame's Concatenation Format Indicator (CFI) of
* the frames VLANTCI field was set.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxCFI(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_CFI_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the End Of Frame (EOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxEOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the Start Of Frame (SOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxSOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_SOF_MASK) ? TRUE : FALSE)
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

1001
XilinxProcessorIPLib/drivers/emacps/src/xemacps_bdring.c Executable file
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XilinxProcessorIPLib/drivers/emacps/src/xemacps_bdring.h Executable file
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/* $Id: xemacps_bdring.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bdring.h
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
* DMA functionalities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
#define XEMACPS_BDRING_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/**************************** Type Definitions *******************************/
/** This is an internal structure used to maintain the DMA list */
typedef struct {
u32 PhysBaseAddr;/**< Physical address of 1st BD in list */
u32 BaseBdAddr; /**< Virtual address of 1st BD in list */
u32 HighBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
u32 RunState; /**< Flag to indicate DMA is started */
u32 Separation; /**< Number of bytes between the starting address
of adjacent BDs */
XEmacPs_Bd *FreeHead;
/**< First BD in the free group */
XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
XEmacPs_Bd *HwHead; /**< First BD in the work group */
XEmacPs_Bd *HwTail; /**< Last BD in the work group */
XEmacPs_Bd *PostHead;
/**< First BD in the post-work group */
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
unsigned HwCnt; /**< Number of BDs in work group */
unsigned PreCnt; /**< Number of BDs in pre-work group */
unsigned FreeCnt; /**< Number of allocatable BDs in the free group */
unsigned PostCnt; /**< Number of BDs in post-work group */
unsigned AllCnt; /**< Total Number of BDs for channel */
} XEmacPs_BdRing;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many BDs will fit
* in a BD list within the given memory constraints.
*
* The results of this macro can be provided to XEmacPs_BdRingCreate().
*
* @param Alignment specifies what byte alignment the BDs must fall on and
* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
* @param Bytes is the number of bytes to be used to store BDs.
*
* @return Number of BDs that can fit in the given memory area
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
*
******************************************************************************/
#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
(u32)((Bytes) / ((sizeof(XEmacPs_Bd) + ((Alignment)-1)) & \
~((Alignment)-1)))
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many bytes of memory
* is required to contain a given number of BDs at a given alignment.
*
* @param Alignment specifies what byte alignment the BDs must fall on. This
* parameter must be a power of 2 to get an accurate calculation (32, 64,
* 128,...)
* @param NumBd is the number of BDs to calculate memory size requirements for
*
* @return The number of bytes of memory required to create a BD list with the
* given memory constraints.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
*
******************************************************************************/
#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
(u32)((sizeof(XEmacPs_Bd) + ((Alignment)-1)) & \
~((Alignment)-1)) * (NumBd)
/****************************************************************************/
/**
* Return the total number of BDs allocated by this channel with
* XEmacPs_BdRingCreate().
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The total number of BDs allocated for this channel.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
/****************************************************************************/
/**
* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
* processing.
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The number of BDs currently allocatable.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
/****************************************************************************/
/**
* Return the next BD from BdPtr in a list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on.
*
* @return The next BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
(((u32)(BdPtr) >= (RingPtr)->HighBdAddr) ? \
(XEmacPs_Bd*)(RingPtr)->BaseBdAddr : \
(XEmacPs_Bd*)((u32)(BdPtr) + (RingPtr)->Separation))
/****************************************************************************/
/**
* Return the previous BD from BdPtr in the list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on
*
* @return The previous BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
(((u32)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
(XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
(XEmacPs_Bd*)((u32)(BdPtr) - (RingPtr)->Separation))
/************************** Function Prototypes ******************************/
/*
* Scatter gather DMA related functions in xemacps_bdring.c
*/
int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr,
u32 VirtAddr, u32 Alignment, unsigned BdCount);
int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
u8 Direction);
int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
XEmacPs_Bd ** BdSetPtr);
int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
XEmacPs_Bd * BdSetPtr);
int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd,
XEmacPs_Bd * BdSetPtr);
int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd,
XEmacPs_Bd * BdSetPtr);
unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
XEmacPs_Bd ** BdSetPtr);
unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
XEmacPs_Bd ** BdSetPtr);
int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macros */

1075
XilinxProcessorIPLib/drivers/emacps/src/xemacps_control.c Executable file
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XilinxProcessorIPLib/drivers/emacps/src/xemacps_g.c Executable file
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/* $Id: xemacps_g.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_g.c
*
* This file contains a configuration table that specifies the configuration of
* ethernet devices in the system.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.00 hk 22/01/14 Added check for picking second instance
* </pre>
*
* @internal
*
* This configuration table contains entries that are modified at runtime by the
* driver. This table reflects only the hardware configuration of the device.
* This emac configuration table contains software information in addition to
* hardware configuration.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xemacps.h"
/************************** Constant Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Prototypes ******************************/
/*
* The configuration table for emacps device
*/
XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] = {
{
XPAR_XEMACPS_0_DEVICE_ID, /* Device ID */
XPAR_XEMACPS_0_BASEADDR /* Device base address */
},
#ifdef XPAR_XEMACPS_1_DEVICE_ID
{
XPAR_XEMACPS_1_DEVICE_ID, /* Device ID */
XPAR_XEMACPS_1_BASEADDR /* Device base address */
}
#endif
};

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XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.c Executable file
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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_hw.c
*
* This file contains the implementation of the ethernet interface reset sequence
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.05a kpc 28/06/13 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xemacps_hw.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* This function perform the reset sequence to the given emacps interface by
* configuring the appropriate control bits in the emacps specifc registers.
* the emacps reset squence involves the following steps
* Disable all the interuupts
* Clear the status registers
* Disable Rx and Tx engines
* Update the Tx and Rx descriptor queue registers with reset values
* Update the other relevant control registers with reset value
*
* @param BaseAddress of the interface
*
* @return N/A
*
* @note
* This function will not modify the slcr registers that are relavant for
* emacps controller
******************************************************************************/
void XEmacPs_ResetHw(u32 BaseAddr)
{
u32 RegVal = 0;
/* Disable the interrupts */
XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0);
/* Stop transmission,disable loopback and Stop tx and Rx engines */
RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
RegVal &= ~(XEMACPS_NWCTRL_TXEN_MASK|
XEMACPS_NWCTRL_RXEN_MASK|
XEMACPS_NWCTRL_HALTTX_MASK|
XEMACPS_NWCTRL_LOOPEN_MASK);
/* Clear the statistic registers, flush the packets in DPRAM*/
RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
/* Clear the interrupt status */
XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
/* Clear the tx status */
XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,XEMACPS_TXSR_ERROR_MASK|
XEMACPS_TXSR_TXCOMPL_MASK|
XEMACPS_TXSR_TXGO_MASK);
/* Clear the rx status */
XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
XEMACPS_RXSR_FRAMERX_MASK);
/* Clear the tx base address */
XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0);
/* Clear the rx base address */
XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0);
/* Update the network config register with reset value */
XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
/* Update the hash address registers with reset value */
XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0);
XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0);
}

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XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h Executable file
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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_hw.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
* High-level driver functions are defined in xemacps.h.
*
* @note
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release.
* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_HW_H /* prevent circular inclusions */
#define XEMACPS_HW_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
#define XEMACPS_MAX_MAC_ADDR 4 /**< Maxmum number of mac address
supported */
#define XEMACPS_MAX_TYPE_ID 4 /**< Maxmum number of type id supported */
#define XEMACPS_BD_ALIGNMENT 4 /**< Minimum buffer descriptor alignment
on the local bus */
#define XEMACPS_RX_BUF_ALIGNMENT 4 /**< Minimum buffer alignment when using
options that impose alignment
restrictions on the buffer data on
the local bus */
/** @name Direction identifiers
*
* These are used by several functions and callbacks that need
* to specify whether an operation specifies a send or receive channel.
* @{
*/
#define XEMACPS_SEND 1 /**< send direction */
#define XEMACPS_RECV 2 /**< receive direction */
/*@}*/
/** @name MDC clock division
* currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
* @{
*/
typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
} XEmacPs_MdcDiv;
/*@}*/
#define XEMACPS_RX_BUF_SIZE 1536 /**< Specify the receive buffer size in
bytes, 64, 128, ... 10240 */
#define XEMACPS_RX_BUF_UNIT 64 /**< Number of receive buffer bytes as a
unit, this is HW setup */
#define XEMACPS_MAX_RXBD 128 /**< Size of RX buffer descriptor queues */
#define XEMACPS_MAX_TXBD 128 /**< Size of TX buffer descriptor queues */
#define XEMACPS_MAX_HASH_BITS 64 /**< Maximum value for hash bits. 2**6 */
/* Register offset definitions. Unless otherwise noted, register access is
* 32 bit. Names are self explained here.
*/
#define XEMACPS_NWCTRL_OFFSET 0x00000000 /**< Network Control reg */
#define XEMACPS_NWCFG_OFFSET 0x00000004 /**< Network Config reg */
#define XEMACPS_NWSR_OFFSET 0x00000008 /**< Network Status reg */
#define XEMACPS_DMACR_OFFSET 0x00000010 /**< DMA Control reg */
#define XEMACPS_TXSR_OFFSET 0x00000014 /**< TX Status reg */
#define XEMACPS_RXQBASE_OFFSET 0x00000018 /**< RX Q Base address reg */
#define XEMACPS_TXQBASE_OFFSET 0x0000001C /**< TX Q Base address reg */
#define XEMACPS_RXSR_OFFSET 0x00000020 /**< RX Status reg */
#define XEMACPS_ISR_OFFSET 0x00000024 /**< Interrupt Status reg */
#define XEMACPS_IER_OFFSET 0x00000028 /**< Interrupt Enable reg */
#define XEMACPS_IDR_OFFSET 0x0000002C /**< Interrupt Disable reg */
#define XEMACPS_IMR_OFFSET 0x00000030 /**< Interrupt Mask reg */
#define XEMACPS_PHYMNTNC_OFFSET 0x00000034 /**< Phy Maintaince reg */
#define XEMACPS_RXPAUSE_OFFSET 0x00000038 /**< RX Pause Time reg */
#define XEMACPS_TXPAUSE_OFFSET 0x0000003C /**< TX Pause Time reg */
#define XEMACPS_HASHL_OFFSET 0x00000080 /**< Hash Low address reg */
#define XEMACPS_HASHH_OFFSET 0x00000084 /**< Hash High address reg */
#define XEMACPS_LADDR1L_OFFSET 0x00000088 /**< Specific1 addr low reg */
#define XEMACPS_LADDR1H_OFFSET 0x0000008C /**< Specific1 addr high reg */
#define XEMACPS_LADDR2L_OFFSET 0x00000090 /**< Specific2 addr low reg */
#define XEMACPS_LADDR2H_OFFSET 0x00000094 /**< Specific2 addr high reg */
#define XEMACPS_LADDR3L_OFFSET 0x00000098 /**< Specific3 addr low reg */
#define XEMACPS_LADDR3H_OFFSET 0x0000009C /**< Specific3 addr high reg */
#define XEMACPS_LADDR4L_OFFSET 0x000000A0 /**< Specific4 addr low reg */
#define XEMACPS_LADDR4H_OFFSET 0x000000A4 /**< Specific4 addr high reg */
#define XEMACPS_MATCH1_OFFSET 0x000000A8 /**< Type ID1 Match reg */
#define XEMACPS_MATCH2_OFFSET 0x000000AC /**< Type ID2 Match reg */
#define XEMACPS_MATCH3_OFFSET 0x000000B0 /**< Type ID3 Match reg */
#define XEMACPS_MATCH4_OFFSET 0x000000B4 /**< Type ID4 Match reg */
#define XEMACPS_STRETCH_OFFSET 0x000000BC /**< IPG Stretch reg */
#define XEMACPS_OCTTXL_OFFSET 0x00000100 /**< Octects transmitted Low
reg */
#define XEMACPS_OCTTXH_OFFSET 0x00000104 /**< Octects transmitted High
reg */
#define XEMACPS_TXCNT_OFFSET 0x00000108 /**< Error-free Frmaes
transmitted counter */
#define XEMACPS_TXBCCNT_OFFSET 0x0000010C /**< Error-free Broadcast
Frames counter*/
#define XEMACPS_TXMCCNT_OFFSET 0x00000110 /**< Error-free Multicast
Frame counter */
#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114 /**< Pause Frames Transmitted
Counter */
#define XEMACPS_TX64CNT_OFFSET 0x00000118 /**< Error-free 64 byte Frames
Transmitted counter */
#define XEMACPS_TX65CNT_OFFSET 0x0000011C /**< Error-free 65-127 byte
Frames Transmitted
counter */
#define XEMACPS_TX128CNT_OFFSET 0x00000120 /**< Error-free 128-255 byte
Frames Transmitted
counter*/
#define XEMACPS_TX256CNT_OFFSET 0x00000124 /**< Error-free 256-511 byte
Frames transmitted
counter */
#define XEMACPS_TX512CNT_OFFSET 0x00000128 /**< Error-free 512-1023 byte
Frames transmitted
counter */
#define XEMACPS_TX1024CNT_OFFSET 0x0000012C /**< Error-free 1024-1518 byte
Frames transmitted
counter */
#define XEMACPS_TX1519CNT_OFFSET 0x00000130 /**< Error-free larger than
1519 byte Frames
transmitted counter */
#define XEMACPS_TXURUNCNT_OFFSET 0x00000134 /**< TX under run error
counter */
#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138 /**< Single Collision Frame
Counter */
#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013C /**< Multiple Collision Frame
Counter */
#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140 /**< Excessive Collision Frame
Counter */
#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144 /**< Late Collision Frame
Counter */
#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148 /**< Deferred Transmission
Frame Counter */
#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014C /**< Transmit Carrier Sense
Error Counter */
#define XEMACPS_OCTRXL_OFFSET 0x00000150 /**< Octects Received register
Low */
#define XEMACPS_OCTRXH_OFFSET 0x00000154 /**< Octects Received register
High */
#define XEMACPS_RXCNT_OFFSET 0x00000158 /**< Error-free Frames
Received Counter */
#define XEMACPS_RXBROADCNT_OFFSET 0x0000015C /**< Error-free Broadcast
Frames Received Counter */
#define XEMACPS_RXMULTICNT_OFFSET 0x00000160 /**< Error-free Multicast
Frames Received Counter */
#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164 /**< Pause Frames
Received Counter */
#define XEMACPS_RX64CNT_OFFSET 0x00000168 /**< Error-free 64 byte Frames
Received Counter */
#define XEMACPS_RX65CNT_OFFSET 0x0000016C /**< Error-free 65-127 byte
Frames Received Counter */
#define XEMACPS_RX128CNT_OFFSET 0x00000170 /**< Error-free 128-255 byte
Frames Received Counter */
#define XEMACPS_RX256CNT_OFFSET 0x00000174 /**< Error-free 256-512 byte
Frames Received Counter */
#define XEMACPS_RX512CNT_OFFSET 0x00000178 /**< Error-free 512-1023 byte
Frames Received Counter */
#define XEMACPS_RX1024CNT_OFFSET 0x0000017C /**< Error-free 1024-1518 byte
Frames Received Counter */
#define XEMACPS_RX1519CNT_OFFSET 0x00000180 /**< Error-free 1519-max byte
Frames Received Counter */
#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184 /**< Undersize Frames Received
Counter */
#define XEMACPS_RXOVRCNT_OFFSET 0x00000188 /**< Oversize Frames Received
Counter */
#define XEMACPS_RXJABCNT_OFFSET 0x0000018C /**< Jabbers Received
Counter */
#define XEMACPS_RXFCSCNT_OFFSET 0x00000190 /**< Frame Check Sequence
Error Counter */
#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194 /**< Length Field Error
Counter */
#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198 /**< Symbol Error Counter */
#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019C /**< Alignment Error Counter */
#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0 /**< Receive Resource Error
Counter */
#define XEMACPS_RXORCNT_OFFSET 0x000001A4 /**< Receive Overrun Counter */
#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8 /**< IP header Checksum Error
Counter */
#define XEMACPS_RXTCPCCNT_OFFSET 0x000001AC /**< TCP Checksum Error
Counter */
#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0 /**< UDP Checksum Error
Counter */
#define XEMACPS_LAST_OFFSET 0x000001B4 /**< Last statistic counter
offset, for clearing */
#define XEMACPS_1588_SEC_OFFSET 0x000001D0 /**< 1588 second counter */
#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4 /**< 1588 nanosecond counter */
#define XEMACPS_1588_ADJ_OFFSET 0x000001D8 /**< 1588 nanosecond
adjustment counter */
#define XEMACPS_1588_INC_OFFSET 0x000001DC /**< 1588 nanosecond
increment counter */
#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0 /**< 1588 PTP transmit second
counter */
#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4 /**< 1588 PTP transmit
nanosecond counter */
#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8 /**< 1588 PTP receive second
counter */
#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001EC /**< 1588 PTP receive
nanosecond counter */
#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0 /**< 1588 PTP peer transmit
second counter */
#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4 /**< 1588 PTP peer transmit
nanosecond counter */
#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8 /**< 1588 PTP peer receive
second counter */
#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FC /**< 1588 PTP peer receive
nanosecond counter */
/* Define some bit positions for registers. */
/** @name network control register bit definitions
* @{
*/
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000 /**< Flush a packet from
Rx SRAM */
#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800 /**< Transmit zero quantum
pause frame */
#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800 /**< Transmit pause frame */
#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400 /**< Halt transmission
after current frame */
#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200 /**< Start tx (tx_go) */
#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080 /**< Enable writing to
stat counters */
#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040 /**< Increment statistic
registers */
#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020 /**< Clear statistic
registers */
#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010 /**< Enable MDIO port */
#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008 /**< Enable transmit */
#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004 /**< Enable receive */
#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002 /**< local loopback */
/*@}*/
/** @name network configuration register bit definitions
* @{
*/
#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000 /**< disable rejection of
non-standard preamble */
#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000 /**< enable transmit IPG */
#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000 /**< disable rejection of
FCS error */
#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000 /**< RX half duplex */
#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000 /**< enable RX checksum
offload */
#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000 /**< Do not copy pause
Frames to memory */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18 /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000 /**< MDC Mask PCLK divisor */
#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000 /**< Discard FCS from
received frames */
#define XEMACPS_NWCFG_LENGTHERRDSCRD_MASK 0x00010000
/**< RX length error discard */
#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000 /**< RX buffer offset */
#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000 /**< Enable pause RX */
#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000 /**< Retry test */
#define XEMACPS_NWCFG_EXTADDRMATCHEN_MASK 0x00000200
/**< External address match enable */
#define XEMACPS_NWCFG_1000_MASK 0x00000400 /**< 1000 Mbps */
#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100 /**< Enable 1536 byte
frames reception */
#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080 /**< Receive unicast hash
frames */
#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040 /**< Receive multicast hash
frames */
#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020 /**< Do not receive
broadcast frames */
#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010 /**< Copy all frames */
#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008 /**< Jumbo frames */
#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004 /**< Receive only VLAN
frames */
#define XEMACPS_NWCFG_FDEN_MASK 0x00000002 /**< full duplex */
#define XEMACPS_NWCFG_100_MASK 0x00000001 /**< 100 Mbps */
#define XEMACPS_NWCFG_RESET_MASK 0x00080000 /**< reset value */
/*@}*/
/** @name network status register bit definitaions
* @{
*/
#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004 /**< PHY management idle */
#define XEMACPS_NWSR_MDIO_MASK 0x00000002 /**< Status of mdio_in */
/*@}*/
/** @name MAC address register word 1 mask
* @{
*/
#define XEMACPS_LADDR_MACH_MASK 0x0000FFFF /**< Address bits[47:32]
bit[31:0] are in BOTTOM */
/*@}*/
/** @name DMA control register bit definitions
* @{
*/
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000 /**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT 16 /**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800 /**< enable/disable TX
checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400 /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300 /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080 /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001F /**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001 /**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004 /**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008 /**< 8 bytes AHB bursts */
#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010 /**< 16 bytes AHB bursts */
/*@}*/
/** @name transmit status register bit definitions
* @{
*/
#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100 /**< Transmit hresp not OK */
#define XEMACPS_TXSR_URUN_MASK 0x00000040 /**< Transmit underrun */
#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020 /**< Transmit completed OK */
#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010 /**< Transmit buffs exhausted
mid frame */
#define XEMACPS_TXSR_TXGO_MASK 0x00000008 /**< Status of go flag */
#define XEMACPS_TXSR_RXOVR_MASK 0x00000004 /**< Retry limit exceeded */
#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002 /**< Collision tx frame */
#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001 /**< TX buffer used bit set */
#define XEMACPS_TXSR_ERROR_MASK (XEMACPS_TXSR_HRESPNOK_MASK | \
XEMACPS_TXSR_URUN_MASK | \
XEMACPS_TXSR_BUFEXH_MASK | \
XEMACPS_TXSR_RXOVR_MASK | \
XEMACPS_TXSR_FRAMERX_MASK | \
XEMACPS_TXSR_USEDREAD_MASK)
/*@}*/
/**
* @name receive status register bit definitions
* @{
*/
#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008 /**< Receive hresp not OK */
#define XEMACPS_RXSR_RXOVR_MASK 0x00000004 /**< Receive overrun */
#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002 /**< Frame received OK */
#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001 /**< RX buffer used bit set */
#define XEMACPS_RXSR_ERROR_MASK (XEMACPS_RXSR_HRESPNOK_MASK | \
XEMACPS_RXSR_RXOVR_MASK | \
XEMACPS_RXSR_BUFFNA_MASK)
/*@}*/
/**
* @name interrupts bit definitions
* Bits definitions are same in XEMACPS_ISR_OFFSET,
* XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
* @{
*/
#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000 /**< PTP Psync transmitted */
#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000 /**< PTP Pdelay_req
transmitted */
#define XEMACPS_IXR_PTPSTX_MASK 0x00800000 /**< PTP Sync transmitted */
#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000 /**< PTP Delay_req transmitted
*/
#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000 /**< PTP Psync received */
#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000 /**< PTP Pdelay_req received */
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000 /**< PTP Sync received */
#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000 /**< PTP Delay_req received */
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000 /**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000 /**< Pause time has reached
zero */
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000 /**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800 /**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK 0x00000400 /**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080 /**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK 0x00000040 /**< Transmit err occurred or
no buffers*/
#define XEMACPS_IXR_RETRY_MASK 0x00000020 /**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK 0x00000010 /**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK 0x00000008 /**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK 0x00000004 /**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002 /**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK 0x00000001 /**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK 0x00007FFF /**< Everything! */
#define XEMACPS_IXR_TX_ERR_MASK (XEMACPS_IXR_TXEXH_MASK | \
XEMACPS_IXR_RETRY_MASK | \
XEMACPS_IXR_URUN_MASK | \
XEMACPS_IXR_TXUSED_MASK)
#define XEMACPS_IXR_RX_ERR_MASK (XEMACPS_IXR_HRESPNOK_MASK | \
XEMACPS_IXR_RXUSED_MASK | \
XEMACPS_IXR_RXOVR_MASK)
/*@}*/
/** @name PHY Maintenance bit definitions
* @{
*/
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000 /**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000 /**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000 /**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000 /**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000 /**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFF /**< data bits */
#define XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK 23 /**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK 18 /**< Shift bits for PHREG */
/*@}*/
/* Transmit buffer descriptor status words offset
* @{
*/
#define XEMACPS_BD_ADDR_OFFSET 0x00000000 /**< word 0/addr of BDs */
#define XEMACPS_BD_STAT_OFFSET 0x00000004 /**< word 1/status of BDs */
/*
* @}
*/
/* Transmit buffer descriptor status words bit positions.
* Transmit buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit address pointing to the location of
* the transmit data.
* The following register - word1, consists of various information to control
* the XEmacPs transmit process. After transmit, this is updated with status
* information, whether the frame was transmitted OK or why it had failed.
* @{
*/
#define XEMACPS_TXBUF_USED_MASK 0x80000000 /**< Used bit. */
#define XEMACPS_TXBUF_WRAP_MASK 0x40000000 /**< Wrap bit, last descriptor */
#define XEMACPS_TXBUF_RETRY_MASK 0x20000000 /**< Retry limit exceeded */
#define XEMACPS_TXBUF_URUN_MASK 0x10000000 /**< Transmit underrun occurred */
#define XEMACPS_TXBUF_EXH_MASK 0x08000000 /**< Buffers exhausted */
#define XEMACPS_TXBUF_TCP_MASK 0x04000000 /**< Late collision. */
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000 /**< No CRC */
#define XEMACPS_TXBUF_LAST_MASK 0x00008000 /**< Last buffer */
#define XEMACPS_TXBUF_LEN_MASK 0x00003FFF /**< Mask for length field */
/*
* @}
*/
/* Receive buffer descriptor status words bit positions.
* Receive buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit word aligned address pointing to the
* address of the buffer. The lower two bits make up the wrap bit indicating
* the last descriptor and the ownership bit to indicate it has been used by
* the XEmacPs.
* The following register - word1, contains status information regarding why
* the frame was received (the filter match condition) as well as other
* useful info.
* @{
*/
#define XEMACPS_RXBUF_BCAST_MASK 0x80000000 /**< Broadcast frame */
#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000 /**< Multicast hashed frame */
#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000 /**< Unicast hashed frame */
#define XEMACPS_RXBUF_EXH_MASK 0x08000000 /**< buffer exhausted */
#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000 /**< Specific address
matched */
#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000 /**< Type ID matched */
#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000 /**< ID matched mask */
#define XEMACPS_RXBUF_VLAN_MASK 0x00200000 /**< VLAN tagged */
#define XEMACPS_RXBUF_PRI_MASK 0x00100000 /**< Priority tagged */
#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000 /**< Vlan priority */
#define XEMACPS_RXBUF_CFI_MASK 0x00010000 /**< CFI frame */
#define XEMACPS_RXBUF_EOF_MASK 0x00008000 /**< End of frame. */
#define XEMACPS_RXBUF_SOF_MASK 0x00004000 /**< Start of frame. */
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFF /**< Mask for length field */
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002 /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK 0x00000001 /**< Used bit.. */
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFC /**< Mask for address */
/*
* @}
*/
/*
* Define appropriate I/O access method to mempry mapped I/O or other
* intarfce if necessary.
*/
#define XEmacPs_In32 Xil_In32
#define XEmacPs_Out32 Xil_Out32
/****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
XEmacPs_In32((BaseAddress) + (RegOffset))
/****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
* u32 Data)
*
*****************************************************************************/
#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
XEmacPs_Out32((BaseAddress) + (RegOffset), (Data))
/************************** Function Prototypes *****************************/
/*
* Perform reset operation to the emacps interface
*/
void XEmacPs_ResetHw(u32 BaseAddr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c Executable file
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@ -0,0 +1,220 @@
/* $Id: xemacps_intr.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_intr.c
*
* Functions in this file implement general purpose interrupt processing related
* functionality. See xemacps.h for a detailed description of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* </pre>
******************************************************************************/
/***************************** Include Files *********************************/
#include "xemacps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* Install an asynchronious handler function for the given HandlerType:
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param HandlerType indicates what interrupt handler type is.
* XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
* XEMACPS_HANDLER_ERROR.
* @param FuncPtr is the pointer to the callback function
* @param CallBackRef is the upper layer callback reference passed back when
* when the callback function is invoked.
*
* @return
*
* None.
*
* @note
* There is no assert on the CallBackRef since the driver doesn't know what
* it is.
*
*****************************************************************************/
int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPtr, void *CallBackRef)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(FuncPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
switch (HandlerType) {
case XEMACPS_HANDLER_DMASEND:
InstancePtr->SendHandler = (XEmacPs_Handler) FuncPtr;
InstancePtr->SendRef = CallBackRef;
break;
case XEMACPS_HANDLER_DMARECV:
InstancePtr->RecvHandler = (XEmacPs_Handler) FuncPtr;
InstancePtr->RecvRef = CallBackRef;
break;
case XEMACPS_HANDLER_ERROR:
InstancePtr->ErrorHandler = (XEmacPs_ErrHandler) FuncPtr;
InstancePtr->ErrorRef = CallBackRef;
break;
default:
return (XST_INVALID_PARAM);
}
return (XST_SUCCESS);
}
/*****************************************************************************/
/**
* Master interrupt handler for EMAC driver. This routine will query the
* status of the device, bump statistics, and invoke user callbacks.
*
* This routine must be connected to an interrupt controller using OS/BSP
* specific methods.
*
* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
* interrupt.
*
******************************************************************************/
void XEmacPs_IntrHandler(void *XEmacPsPtr)
{
u32 RegISR;
u32 RegSR;
u32 RegCtrl;
XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* This ISR will try to handle as many interrupts as it can in a single
* call. However, in most of the places where the user's error handler
* is called, this ISR exits because it is expected that the user will
* reset the device in nearly all instances.
*/
RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_ISR_OFFSET);
/* Clear the interrupt status register */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
RegISR);
/* Receive complete interrupt */
if (RegISR & (XEMACPS_IXR_FRAMERX_MASK)) {
/* Clear RX status register RX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET,
XEMACPS_RXSR_FRAMERX_MASK |
XEMACPS_RXSR_BUFFNA_MASK);
InstancePtr->RecvHandler(InstancePtr->RecvRef);
}
/* Transmit complete interrupt */
if (RegISR & (XEMACPS_IXR_TXCOMPL_MASK)) {
/* Clear TX status register TX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET,
XEMACPS_TXSR_TXCOMPL_MASK |
XEMACPS_TXSR_USEDREAD_MASK);
InstancePtr->SendHandler(InstancePtr->SendRef);
}
/* Receive error conditions interrupt */
if (RegISR & (XEMACPS_IXR_RX_ERR_MASK)) {
/* Clear RX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET, RegSR);
/* Fix for CR # 692702. Write to bit 18 of net_ctrl
* register to flush a packet out of Rx SRAM upon
* an error for receive buffer not available. */
if (RegISR & XEMACPS_IXR_RXUSED_MASK) {
RegCtrl =
XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
RegCtrl |= XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, RegCtrl);
}
InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_RECV,
RegSR);
}
/* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
* will be asserted the same time.
* Have to distinguish this bit to handle the real error condition.
*/
/* Transmit error conditions interrupt */
if (RegISR & (XEMACPS_IXR_TX_ERR_MASK) &&
!(RegISR & (XEMACPS_IXR_TXCOMPL_MASK))) {
/* Clear TX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET, RegSR);
InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
RegSR);
}
}

93
XilinxProcessorIPLib/drivers/emacps/src/xemacps_sinit.c Executable file
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@ -0,0 +1,93 @@
/* $Id: xemacps_sinit.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_sinit.c
*
* This file contains lookup method by device ID when success, it returns
* pointer to config table to be used to initialize the device.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 New
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xemacps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* contains the configuration info for each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return
* A pointer to the configuration table entry corresponding to the given
* device ID, or NULL if no match is found.
*
******************************************************************************/
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
{
extern XEmacPs_Config XEmacPs_ConfigTable[];
XEmacPs_Config *CfgPtr = NULL;
int i;
for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) {
if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
CfgPtr = &XEmacPs_ConfigTable[i];
break;
}
}
return (CfgPtr);
}