stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

bsp: a53: change in boot.s to include more memory attributes

Browse source 
This patch inclues memory attributes like device memory and
write through cacheable memory attributes to memory
attribute index register in boot.S

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi   <anirudh@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2015-07-27 18:56:15 +05:30 • committed by Nava kishore Manne
parent 59de0ec3be
commit 39f94f2135
1 changed files with 3 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
lib/bsp/standalone/src/cortexa53/64bit/gcc/boot.S
View file

@ -184,8 +184,10 @@ OKToRun:
* 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
* 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
* 2 = b00000000 = Device-nGnRnE
* 3 = b00000100 = Device-nGnRE
* 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
**********************************************/
ldr x1, =0x000000000000FF44
ldr x1, =0x000000BB0400FF44
msr MAIR_EL3, x1
/**********************************************