dptx: Updated Doxygen documentation.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>

XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html

@@ -95,8 +95,7 @@ Here is a list of all class members with links to the classes they belong to:
 : <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html#34af1751495e24548fc7b5af4c6255f4">XDptx_SbMsgLinkAddressReplyDeviceInfo</a>, <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html#b080e020948e5ebe9180c89b761c34fd">XDptx_SbMsgLinkAddressReplyPortDetail</a>, <a class="el" href="struct_x_dptx___topology_node.html#31f91fdac9d2223df8dabb36cd3d47dc">XDptx_TopologyNode</a></ul>
 <h3><a class="anchor" name="index_h">- h -</a></h3><ul>
 <li>HasRedriverInPath
-: <a class="el" href="struct_x_dptx___board_char.html#f0c1cc4e8db9d5eea7d122ae97d72898">XDptx_BoardChar</a><li>HClkTotal
+: <a class="el" href="struct_x_dptx___board_char.html#f0c1cc4e8db9d5eea7d122ae97d72898">XDptx_BoardChar</a><li>Header
-: <a class="el" href="struct_x_dptx___main_stream_attributes.html#6dd2f67ac69e011b4aca69e5c8993c96">XDptx_MainStreamAttributes</a><li>Header
 : <a class="el" href="struct_x_dptx___sideband_msg.html#8b8fb5d20e109c82daf16a8ea2bcb4bd">XDptx_SidebandMsg</a><li>HpdEventCallbackRef
 : <a class="el" href="struct_x_dptx.html#71e5740080d8cced1992a1ab73ccc0f2">XDptx</a><li>HpdEventHandler
 : <a class="el" href="struct_x_dptx.html#5db934dcfed963ee3fba51bfe087a1f7">XDptx</a><li>HpdPulseCallbackRef
@@ -157,7 +156,8 @@ Here is a list of all class members with links to the classes they belong to:
 : <a class="el" href="struct_x_dptx___link_config.html#234eff85460c7b422e117549f9121da7">XDptx_LinkConfig</a><li>PayloadDataWidth
 : <a class="el" href="struct_x_dptx___config.html#929b4359944d85d520b4c14634ae392a">XDptx_Config</a><li>PeerDeviceType
 : <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html#7246cd0cdf0c7c33cf1904aebb6da8dc">XDptx_SbMsgLinkAddressReplyPortDetail</a><li>PeLevel
-: <a class="el" href="struct_x_dptx___link_config.html#b7eb55816a62936fdbe42a8ea8a0ae79">XDptx_LinkConfig</a><li>PortDetails
+: <a class="el" href="struct_x_dptx___link_config.html#b7eb55816a62936fdbe42a8ea8a0ae79">XDptx_LinkConfig</a><li>PixelClockHz
+: <a class="el" href="struct_x_dptx___main_stream_attributes.html#fd9713a9d0069b52c41f2badea942920">XDptx_MainStreamAttributes</a><li>PortDetails
 : <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html#2fc2252e0e60c4635f548b986759429a">XDptx_SbMsgLinkAddressReplyDeviceInfo</a><li>PortNum
 : <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html#be3cce0570a9d5f0424196c2233c136d">XDptx_SbMsgLinkAddressReplyPortDetail</a></ul>
 <h3><a class="anchor" name="index_q">- q -</a></h3><ul>
@@ -195,11 +195,10 @@ Here is a list of all class members with links to the classes they belong to:
 : <a class="el" href="struct_x_dptx.html#fd631f0f90f6cdbbba8848ca5a216ba8">XDptx</a><li>UserTimerWaitUs
 : <a class="el" href="struct_x_dptx.html#fd2cbc84e307d853f48f19d9d8aedc06">XDptx</a></ul>
 <h3><a class="anchor" name="index_v">- v -</a></h3><ul>
-<li>VClkTotal
+<li>VsLevel
-: <a class="el" href="struct_x_dptx___main_stream_attributes.html#862e898079c25c530cc796330de0ba1a">XDptx_MainStreamAttributes</a><li>VsLevel
 : <a class="el" href="struct_x_dptx___link_config.html#bb910ca8ad553f5c6d80071265fb3584">XDptx_LinkConfig</a><li>VStart
 : <a class="el" href="struct_x_dptx___main_stream_attributes.html#b37f3817a1bda33892d2dd8a2a6bcc23">XDptx_MainStreamAttributes</a><li>Vtm
-: <a class="el" href="struct_x_dptx___main_stream_attributes.html#2e5f919bab78b5937a78d9855b545a24">XDptx_MainStreamAttributes</a></ul>
+: <a class="el" href="struct_x_dptx___main_stream_attributes.html#f4c5b131d48d852703dc31c3f3b6dcde">XDptx_MainStreamAttributes</a></ul>
 <h3><a class="anchor" name="index_y">- y -</a></h3><ul>
 <li>YCbCrColorimetry
 : <a class="el" href="struct_x_dptx___main_stream_attributes.html#3ec3d85682eb90198377b0fbd92d4df2">XDptx_MainStreamAttributes</a><li>YCrCbEn

XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions_vars.html

@@ -95,8 +95,7 @@
 : <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html#34af1751495e24548fc7b5af4c6255f4">XDptx_SbMsgLinkAddressReplyDeviceInfo</a>, <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html#b080e020948e5ebe9180c89b761c34fd">XDptx_SbMsgLinkAddressReplyPortDetail</a>, <a class="el" href="struct_x_dptx___topology_node.html#31f91fdac9d2223df8dabb36cd3d47dc">XDptx_TopologyNode</a></ul>
 <h3><a class="anchor" name="index_h">- h -</a></h3><ul>
 <li>HasRedriverInPath
-: <a class="el" href="struct_x_dptx___board_char.html#f0c1cc4e8db9d5eea7d122ae97d72898">XDptx_BoardChar</a><li>HClkTotal
+: <a class="el" href="struct_x_dptx___board_char.html#f0c1cc4e8db9d5eea7d122ae97d72898">XDptx_BoardChar</a><li>Header
-: <a class="el" href="struct_x_dptx___main_stream_attributes.html#6dd2f67ac69e011b4aca69e5c8993c96">XDptx_MainStreamAttributes</a><li>Header
 : <a class="el" href="struct_x_dptx___sideband_msg.html#8b8fb5d20e109c82daf16a8ea2bcb4bd">XDptx_SidebandMsg</a><li>HpdEventCallbackRef
 : <a class="el" href="struct_x_dptx.html#71e5740080d8cced1992a1ab73ccc0f2">XDptx</a><li>HpdEventHandler
 : <a class="el" href="struct_x_dptx.html#5db934dcfed963ee3fba51bfe087a1f7">XDptx</a><li>HpdPulseCallbackRef
@@ -157,7 +156,8 @@
 : <a class="el" href="struct_x_dptx___link_config.html#234eff85460c7b422e117549f9121da7">XDptx_LinkConfig</a><li>PayloadDataWidth
 : <a class="el" href="struct_x_dptx___config.html#929b4359944d85d520b4c14634ae392a">XDptx_Config</a><li>PeerDeviceType
 : <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html#7246cd0cdf0c7c33cf1904aebb6da8dc">XDptx_SbMsgLinkAddressReplyPortDetail</a><li>PeLevel
-: <a class="el" href="struct_x_dptx___link_config.html#b7eb55816a62936fdbe42a8ea8a0ae79">XDptx_LinkConfig</a><li>PortDetails
+: <a class="el" href="struct_x_dptx___link_config.html#b7eb55816a62936fdbe42a8ea8a0ae79">XDptx_LinkConfig</a><li>PixelClockHz
+: <a class="el" href="struct_x_dptx___main_stream_attributes.html#fd9713a9d0069b52c41f2badea942920">XDptx_MainStreamAttributes</a><li>PortDetails
 : <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_device_info.html#2fc2252e0e60c4635f548b986759429a">XDptx_SbMsgLinkAddressReplyDeviceInfo</a><li>PortNum
 : <a class="el" href="struct_x_dptx___sb_msg_link_address_reply_port_detail.html#be3cce0570a9d5f0424196c2233c136d">XDptx_SbMsgLinkAddressReplyPortDetail</a></ul>
 <h3><a class="anchor" name="index_q">- q -</a></h3><ul>
@@ -195,11 +195,10 @@
 : <a class="el" href="struct_x_dptx.html#fd631f0f90f6cdbbba8848ca5a216ba8">XDptx</a><li>UserTimerWaitUs
 : <a class="el" href="struct_x_dptx.html#fd2cbc84e307d853f48f19d9d8aedc06">XDptx</a></ul>
 <h3><a class="anchor" name="index_v">- v -</a></h3><ul>
-<li>VClkTotal
+<li>VsLevel
-: <a class="el" href="struct_x_dptx___main_stream_attributes.html#862e898079c25c530cc796330de0ba1a">XDptx_MainStreamAttributes</a><li>VsLevel
 : <a class="el" href="struct_x_dptx___link_config.html#bb910ca8ad553f5c6d80071265fb3584">XDptx_LinkConfig</a><li>VStart
 : <a class="el" href="struct_x_dptx___main_stream_attributes.html#b37f3817a1bda33892d2dd8a2a6bcc23">XDptx_MainStreamAttributes</a><li>Vtm
-: <a class="el" href="struct_x_dptx___main_stream_attributes.html#2e5f919bab78b5937a78d9855b545a24">XDptx_MainStreamAttributes</a></ul>
+: <a class="el" href="struct_x_dptx___main_stream_attributes.html#f4c5b131d48d852703dc31c3f3b6dcde">XDptx_MainStreamAttributes</a></ul>
 <h3><a class="anchor" name="index_y">- y -</a></h3><ul>
 <li>YCbCrColorimetry
 : <a class="el" href="struct_x_dptx___main_stream_attributes.html#3ec3d85682eb90198377b0fbd92d4df2">XDptx_MainStreamAttributes</a><li>YCrCbEn

XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x78.html

@@ -86,7 +86,7 @@ Here is a list of all file members with links to the files they belong to:
 : <a class="el" href="xdptx__spm_8c.html#5dba8599ab68d0766e120119a6c6b83a">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#5dba8599ab68d0766e120119a6c6b83a">xdptx.h</a><li>XDptx_CfgMsaUseCustom()
 : <a class="el" href="xdptx__spm_8c.html#b04d6d38ab65f7d6d5b4734eedf9b020">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#b04d6d38ab65f7d6d5b4734eedf9b020">xdptx.h</a><li>XDptx_CfgMsaUseEdidPreferredTiming()
 : <a class="el" href="xdptx__spm_8c.html#b4778897734128bf467047a90066c922">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#b4778897734128bf467047a90066c922">xdptx.h</a><li>XDptx_CfgMsaUseStandardVideoMode()
-: <a class="el" href="xdptx__spm_8c.html#8f5a8d3f316f519145ecd9a94bf27ce8">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#8f5a8d3f316f519145ecd9a94bf27ce8">xdptx.h</a><li>XDptx_CfgTxPeLevel()
+: <a class="el" href="xdptx__spm_8c.html#79a528fe544595d48fbf1d2438f0304d">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#79a528fe544595d48fbf1d2438f0304d">xdptx.h</a><li>XDptx_CfgTxPeLevel()
 : <a class="el" href="xdptx_8h.html#eda4459fe23e2926575401293fa9ee75">xdptx.h</a>, <a class="el" href="xdptx_8c.html#eda4459fe23e2926575401293fa9ee75">xdptx.c</a><li>XDptx_CfgTxVsLevel()
 : <a class="el" href="xdptx_8h.html#1c2e557e06c47e2f6d3b6f072a462d03">xdptx.h</a>, <a class="el" href="xdptx_8c.html#1c2e557e06c47e2f6d3b6f072a462d03">xdptx.c</a><li>XDptx_CfgTxVsOffset()
 : <a class="el" href="xdptx_8h.html#74b044b7d09f44e887d9a5c61b6dfcdb">xdptx.h</a>, <a class="el" href="xdptx_8c.html#74b044b7d09f44e887d9a5c61b6dfcdb">xdptx.c</a><li>XDptx_CheckLinkStatus()

XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_func.html

@@ -54,7 +54,7 @@
 : <a class="el" href="xdptx__spm_8c.html#5dba8599ab68d0766e120119a6c6b83a">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#5dba8599ab68d0766e120119a6c6b83a">xdptx.h</a><li>XDptx_CfgMsaUseCustom()
 : <a class="el" href="xdptx__spm_8c.html#b04d6d38ab65f7d6d5b4734eedf9b020">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#b04d6d38ab65f7d6d5b4734eedf9b020">xdptx.h</a><li>XDptx_CfgMsaUseEdidPreferredTiming()
 : <a class="el" href="xdptx__spm_8c.html#b4778897734128bf467047a90066c922">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#b4778897734128bf467047a90066c922">xdptx.h</a><li>XDptx_CfgMsaUseStandardVideoMode()
-: <a class="el" href="xdptx__spm_8c.html#8f5a8d3f316f519145ecd9a94bf27ce8">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#8f5a8d3f316f519145ecd9a94bf27ce8">xdptx.h</a><li>XDptx_CfgTxPeLevel()
+: <a class="el" href="xdptx__spm_8c.html#79a528fe544595d48fbf1d2438f0304d">xdptx_spm.c</a>, <a class="el" href="xdptx_8h.html#79a528fe544595d48fbf1d2438f0304d">xdptx.h</a><li>XDptx_CfgTxPeLevel()
 : <a class="el" href="xdptx_8h.html#eda4459fe23e2926575401293fa9ee75">xdptx.h</a>, <a class="el" href="xdptx_8c.html#eda4459fe23e2926575401293fa9ee75">xdptx.c</a><li>XDptx_CfgTxVsLevel()
 : <a class="el" href="xdptx_8h.html#1c2e557e06c47e2f6d3b6f072a462d03">xdptx.h</a>, <a class="el" href="xdptx_8c.html#1c2e557e06c47e2f6d3b6f072a462d03">xdptx.c</a><li>XDptx_CfgTxVsOffset()
 : <a class="el" href="xdptx_8h.html#74b044b7d09f44e887d9a5c61b6dfcdb">xdptx.h</a>, <a class="el" href="xdptx_8c.html#74b044b7d09f44e887d9a5c61b6dfcdb">xdptx.c</a><li>XDptx_CheckLinkStatus()

XilinxProcessorIPLib/drivers/dptx/doc/html/api/index.html

@@ -2,7 +2,7 @@
 <head>
    <meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
 <title>
-   Main Page
+   dptx v3_0
 </title>
 <link href="$DriverApiDocsCssPath" rel="stylesheet" type="text/css">
 </head>
@@ -16,6 +16,71 @@
     <li><a href="annotated.html"><span>Classes</span></a></li>
     <li><a href="files.html"><span>Files</span></a></li>
   </ul></div>
-<h1></h1>
+<h1>dptx v3_0</h1>
 <p>
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the DisplayPort 1.2a specification.<p>
+The Xilinx DisplayPort soft IP supports the following features:<ul>
+<li>1, 2, or 4 lanes.</li><li>A link rate of 1.62, 2.70, or 5.40Gbps per lane.</li><li>1, 2, or 4 pixel-wide video interfaces.</li><li>RGB and YCbCr color space.</li><li>Up to 16 bits per component.</li><li>Up to 4Kx2K monitor resolution.</li><li>Auto lane rate and width negotiation.</li><li>I2C over a 1Mb/s AUX channel.</li><li>Secondary channel audio support (2 channels).</li><li>4 independent video multi-streams.</li></ul>
+<p>
+The Xilinx DisplayPort soft IP does not support the following features:<ul>
+<li>The automated test feature.</li><li>Audio (3-8 channel).</li><li>FAUX.</li><li>Bridging function.</li><li>MST audio.</li><li>eDP optional features.</li><li>iDP.</li><li>GTC.</li></ul>
+<p>
+<b>DisplayPort overview</b><p>
+A DisplayPort link consists of:<ul>
+<li>A unidirectional main link which is used to transport isochronous data streams such as video and audio. The main link may use 1, 2, or 4 lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link needs to be trained prior to sending streams.</li><li>An auxiliary (AUX) channel is a 1MBps bidirectional channel used for link training, link management, and device control.</li><li>A hot-plug-detect (HPD) signal line is used to determine whether a DisplayPort connection exists between the DisplayPort TX connector and an RX device. It is serves as an interrupt request by the RX device.</li></ul>
+<p>
+<b>Driver description</b><p>
+The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort TX soft IP, communicate and control an RX device/sink monitor over the AUX channel, and to initialize and transmit data streams over the main link.<p>
+This driver implements link layer functionality: a Link Policy Maker (LPM) and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.<ul>
+<li>The LPM manages the main link and is responsible for keeping the link synchronized. It will establish a link with a downstream RX device by undergoing a link training sequence which consists of:<ul>
+<li>Clock recovery: The clock needs to be recovered and PLLs need to be locked for all lanes.</li><li>Channel equalization: All lanes need to achieve channel equalization and and symbol lock, as well as for interlane alignment to take place.</li></ul>
+</li><li>The SPM manages transportation of an isochronous stream. That is, it will initialize and maintain a video stream, establish a virtual channel to a sink monitor, and transmit the stream.</li></ul>
+<p>
+Using AUX transactions to read/write from/to the sink's DisplayPort Configuration Data (DPCD) address space, the LPM obtains the link capabilities, obtains link configuration and link and sink status, and configures and controls the link and sink. The main link is trained this way.<p>
+I2C-over-AUX transactions are used to obtain the sink's Extended Display Identification Data (EDID) which give information on the display capabilities of the monitor. The SPM may use this information to determine what available screen resolutions and video timing are possible.<p>
+<b>Device configuration</b><p>
+The device can be configured in various ways during the FPGA implementation process. Configuration parameters are stored in the xdptx_g.c file which is generated when compiling the board support package (BSP). A table is defined where each entry contains configuration information for the DisplayPort instances present in the system. This information includes parameters that are defined in the driver's data/dptx.tcl file such as the base address of the memory-mapped device and the maximum number of lanes, maximum link rate, and video interface that the DisplayPort instance supports, among others.<p>
+<b>Interrupt processing</b><p>
+DisplayPort interrupts occur on the HPD signal line when the DisplayPort cable is connected/disconnected or when the RX device sends a pulse. The user hardware design must contain an interrupt controller which the DisplayPort TX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts. When the XDptx_HpdInterruptHandler function is invoked, the handler will identify what type of DisplayPort interrupt has occurred, and will call either the HPD event handler function or the HPD pulse handler function, depending on whether a an HPD event on an HPD pulse event occurred.<p>
+The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of interrupt that has occured, and the XDptx_HpdInterruptHandler will use this information to decide which handler to call. An HPD event is identified if bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.<p>
+The HPD event handler may be set up by using the XDptx_SetHpdEventHandler function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler function.<p>
+<b>Multi-stream transport (MST) mode</b><p>
+The driver handles MST mode functionality, including sideband messaging, topology discovery, virtual channel payload ID table management, and directing streams to different sinks.<p>
+MST testing has been done at all possible link rate/lane count/topology/ resolution/color depth combinations with each setting using following values:<ul>
+<li>Link rate: 1.62, 2.70, and 5.40Gbps per lane.</li><li>Lane count: 1, 2, and 4 lanes.</li><li>Number of sink displays: 1, 2, 3, and 4 sink displays in both a daisy-chain configuration and in a configuration using a combination of a 1-to-3 hub and daisy-chain. Each stream was using the same resolution.</li><li>Resolutions (60Hz): 640x480, 800x600, 1024x768, 1280x800, 1280x1024, 1360x768, 1400x1050, 1680x1050, 1920x1080, 1920x2160, and 3840x2160.</li><li>Color depths: 18, 24, 30, 36, and 48 bits per pixel.</li></ul>
+<p>
+<b>Audio</b><p>
+The driver does not handle audio. For an example as to how to configure and transmit audio, examples/xdptx_audio_example.c illustrates the required sequence. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.<p>
+<b>Asserts</b><p>
+Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.<p>
+<b>Limitations</b><p>
+<ul>
+<li>For MST mode to correctly display, the current version of the driver requires that each of the DisplayPort TX streams be allocated without skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems were experienced if skipping stream 2 and assigning stream 4 instead). skipping monitors in a daisy chain is OK as long as they are assigned to streams in order.</li><li>In MST mode, the current version of the driver does not support removal of an allocated stream from the virtual channel payload ID table without clearing the entire table.</li><li>Some sideband messages have not been implemented in the current version of the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY sideband message.</li><li>The driver does not handle audio. See the audio example in the driver examples directory for the required sequence for enabling audio.</li></ul>
+<p>
+<dl compact><dt><b>Note:</b></dt><dd>For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.</dd></dl>
+<pre>
+ MODIFICATION HISTORY:</pre><p>
+<pre> Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.0   als  05/17/14 Initial release.
+       als  08/03/14 Initial MST addition.
+ 2.0   als  09/21/14 Added XDptx_DiscoverTopology function and changed
+                     XDptx_IsConnected from macro to function.
+ 3.0   als  12/16/14 Updated to use common video library.
+                     Added topology reordering functions:
+                         XDptx_TopologySwapSinks,
+                         XDptx_TopologySortSinksByTiling
+                     Added wrapper functions for remote DPCD/I2C read/writes:
+                         XDptx_RemoteDpcdRead, XDptx_RemoteDpcdWrite,
+                         XDptx_RemoteIicRead, XDptx_RemoteIicWrite
+                     Added EDID utility functions:
+                         XDptx_GetRemoteEdid, XDptx_GetEdidBlock,
+                         XDptx_GetRemoteEdidBlock,
+                         XDptx_GetRemoteEdidDispIdExt,
+                         XDptx_GetDispIdDataBlock,
+                         XDptx_GetRemoteTiledDisplayDb
+                     Remove unused arguments from functions:
+                         LinkCountTotal, RelativeAddress from
+                             XDptx_AllocatePayloadVcIdTable
+                         RegStartAddress from XDptx_IicWrite
+ </pre> Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html

@@ -27,18 +27,17 @@
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#5aae7d62087f1d2d732e026fc4a27405">ComponentFormat</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#d9cb9ca501e27d8ac67d2cdefddb0869">DataPerLane</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#38d56ea36d19b0a19372cd0ab1e46368">DynamicRange</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
-  <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#6dd2f67ac69e011b4aca69e5c8993c96">HClkTotal</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#8a71abcd837672ebc8786afeec2a85d3">HStart</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#e5baab206041cf94ed952f2260b03a79">InitWait</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#e38c5264a92f1f3da62ee8ab04fdc768">Misc0</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#b2156fd70d080aff62bc0ce32e0c9228">Misc1</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#90edcc6fa8254a65a8e0c6fdd2cae1a1">NVid</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#577be212fb5a000069331993bd6b90b9">OverrideUserPixelWidth</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
+  <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#fd9713a9d0069b52c41f2badea942920">PixelClockHz</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#fcdf2d723786ffe2c7153a61fdea2966">SynchronousClockMode</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#ffba3d4fddc885d2db008c9e0643df28">TransferUnitSize</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#9c1460f55c4a8cad813aa8942aa48027">UserPixelWidth</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
-  <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#862e898079c25c530cc796330de0ba1a">VClkTotal</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#b37f3817a1bda33892d2dd8a2a6bcc23">VStart</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
-  <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#2e5f919bab78b5937a78d9855b545a24">Vtm</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
+  <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#f4c5b131d48d852703dc31c3f3b6dcde">Vtm</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
   <tr class="memlist"><td><a class="el" href="struct_x_dptx___main_stream_attributes.html#3ec3d85682eb90198377b0fbd92d4df2">YCbCrColorimetry</a></td><td><a class="el" href="struct_x_dptx___main_stream_attributes.html">XDptx_MainStreamAttributes</a></td><td></td></tr>
 </table>Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.

XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html

@@ -29,11 +29,9 @@ This typedef contains the main stream attributes which determine how the video w
 <table border="0" cellpadding="0" cellspacing="0">
 <tr><td></td></tr>
 <tr><td colspan="2"><br><h2>Public Attributes</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">XVid_VideoTimingMode&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dptx___main_stream_attributes.html#2e5f919bab78b5937a78d9855b545a24">Vtm</a></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">XVidC_VideoTimingMode&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dptx___main_stream_attributes.html#f4c5b131d48d852703dc31c3f3b6dcde">Vtm</a></td></tr>
 
-<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dptx___main_stream_attributes.html#6dd2f67ac69e011b4aca69e5c8993c96">HClkTotal</a></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dptx___main_stream_attributes.html#fd9713a9d0069b52c41f2badea942920">PixelClockHz</a></td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dptx___main_stream_attributes.html#862e898079c25c530cc796330de0ba1a">VClkTotal</a></td></tr>
 
 <tr><td class="memItemLeft" nowrap align="right" valign="top">u32&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dptx___main_stream_attributes.html#8a71abcd837672ebc8786afeec2a85d3">HStart</a></td></tr>
 
@@ -144,21 +142,6 @@ Used to translate the number of pixels per line to the native internal 16-bit da
 The dynamic range currently in use by the video stream.
 </div>
 </div><p>
-<a class="anchor" name="6dd2f67ac69e011b4aca69e5c8993c96"></a><!-- doxytag: member="XDptx_MainStreamAttributes::HClkTotal" ref="6dd2f67ac69e011b4aca69e5c8993c96" args="" -->
-<div class="memitem">
-<div class="memproto">
-      <table class="memname">
-        <tr>
-          <td class="memname">u32 <a class="el" href="struct_x_dptx___main_stream_attributes.html#6dd2f67ac69e011b4aca69e5c8993c96">XDptx_MainStreamAttributes::HClkTotal</a>          </td>
-        </tr>
-      </table>
-</div>
-<div class="memdoc">
-
-<p>
-Horizontal total time (in pixels).
-</div>
-</div><p>
 <a class="anchor" name="8a71abcd837672ebc8786afeec2a85d3"></a><!-- doxytag: member="XDptx_MainStreamAttributes::HStart" ref="8a71abcd837672ebc8786afeec2a85d3" args="" -->
 <div class="memitem">
 <div class="memproto">
@@ -249,6 +232,21 @@ N value for the video stream.
 If set to 1, the value stored for UserPixelWidth will be used as the pixel width.
 </div>
 </div><p>
+<a class="anchor" name="fd9713a9d0069b52c41f2badea942920"></a><!-- doxytag: member="XDptx_MainStreamAttributes::PixelClockHz" ref="fd9713a9d0069b52c41f2badea942920" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 <a class="el" href="struct_x_dptx___main_stream_attributes.html#fd9713a9d0069b52c41f2badea942920">XDptx_MainStreamAttributes::PixelClockHz</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The pixel clock of the stream (in Hz).
+</div>
+</div><p>
 <a class="anchor" name="fcdf2d723786ffe2c7153a61fdea2966"></a><!-- doxytag: member="XDptx_MainStreamAttributes::SynchronousClockMode" ref="fcdf2d723786ffe2c7153a61fdea2966" args="" -->
 <div class="memitem">
 <div class="memproto">
@@ -294,21 +292,6 @@ Size of the transfer unit in the framing logic. In MST mode, this is also the nu
 The width of the user data input port.
 </div>
 </div><p>
-<a class="anchor" name="862e898079c25c530cc796330de0ba1a"></a><!-- doxytag: member="XDptx_MainStreamAttributes::VClkTotal" ref="862e898079c25c530cc796330de0ba1a" args="" -->
-<div class="memitem">
-<div class="memproto">
-      <table class="memname">
-        <tr>
-          <td class="memname">u32 <a class="el" href="struct_x_dptx___main_stream_attributes.html#862e898079c25c530cc796330de0ba1a">XDptx_MainStreamAttributes::VClkTotal</a>          </td>
-        </tr>
-      </table>
-</div>
-<div class="memdoc">
-
-<p>
-Vertical total time (in pixels).
-</div>
-</div><p>
 <a class="anchor" name="b37f3817a1bda33892d2dd8a2a6bcc23"></a><!-- doxytag: member="XDptx_MainStreamAttributes::VStart" ref="b37f3817a1bda33892d2dd8a2a6bcc23" args="" -->
 <div class="memitem">
 <div class="memproto">
@@ -324,12 +307,12 @@ Vertical total time (in pixels).
 Vertical blank start (in lines).
 </div>
 </div><p>
-<a class="anchor" name="2e5f919bab78b5937a78d9855b545a24"></a><!-- doxytag: member="XDptx_MainStreamAttributes::Vtm" ref="2e5f919bab78b5937a78d9855b545a24" args="" -->
+<a class="anchor" name="f4c5b131d48d852703dc31c3f3b6dcde"></a><!-- doxytag: member="XDptx_MainStreamAttributes::Vtm" ref="f4c5b131d48d852703dc31c3f3b6dcde" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">XVid_VideoTimingMode <a class="el" href="struct_x_dptx___main_stream_attributes.html#2e5f919bab78b5937a78d9855b545a24">XDptx_MainStreamAttributes::Vtm</a>          </td>
+          <td class="memname">XVidC_VideoTimingMode <a class="el" href="struct_x_dptx___main_stream_attributes.html#f4c5b131d48d852703dc31c3f3b6dcde">XDptx_MainStreamAttributes::Vtm</a>          </td>
         </tr>
       </table>
 </div>

XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html

@@ -21,78 +21,12 @@
     <li><a href="files.html"><span>File&nbsp;List</span></a></li>
     <li><a href="globals.html"><span>File&nbsp;Members</span></a></li>
   </ul></div>
-<h1>xdptx.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
+<h1>xdptx.h File Reference</h1>
-The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the DisplayPort 1.2a specification.<p>
-The Xilinx DisplayPort soft IP supports the following features:<ul>
-<li>1, 2, or 4 lanes.</li><li>A link rate of 1.62, 2.70, or 5.40Gbps per lane.</li><li>1, 2, or 4 pixel-wide video interfaces.</li><li>RGB and YCbCr color space.</li><li>Up to 16 bits per component.</li><li>Up to 4Kx2K monitor resolution.</li><li>Auto lane rate and width negotiation.</li><li>I2C over a 1Mb/s AUX channel.</li><li>Secondary channel audio support (2 channels).</li><li>4 independent video multi-streams.</li></ul>
-<p>
-The Xilinx DisplayPort soft IP does not support the following features:<ul>
-<li>The automated test feature.</li><li>Audio (3-8 channel).</li><li>FAUX.</li><li>Bridging function.</li><li>MST audio.</li><li>eDP optional features.</li><li>iDP.</li><li>GTC.</li></ul>
-<p>
-<b>DisplayPort overview</b><p>
-A DisplayPort link consists of:<ul>
-<li>A unidirectional main link which is used to transport isochronous data streams such as video and audio. The main link may use 1, 2, or 4 lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link needs to be trained prior to sending streams.</li><li>An auxiliary (AUX) channel is a 1MBps bidirectional channel used for link training, link management, and device control.</li><li>A hot-plug-detect (HPD) signal line is used to determine whether a DisplayPort connection exists between the DisplayPort TX connector and an RX device. It is serves as an interrupt request by the RX device.</li></ul>
-<p>
-<b>Driver description</b><p>
-The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort TX soft IP, communicate and control an RX device/sink monitor over the AUX channel, and to initialize and transmit data streams over the main link.<p>
-This driver implements link layer functionality: a Link Policy Maker (LPM) and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.<ul>
-<li>The LPM manages the main link and is responsible for keeping the link synchronized. It will establish a link with a downstream RX device by undergoing a link training sequence which consists of:<ul>
-<li>Clock recovery: The clock needs to be recovered and PLLs need to be locked for all lanes.</li><li>Channel equalization: All lanes need to achieve channel equalization and and symbol lock, as well as for interlane alignment to take place.</li></ul>
-</li><li>The SPM manages transportation of an isochronous stream. That is, it will initialize and maintain a video stream, establish a virtual channel to a sink monitor, and transmit the stream.</li></ul>
-<p>
-Using AUX transactions to read/write from/to the sink's DisplayPort Configuration Data (DPCD) address space, the LPM obtains the link capabilities, obtains link configuration and link and sink status, and configures and controls the link and sink. The main link is trained this way.<p>
-I2C-over-AUX transactions are used to obtain the sink's Extended Display Identification Data (EDID) which give information on the display capabilities of the monitor. The SPM may use this information to determine what available screen resolutions and video timing are possible.<p>
-<b>Device configuration</b><p>
-The device can be configured in various ways during the FPGA implementation process. Configuration parameters are stored in the xdptx_g.c file which is generated when compiling the board support package (BSP). A table is defined where each entry contains configuration information for the DisplayPort instances present in the system. This information includes parameters that are defined in the driver's data/dptx.tcl file such as the base address of the memory-mapped device and the maximum number of lanes, maximum link rate, and video interface that the DisplayPort instance supports, among others.<p>
-<b>Interrupt processing</b><p>
-DisplayPort interrupts occur on the HPD signal line when the DisplayPort cable is connected/disconnected or when the RX device sends a pulse. The user hardware design must contain an interrupt controller which the DisplayPort TX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts. When the XDptx_HpdInterruptHandler function is invoked, the handler will identify what type of DisplayPort interrupt has occurred, and will call either the HPD event handler function or the HPD pulse handler function, depending on whether a an HPD event on an HPD pulse event occurred.<p>
-The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of interrupt that has occured, and the XDptx_HpdInterruptHandler will use this information to decide which handler to call. An HPD event is identified if bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.<p>
-The HPD event handler may be set up by using the XDptx_SetHpdEventHandler function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler function.<p>
-<b>Multi-stream transport (MST) mode</b><p>
-The driver handles MST mode functionality, including sideband messaging, topology discovery, virtual channel payload ID table management, and directing streams to different sinks.<p>
-MST testing has been done at all possible link rate/lane count/topology/ resolution/color depth combinations with each setting using following values:<ul>
-<li>Link rate: 1.62, 2.70, and 5.40Gbps per lane.</li><li>Lane count: 1, 2, and 4 lanes.</li><li>Number of sink displays: 1, 2, 3, and 4 sink displays in both a daisy-chain configuration and in a configuration using a combination of a 1-to-3 hub and daisy-chain. Each stream was using the same resolution.</li><li>Resolutions (60Hz): 640x480, 800x600, 1024x768, 1280x800, 1280x1024, 1360x768, 1400x1050, 1680x1050, 1920x1080, 1920x2160, and 3840x2160.</li><li>Color depths: 18, 24, 30, 36, and 48 bits per pixel.</li></ul>
-<p>
-<b>Audio</b><p>
-The driver does not handle audio. For an example as to how to configure and transmit audio, examples/xdptx_audio_example.c illustrates the required sequence. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.<p>
-<b>Asserts</b><p>
-Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.<p>
-<b>Limitations</b><p>
-<ul>
-<li>For MST mode to correctly display, the current version of the driver requires that each of the DisplayPort TX streams be allocated without skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems were experienced if skipping stream 2 and assigning stream 4 instead). skipping monitors in a daisy chain is OK as long as they are assigned to streams in order.</li><li>In MST mode, the current version of the driver does not support removal of an allocated stream from the virtual channel payload ID table without clearing the entire table.</li><li>Some sideband messages have not been implemented in the current version of the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY sideband message.</li><li>The driver does not handle audio. See the audio example in the driver examples directory for the required sequence for enabling audio.</li></ul>
-<p>
-<dl compact><dt><b>Note:</b></dt><dd>For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.</dd></dl>
-<pre>
- MODIFICATION HISTORY:</pre><p>
-<pre> Ver   Who  Date     Changes
- ----- ---- -------- -----------------------------------------------
- 1.0   als  05/17/14 Initial release.
-       als  08/03/14 Initial MST addition.
- 2.0   als  09/21/14 Added XDptx_DiscoverTopology function and changed
-                     XDptx_IsConnected from macro to function.
- 3.0   als  12/16/14 Updated to use common video library.
-                     Added topology reordering functions:
-                         XDptx_TopologySwapSinks,
-                         XDptx_TopologySortSinksByTiling
-                     Added wrapper functions for remote DPCD/I2C read/writes:
-                         XDptx_RemoteDpcdRead, XDptx_RemoteDpcdWrite,
-                         XDptx_RemoteIicRead, XDptx_RemoteIicWrite
-                     Added EDID utility functions:
-                         XDptx_GetRemoteEdid, XDptx_GetEdidBlock,
-                         XDptx_GetRemoteEdidBlock,
-                         XDptx_GetRemoteEdidDispIdExt,
-                         XDptx_GetDispIdDataBlock,
-                         XDptx_GetRemoteTiledDisplayDb
-                     Remove unused arguments from functions:
-                         LinkCountTotal, RelativeAddress from
-                             XDptx_AllocatePayloadVcIdTable
-                         RegStartAddress from XDptx_IicWrite
- </pre>
 <p>
 <code>#include &quot;<a class="el" href="xdptx__hw_8h.html">xdptx_hw.h</a>&quot;</code><br>
 <code>#include &quot;xil_assert.h&quot;</code><br>
 <code>#include &quot;xil_types.h&quot;</code><br>
-<code>#include &quot;xvid.h&quot;</code><br>
+<code>#include &quot;xvidc.h&quot;</code><br>
 <table border="0" cellpadding="0" cellspacing="0">
 <tr><td></td></tr>
 <tr><td colspan="2"><br><h2>Classes</h2></td></tr>
@@ -180,7 +114,7 @@ Asserts are used within all Xilinx drivers to enforce constraints on argument va
 
 <tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#99d8902337e7bb3f7c607568501e16a1">XDptx_CfgMsaRecalculate</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream)</td></tr>
 
-<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#8f5a8d3f316f519145ecd9a94bf27ce8">XDptx_CfgMsaUseStandardVideoMode</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream, XVid_VideoMode VideoMode)</td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#79a528fe544595d48fbf1d2438f0304d">XDptx_CfgMsaUseStandardVideoMode</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode)</td></tr>
 
 <tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx_8h.html#b4778897734128bf467047a90066c922">XDptx_CfgMsaUseEdidPreferredTiming</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream, u8 *Edid)</td></tr>
 
@@ -791,7 +725,7 @@ This function sets the bits per color value of the video stream.<p>
 
 <p>
 This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr-&gt;MsaConfig. If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes (MSA) that must be contained in the MsaConfigCustom structure are:<ul>
-<li>Pixel clock (in KHz)</li><li>Horizontal sync polarity</li><li>Vertical sync polarity</li><li>Horizontal sync pulse width</li><li>Vertical sync pulse width</li><li>Horizontal resolution</li><li>Vertical resolution</li><li>Vertical back porch</li><li>Vertical front porch</li><li>Horizontal back porch</li><li>Horizontal front porch</li></ul>
+<li>Pixel clock (in Hz)</li><li>Horizontal sync polarity</li><li>Vertical sync polarity</li><li>Horizontal sync pulse width</li><li>Vertical sync pulse width</li><li>Horizontal resolution</li><li>Vertical resolution</li><li>Vertical back porch</li><li>Vertical front porch</li><li>Horizontal back porch</li><li>Horizontal front porch</li></ul>
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 <dl compact><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
@@ -851,7 +785,7 @@ This function sets the main stream attribute values in the configuration structu
 
 </div>
 </div><p>
-<a class="anchor" name="8f5a8d3f316f519145ecd9a94bf27ce8"></a><!-- doxytag: member="xdptx.h::XDptx_CfgMsaUseStandardVideoMode" ref="8f5a8d3f316f519145ecd9a94bf27ce8" args="(XDptx *InstancePtr, u8 Stream, XVid_VideoMode VideoMode)" -->
+<a class="anchor" name="79a528fe544595d48fbf1d2438f0304d"></a><!-- doxytag: member="xdptx.h::XDptx_CfgMsaUseStandardVideoMode" ref="79a528fe544595d48fbf1d2438f0304d" args="(XDptx *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode)" -->
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@@ -870,7 +804,7 @@ This function sets the main stream attribute values in the configuration structu
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           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype">XVid_VideoMode&nbsp;</td>
+          <td class="paramtype">XVidC_VideoMode&nbsp;</td>
           <td class="paramname"> <em>VideoMode</em></td><td>&nbsp;</td>
         </tr>
         <tr>

XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html

@@ -42,7 +42,7 @@ This file contains the stream policy maker functions for the <a class="el" href=
 <tr><td colspan="2"><br><h2>Functions</h2></td></tr>
 <tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__spm_8c.html#99d8902337e7bb3f7c607568501e16a1">XDptx_CfgMsaRecalculate</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream)</td></tr>
 
-<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__spm_8c.html#8f5a8d3f316f519145ecd9a94bf27ce8">XDptx_CfgMsaUseStandardVideoMode</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream, XVid_VideoMode VideoMode)</td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__spm_8c.html#79a528fe544595d48fbf1d2438f0304d">XDptx_CfgMsaUseStandardVideoMode</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode)</td></tr>
 
 <tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__spm_8c.html#b4778897734128bf467047a90066c922">XDptx_CfgMsaUseEdidPreferredTiming</a> (<a class="el" href="struct_x_dptx.html">XDptx</a> *InstancePtr, u8 Stream, u8 *Edid)</td></tr>
 
@@ -229,7 +229,7 @@ This function sets the bits per color value of the video stream.<p>
 
 <p>
 This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr-&gt;MsaConfig. If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes (MSA) that must be contained in the MsaConfigCustom structure are:<ul>
-<li>Pixel clock (in KHz)</li><li>Horizontal sync polarity</li><li>Vertical sync polarity</li><li>Horizontal sync pulse width</li><li>Vertical sync pulse width</li><li>Horizontal resolution</li><li>Vertical resolution</li><li>Vertical back porch</li><li>Vertical front porch</li><li>Horizontal back porch</li><li>Horizontal front porch</li></ul>
+<li>Pixel clock (in Hz)</li><li>Horizontal sync polarity</li><li>Vertical sync polarity</li><li>Horizontal sync pulse width</li><li>Vertical sync pulse width</li><li>Horizontal resolution</li><li>Vertical resolution</li><li>Vertical back porch</li><li>Vertical front porch</li><li>Horizontal back porch</li><li>Horizontal front porch</li></ul>
 <p>
 <dl compact><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
@@ -289,7 +289,7 @@ This function sets the main stream attribute values in the configuration structu
 
 </div>
 </div><p>
-<a class="anchor" name="8f5a8d3f316f519145ecd9a94bf27ce8"></a><!-- doxytag: member="xdptx_spm.c::XDptx_CfgMsaUseStandardVideoMode" ref="8f5a8d3f316f519145ecd9a94bf27ce8" args="(XDptx *InstancePtr, u8 Stream, XVid_VideoMode VideoMode)" -->
+<a class="anchor" name="79a528fe544595d48fbf1d2438f0304d"></a><!-- doxytag: member="xdptx_spm.c::XDptx_CfgMsaUseStandardVideoMode" ref="79a528fe544595d48fbf1d2438f0304d" args="(XDptx *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode)" -->
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@@ -308,7 +308,7 @@ This function sets the main stream attribute values in the configuration structu
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           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype">XVid_VideoMode&nbsp;</td>
+          <td class="paramtype">XVidC_VideoMode&nbsp;</td>
           <td class="paramname"> <em>VideoMode</em></td><td>&nbsp;</td>
         </tr>
         <tr>