dprxss: Modified the order of execution in training pattern 1 callback
This patch modifies the order of execution in training pattern 1 callback as DP159 programming for training pattern 1 and then link bandwidth callback. This modification require for few GPUs (Intel) to allow DP159 programming for training pattern 1 before link bandwidth callback. Signed-off-by: Shadul Shaikh <shaduls@xilinx.com> Acked-by: Srikanth Vemula <svemula@xilinx.com>
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1 changed files with 7 additions and 5 deletions
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@ -51,6 +51,8 @@
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* Protected HDCP under macro number of instances.
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* 2.00 sha 10/15/15 Generate a HPD interrupt whenever RX cable
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* disconnect/unplug interrupt is detected.
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* 2.00 sha 11/06/15 Modified the order of execution in TP1 callback as DP159
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* config for TP1 and then link bandwidth callback.
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* </pre>
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*
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******************************************************************************/
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@ -1213,16 +1215,16 @@ static void StubTp1Callback(void *InstancePtr)
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XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
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XDPRXSS_DPCD_LANE_COUNT_SET);
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/* Link bandwidth callback */
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if (DpRxSsPtr->LinkBwCallback) {
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DpRxSsPtr->LinkBwCallback(DpRxSsPtr->LinkBwRef);
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}
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/* DP159 config for TP1 */
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XVidC_Dp159Config(DpRxSsPtr->IicPtr, XVIDC_DP159_CT_TP1,
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DpRxSsPtr->UsrOpt.LinkRate,
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DpRxSsPtr->UsrOpt.LaneCount);
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/* Link bandwidth callback */
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if (DpRxSsPtr->LinkBwCallback) {
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DpRxSsPtr->LinkBwCallback(DpRxSsPtr->LinkBwRef);
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}
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XDpRxSs_WriteReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
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XDPRXSS_RX_PHY_CONFIG, 0x3800000);
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