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dprxss: Modified the order of execution in training pattern 1 callback

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This patch modifies the order of execution in training pattern 1 callback as
DP159 programming for training pattern 1 and then link bandwidth callback.

This modification require for few GPUs (Intel) to allow DP159 programming for
training pattern 1 before link bandwidth callback.

Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This commit is contained in:
Shadul Shaikh 2015-11-06 15:51:01 +05:30 • committed by Nava kishore Manne
parent fc2ea039d9
commit 46350e52d2
1 changed files with 7 additions and 5 deletions
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12
XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c
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@ -51,6 +51,8 @@
* Protected HDCP under macro number of instances.
* 2.00 sha 10/15/15 Generate a HPD interrupt whenever RX cable
* disconnect/unplug interrupt is detected.
* 2.00 sha 11/06/15 Modified the order of execution in TP1 callback as DP159
* config for TP1 and then link bandwidth callback.
* </pre>
*
******************************************************************************/
@ -1213,16 +1215,16 @@ static void StubTp1Callback(void *InstancePtr)
XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
XDPRXSS_DPCD_LANE_COUNT_SET);
/* Link bandwidth callback */
if (DpRxSsPtr->LinkBwCallback) {
DpRxSsPtr->LinkBwCallback(DpRxSsPtr->LinkBwRef);
}
/* DP159 config for TP1 */
XVidC_Dp159Config(DpRxSsPtr->IicPtr, XVIDC_DP159_CT_TP1,
DpRxSsPtr->UsrOpt.LinkRate,
DpRxSsPtr->UsrOpt.LaneCount);
/* Link bandwidth callback */
if (DpRxSsPtr->LinkBwCallback) {
DpRxSsPtr->LinkBwCallback(DpRxSsPtr->LinkBwRef);
}
XDpRxSs_WriteReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
XDPRXSS_RX_PHY_CONFIG, 0x3800000);