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zynq_fsbl: Fix for CR#785778, CR#773866, CR#791245

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This patch fixes for CR#785778, CR#773866, CR#791245

Signed-off-by: Krishna Chaitanya <kpataka@xilinx.com>
This commit is contained in:
Krishna Chaitanya 2014-04-18 14:42:07 +05:30 • committed by Jagannadha Sutradharudu Teki
parent 234ca56569
commit 4f9efaf584
9 changed files with 464 additions and 177 deletions
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6
lib/sw_apps/zynq_fsbl/data/zynq_fsbl.mss
View file

@ -9,4 +9,8 @@ END
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = xilffs
END
END
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = xilrsa
END

8
lib/sw_apps/zynq_fsbl/data/zynq_fsbl.tcl
View file

@ -34,6 +34,14 @@ proc swapp_is_supported_sw {} {
} elseif { [llength $librarylist] > 1} {
error "Multiple xilffs libraries present in the Board Support Package."
}
# make sure xilrsa is available
set librarylist [get_libs -filter "NAME==xilrsa"];
if { [llength $librarylist] == 0 } {
error "This application requires xilrsa library in the Board Support Package.";
} elseif { [llength $librarylist] > 1} {
error "Multiple xilrsa libraries present in the Board Support Package."
}
}
proc swapp_is_supported_hw {} {

12
lib/sw_apps/zynq_fsbl/src/fsbl.h
View file

@ -201,6 +201,16 @@
* 02/20/14 775631 - FSBL: FsblGetGlobalTimer() is not proper
* Resolution: Function argument is updated from value
* to pointer to reflect updated value
* 9.00a kc 04/16/14 773866 - SetPpk() will fail on secure fallback
* unless FSBL* and FSBL are identical in length
* Resolution: PPK is set only once now.
* 785778 - FSBL takes 8 seconds to
* authenticate (RSA) a bitstream on zc706
* Resolution: Data Caches are enabled only for
* authentication.
* 791245 - Use of xilrsa in fsbl
* Resolution: Rsa library is removed from fsbl source
* and xilrsa is used from BSP
* </pre>
*
* </pre>
@ -286,7 +296,7 @@ extern "C" {
* SDK release version
*/
#define SDK_RELEASE_YEAR 2014
#define SDK_RELEASE_QUARTER 1
#define SDK_RELEASE_QUARTER 2
#define WORD_LENGTH_SHIFT 2

6
lib/sw_apps/zynq_fsbl/src/image_mover.c
View file

@ -76,6 +76,8 @@
* for encrypted images
* Fix for CR#761895 FSBL should authenticate image
* only if partition owner was not set to u-boot
* 9.00a kc 04/16/14 Fix for CR#785778 FSBL takes 8 seconds to
* authenticate (RSA) a bitstream on zc706
*
* </pre>
*
@ -99,6 +101,7 @@
#ifdef RSA_SUPPORT
#include "rsa.h"
#include "xil_cache.h"
#endif
/************************** Constant Definitions *****************************/
@ -489,6 +492,7 @@ u32 LoadBootImage(void)
*/
if (SignedPartitionFlag == 1 ) {
#ifdef RSA_SUPPORT
Xil_DCacheEnable();
Status = AuthenticatePartition((u8*)PartitionStartAddr,
(PartitionTotalSize << WORD_LENGTH_SHIFT));
if (Status != XST_SUCCESS) {
@ -497,6 +501,8 @@ u32 LoadBootImage(void)
FsblFallback();
}
fsbl_printf(DEBUG_INFO,"Authentication Done\r\n");
Xil_DCacheFlush();
Xil_DCacheDisable();
#else
/*
* In case user not enabled RSA authentication feature

BIN
lib/sw_apps/zynq_fsbl/src/librsa.a
View file

Binary file not shown.

17
lib/sw_apps/zynq_fsbl/src/main.c
View file

@ -98,7 +98,10 @@
* function
* 7.00a kc 10/18/13 Integrated SD/MMC driver
* 8.00a kc 02/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
* is not proper
* is not proper
* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
* fallback unless FSBL* and FSBL
* are identical in length
* </pre>
*
* @note
@ -139,6 +142,10 @@
#include "xuartps_hw.h"
#endif
#ifdef RSA_SUPPORT
#include "rsa.h"
#endif
/************************** Constant Definitions *****************************/
#ifdef XPAR_XWDTPS_0_BASEADDR
@ -654,6 +661,14 @@ void FsblFallback(void)
*/
FabricInit();
#ifdef RSA_SUPPORT
/*
* Making sure PPK is set for efuse error cases
*/
SetPpk();
#endif
/*
* Search for next valid image
*/

409
lib/sw_apps/zynq_fsbl/src/ps7_init.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
@ -455,9 +455,9 @@ unsigned long ps7_clock_init_data_3_0[] = {
// .. USB0_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. USB1_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[3:3] = 0x00000001U
// .. ==> MASK : 0x00000008U VAL : 0x00000008U
// .. USB1_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. GEM0_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[6:6] = 0x00000001U
// .. ==> MASK : 0x00000040U VAL : 0x00000040U
@ -485,26 +485,26 @@ unsigned long ps7_clock_init_data_3_0[] = {
// .. I2C0_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[18:18] = 0x00000001U
// .. ==> MASK : 0x00040000U VAL : 0x00040000U
// .. I2C1_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[19:19] = 0x00000001U
// .. ==> MASK : 0x00080000U VAL : 0x00080000U
// .. I2C1_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[19:19] = 0x00000000U
// .. ==> MASK : 0x00080000U VAL : 0x00000000U
// .. UART0_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[20:20] = 0x00000000U
// .. ==> MASK : 0x00100000U VAL : 0x00000000U
// .. UART1_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[21:21] = 0x00000001U
// .. ==> MASK : 0x00200000U VAL : 0x00200000U
// .. GPIO_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[22:22] = 0x00000001U
// .. ==> MASK : 0x00400000U VAL : 0x00400000U
// .. GPIO_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[22:22] = 0x00000000U
// .. ==> MASK : 0x00400000U VAL : 0x00000000U
// .. LQSPI_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[23:23] = 0x00000001U
// .. ==> MASK : 0x00800000U VAL : 0x00800000U
// .. SMC_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[24:24] = 0x00000001U
// .. ==> MASK : 0x01000000U VAL : 0x01000000U
// .. SMC_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[24:24] = 0x00000000U
// .. ==> MASK : 0x01000000U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x00A50445U),
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
// .. START: THIS SHOULD BE BLANK
// .. FINISH: THIS SHOULD BE BLANK
@ -3846,6 +3846,10 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
// .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. START: ADD 1 MS DELAY
// .. .. ..
EMIT_MASKDELAY(0XF8F00200, 1),
// .. .. .. FINISH: ADD 1 MS DELAY
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. MASK_0_LSW = 0xff7f
// .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
@ -3914,6 +3918,10 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
// .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. START: ADD 1 MS DELAY
// .. .. ..
EMIT_MASKDELAY(0XF8F00200, 1),
// .. .. .. FINISH: ADD 1 MS DELAY
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. MASK_0_LSW = 0xf7ff
// .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
@ -3982,6 +3990,10 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
// .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. START: ADD 1 MS DELAY
// .. .. ..
EMIT_MASKDELAY(0XF8F00200, 1),
// .. .. .. FINISH: ADD 1 MS DELAY
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. MASK_0_LSW = 0xdfff
// .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
@ -4123,6 +4135,78 @@ unsigned long ps7_post_config_3_0[] = {
//
};
unsigned long ps7_debug_3_0[] = {
// START: top
// .. START: CROSS TRIGGER CONFIGURATIONS
// .. .. START: UNLOCKING CTI REGISTERS
// .. .. KEY = 0XC5ACCE55
// .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
// .. ..
EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
// .. .. KEY = 0XC5ACCE55
// .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
// .. ..
EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
// .. .. KEY = 0XC5ACCE55
// .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
// .. ..
EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
// .. .. FINISH: UNLOCKING CTI REGISTERS
// .. .. START: ENABLING CTI MODULES AND CHANNELS
// .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
// .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
// .. .. TRIGINEN = 0
// .. .. ==> 0XF8809020[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8809020, 0x0000000FU ,0x00000000U),
// .. .. TRIGINEN = 0
// .. .. ==> 0XF8809024[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8809024, 0x0000000FU ,0x00000000U),
// .. .. TRIGINEN = 0
// .. .. ==> 0XF8809028[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8809028, 0x0000000FU ,0x00000000U),
// .. .. TRIGINEN = 0
// .. .. ==> 0XF880902C[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF880902C, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090A0[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090A0, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090A4[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090A4, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090A8[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090A8, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090AC[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090AC, 0x0000000FU ,0x00000000U),
// .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
// .. FINISH: CROSS TRIGGER CONFIGURATIONS
// FINISH: top
//
EMIT_EXIT(),
//
};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
// .. START: SLCR SETTINGS
@ -4529,9 +4613,9 @@ unsigned long ps7_clock_init_data_2_0[] = {
// .. USB0_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. USB1_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[3:3] = 0x00000001U
// .. ==> MASK : 0x00000008U VAL : 0x00000008U
// .. USB1_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. GEM0_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[6:6] = 0x00000001U
// .. ==> MASK : 0x00000040U VAL : 0x00000040U
@ -4559,26 +4643,26 @@ unsigned long ps7_clock_init_data_2_0[] = {
// .. I2C0_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[18:18] = 0x00000001U
// .. ==> MASK : 0x00040000U VAL : 0x00040000U
// .. I2C1_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[19:19] = 0x00000001U
// .. ==> MASK : 0x00080000U VAL : 0x00080000U
// .. I2C1_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[19:19] = 0x00000000U
// .. ==> MASK : 0x00080000U VAL : 0x00000000U
// .. UART0_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[20:20] = 0x00000000U
// .. ==> MASK : 0x00100000U VAL : 0x00000000U
// .. UART1_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[21:21] = 0x00000001U
// .. ==> MASK : 0x00200000U VAL : 0x00200000U
// .. GPIO_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[22:22] = 0x00000001U
// .. ==> MASK : 0x00400000U VAL : 0x00400000U
// .. GPIO_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[22:22] = 0x00000000U
// .. ==> MASK : 0x00400000U VAL : 0x00000000U
// .. LQSPI_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[23:23] = 0x00000001U
// .. ==> MASK : 0x00800000U VAL : 0x00800000U
// .. SMC_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[24:24] = 0x00000001U
// .. ==> MASK : 0x01000000U VAL : 0x01000000U
// .. SMC_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[24:24] = 0x00000000U
// .. ==> MASK : 0x01000000U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x00A50445U),
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
// .. START: THIS SHOULD BE BLANK
// .. FINISH: THIS SHOULD BE BLANK
@ -8093,6 +8177,10 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
// .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. START: ADD 1 MS DELAY
// .. .. ..
EMIT_MASKDELAY(0XF8F00200, 1),
// .. .. .. FINISH: ADD 1 MS DELAY
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. MASK_0_LSW = 0xff7f
// .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
@ -8161,6 +8249,10 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
// .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. START: ADD 1 MS DELAY
// .. .. ..
EMIT_MASKDELAY(0XF8F00200, 1),
// .. .. .. FINISH: ADD 1 MS DELAY
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. MASK_0_LSW = 0xf7ff
// .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
@ -8229,6 +8321,10 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
// .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. START: ADD 1 MS DELAY
// .. .. ..
EMIT_MASKDELAY(0XF8F00200, 1),
// .. .. .. FINISH: ADD 1 MS DELAY
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. MASK_0_LSW = 0xdfff
// .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
@ -8364,6 +8460,78 @@ unsigned long ps7_post_config_2_0[] = {
//
};
unsigned long ps7_debug_2_0[] = {
// START: top
// .. START: CROSS TRIGGER CONFIGURATIONS
// .. .. START: UNLOCKING CTI REGISTERS
// .. .. KEY = 0XC5ACCE55
// .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
// .. ..
EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
// .. .. KEY = 0XC5ACCE55
// .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
// .. ..
EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
// .. .. KEY = 0XC5ACCE55
// .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
// .. ..
EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
// .. .. FINISH: UNLOCKING CTI REGISTERS
// .. .. START: ENABLING CTI MODULES AND CHANNELS
// .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
// .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
// .. .. TRIGINEN = 0
// .. .. ==> 0XF8809020[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8809020, 0x0000000FU ,0x00000000U),
// .. .. TRIGINEN = 0
// .. .. ==> 0XF8809024[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8809024, 0x0000000FU ,0x00000000U),
// .. .. TRIGINEN = 0
// .. .. ==> 0XF8809028[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8809028, 0x0000000FU ,0x00000000U),
// .. .. TRIGINEN = 0
// .. .. ==> 0XF880902C[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF880902C, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090A0[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090A0, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090A4[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090A4, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090A8[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090A8, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090AC[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090AC, 0x0000000FU ,0x00000000U),
// .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
// .. FINISH: CROSS TRIGGER CONFIGURATIONS
// FINISH: top
//
EMIT_EXIT(),
//
};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
// .. START: SLCR SETTINGS
@ -8770,9 +8938,9 @@ unsigned long ps7_clock_init_data_1_0[] = {
// .. USB0_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[2:2] = 0x00000001U
// .. ==> MASK : 0x00000004U VAL : 0x00000004U
// .. USB1_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[3:3] = 0x00000001U
// .. ==> MASK : 0x00000008U VAL : 0x00000008U
// .. USB1_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[3:3] = 0x00000000U
// .. ==> MASK : 0x00000008U VAL : 0x00000000U
// .. GEM0_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[6:6] = 0x00000001U
// .. ==> MASK : 0x00000040U VAL : 0x00000040U
@ -8800,26 +8968,26 @@ unsigned long ps7_clock_init_data_1_0[] = {
// .. I2C0_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[18:18] = 0x00000001U
// .. ==> MASK : 0x00040000U VAL : 0x00040000U
// .. I2C1_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[19:19] = 0x00000001U
// .. ==> MASK : 0x00080000U VAL : 0x00080000U
// .. I2C1_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[19:19] = 0x00000000U
// .. ==> MASK : 0x00080000U VAL : 0x00000000U
// .. UART0_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[20:20] = 0x00000000U
// .. ==> MASK : 0x00100000U VAL : 0x00000000U
// .. UART1_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[21:21] = 0x00000001U
// .. ==> MASK : 0x00200000U VAL : 0x00200000U
// .. GPIO_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[22:22] = 0x00000001U
// .. ==> MASK : 0x00400000U VAL : 0x00400000U
// .. GPIO_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[22:22] = 0x00000000U
// .. ==> MASK : 0x00400000U VAL : 0x00000000U
// .. LQSPI_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[23:23] = 0x00000001U
// .. ==> MASK : 0x00800000U VAL : 0x00800000U
// .. SMC_CPU_1XCLKACT = 0x1
// .. ==> 0XF800012C[24:24] = 0x00000001U
// .. ==> MASK : 0x01000000U VAL : 0x01000000U
// .. SMC_CPU_1XCLKACT = 0x0
// .. ==> 0XF800012C[24:24] = 0x00000000U
// .. ==> MASK : 0x01000000U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x00A50445U),
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
// .. START: THIS SHOULD BE BLANK
// .. FINISH: THIS SHOULD BE BLANK
@ -12267,6 +12435,10 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
// .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. START: ADD 1 MS DELAY
// .. .. ..
EMIT_MASKDELAY(0XF8F00200, 1),
// .. .. .. FINISH: ADD 1 MS DELAY
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. MASK_0_LSW = 0xff7f
// .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
@ -12335,6 +12507,10 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
// .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. START: ADD 1 MS DELAY
// .. .. ..
EMIT_MASKDELAY(0XF8F00200, 1),
// .. .. .. FINISH: ADD 1 MS DELAY
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. MASK_0_LSW = 0xf7ff
// .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
@ -12403,6 +12579,10 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
// .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
// .. .. .. START: ADD 1 MS DELAY
// .. .. ..
EMIT_MASKDELAY(0XF8F00200, 1),
// .. .. .. FINISH: ADD 1 MS DELAY
// .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
// .. .. .. MASK_0_LSW = 0xdfff
// .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
@ -12538,6 +12718,78 @@ unsigned long ps7_post_config_1_0[] = {
//
};
unsigned long ps7_debug_1_0[] = {
// START: top
// .. START: CROSS TRIGGER CONFIGURATIONS
// .. .. START: UNLOCKING CTI REGISTERS
// .. .. KEY = 0XC5ACCE55
// .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
// .. ..
EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
// .. .. KEY = 0XC5ACCE55
// .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
// .. ..
EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
// .. .. KEY = 0XC5ACCE55
// .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
// .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
// .. ..
EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
// .. .. FINISH: UNLOCKING CTI REGISTERS
// .. .. START: ENABLING CTI MODULES AND CHANNELS
// .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
// .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
// .. .. TRIGINEN = 0
// .. .. ==> 0XF8809020[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8809020, 0x0000000FU ,0x00000000U),
// .. .. TRIGINEN = 0
// .. .. ==> 0XF8809024[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8809024, 0x0000000FU ,0x00000000U),
// .. .. TRIGINEN = 0
// .. .. ==> 0XF8809028[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF8809028, 0x0000000FU ,0x00000000U),
// .. .. TRIGINEN = 0
// .. .. ==> 0XF880902C[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF880902C, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090A0[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090A0, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090A4[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090A4, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090A8[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090A8, 0x0000000FU ,0x00000000U),
// .. .. TRIGOUTEN = 0
// .. .. ==> 0XF88090AC[3:0] = 0x00000000U
// .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
// .. ..
EMIT_MASKWRITE(0XF88090AC, 0x0000000FU ,0x00000000U),
// .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
// .. FINISH: CROSS TRIGGER CONFIGURATIONS
// FINISH: top
//
EMIT_EXIT(),
//
};
#include "xil_io.h"
#define PS7_MASK_POLL_TIME 100000000
@ -12576,7 +12828,7 @@ void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
int mask_poll(unsigned long add , unsigned long mask ) {
unsigned long *addr = (unsigned long*) add;
volatile unsigned long *addr = (volatile unsigned long*) add;
int i = 0;
while (!(*addr & mask)) {
if (i == PS7_MASK_POLL_TIME) {
@ -12658,6 +12910,14 @@ ps7_config(unsigned long * ps7_config_init)
i++;
}
break;
case OPCODE_MASKDELAY:
addr = (unsigned long*) args[0];
mask = args[1];
int delay = get_number_of_cycles_for_delay(mask);
perf_reset_and_start_timer();
while ((*addr < delay)) {
}
break;
default:
finish = PS7_INIT_CORRUPT;
break;
@ -12691,11 +12951,31 @@ ps7_post_config()
return PS7_INIT_SUCCESS;
}
int
ps7_debug()
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();
int ret = -1;
if (si_ver == PCW_SILICON_VERSION_1) {
ret = ps7_config (ps7_debug_1_0);
if (ret != PS7_INIT_SUCCESS) return ret;
} else if (si_ver == PCW_SILICON_VERSION_2) {
ret = ps7_config (ps7_debug_2_0);
if (ret != PS7_INIT_SUCCESS) return ret;
} else {
ret = ps7_config (ps7_debug_3_0);
if (ret != PS7_INIT_SUCCESS) return ret;
}
return PS7_INIT_SUCCESS;
}
int
ps7_init()
{
// Get the PS_VERSION on run time
unsigned long si_ver = ps7GetSiliconVersion ();
int ret;
//int pcw_ver = 0;
if (si_ver == PCW_SILICON_VERSION_1) {
@ -12724,7 +13004,7 @@ ps7_init()
}
// MIO init
int ret = ps7_config (ps7_mio_init_data);
ret = ps7_config (ps7_mio_init_data);
if (ret != PS7_INIT_SUCCESS) return ret;
// PLL init
@ -12748,3 +13028,48 @@ ps7_init()
return PS7_INIT_SUCCESS;
}
/* For delay calculation using global timer */
/* start timer */
void perf_start_clock(void)
{
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
(1 << 3) | // Auto-increment
(0 << 8) // Pre-scale
);
}
/* stop timer and reset timer count regs */
void perf_reset_clock(void)
{
perf_disable_clock();
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
}
/* Compute mask for given delay in miliseconds*/
int get_number_of_cycles_for_delay(unsigned int delay)
{
// GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
return (APU_FREQ*delay/(2*1000));
}
/* stop timer */
void perf_disable_clock(void)
{
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
}
void perf_reset_and_start_timer()
{
perf_reset_clock();
perf_start_clock();
}

85
lib/sw_apps/zynq_fsbl/src/rsa.c
View file

@ -59,6 +59,10 @@
* the Partition images
* Fix for CR#722979 - Provide customer-friendly
* changelogs in FSBL
* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
* fallback unless FSBL* and FSBL are
* identical in length
* Fix for CR#791245 - Use of xilrsa in FSBL
* </pre>
*
* @note
@ -68,6 +72,7 @@
/***************************** Include Files *********************************/
#include "fsbl.h"
#include "rsa.h"
#include "xilrsa.h"
#ifdef XPAR_XWDTPS_0_BASEADDR
#include "xwdtps.h"
@ -93,7 +98,7 @@ extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
static u8 *PpkModular;
static u8 *PpkModularEx;
static u32 PpkExp;
static u32 PpkAlreadySet=0;
extern u32 FsblLength;
@ -132,43 +137,55 @@ void SetPpk(void )
{
u32 PadSize;
u8 *PpkPtr;
/*
* Set PpkPtr to PPK in OCM
* Set PPK only if is not already set
*/
/*
* Skip FSBL Length
*/
PpkPtr = (u8 *)(FsblLength);
/*
* Skip to 64 byte Boundary
*/
PadSize = ((u32)PpkPtr % 64);
if(PadSize != 0)
if(PpkAlreadySet == 0)
{
PpkPtr += (64 - PadSize);
/*
* Set PpkPtr to PPK in OCM
*/
/*
* Skip FSBL Length
*/
PpkPtr = (u8 *)(FsblLength);
/*
* Skip to 64 byte Boundary
*/
PadSize = ((u32)PpkPtr % 64);
if(PadSize != 0)
{
PpkPtr += (64 - PadSize);
}
/*
* Increment the pointer by authentication Header size
*/
PpkPtr += RSA_HEADER_SIZE;
/*
* Increment the pointer by Magic word size
*/
PpkPtr += RSA_MAGIC_WORD_SIZE;
/*
* Set pointer to PPK
*/
PpkModular = (u8 *)PpkPtr;
PpkPtr += RSA_PPK_MODULAR_SIZE;
PpkModularEx = (u8 *)PpkPtr;
PpkPtr += RSA_PPK_MODULAR_EXT_SIZE;
PpkExp = *((u32 *)PpkPtr);
/*
* Setting variable to avoid resetting PPK pointers
*/
PpkAlreadySet=1;
}
/*
* Increment the pointer by authentication Header size
*/
PpkPtr += RSA_HEADER_SIZE;
/*
* Increment the pointer by Magic word size
*/
PpkPtr += RSA_MAGIC_WORD_SIZE;
/*
* Set pointer to PPK
*/
PpkModular = (u8 *)PpkPtr;
PpkPtr += RSA_PPK_MODULAR_SIZE;
PpkModularEx = (u8 *)PpkPtr;
PpkPtr += RSA_PPK_MODULAR_EXT_SIZE;
PpkExp = *((u32 *)PpkPtr);
return;
}

98
lib/sw_apps/zynq_fsbl/src/rsa.h
View file

@ -65,70 +65,6 @@ extern "C" {
#endif
/***************************** Include Files *********************************/
/*
* Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
* 32-bit digits are approximately 4 times faster
*/
//#define RSA_DIGIT_16
#define RSA_DIGIT_32
/*
* RSA loop unrolling selection
* RSA main loop can be unrolled 2, 4 or 8 ways
*/
#define RSA_UNROLL 1
/*
* Select if ARM-optimized code is to be used. Only GCC for ARM is supported
*/
//#define RSA_ARM_OPTIMIZED
/*
* Check the compatibility of the selection
*/
#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
#error Please select a digit size
#endif
#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
#error Please select just one digit size
#endif
#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
#error Assembly level code is only supported for the GCC/ARM combination
#endif
#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
#error Only 1, 2, 4, and 8 unrolling are supported
#endif
#ifdef RSA_DIGIT_16
#define RSA_DIGIT unsigned short
#define RSA_SDIGIT short
#define RSA_DDIGIT unsigned long
#endif
#ifdef RSA_DIGIT_32
#define RSA_DIGIT unsigned long
#define RSA_SDIGIT long
#define RSA_DDIGIT unsigned long long
#endif
#define RSA_NUMBER RSA_DIGIT *
#define RSA_NBITS 2048
#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
/*
* Double-digit to single digit conversion
*/
#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
#define SHA_BLKSIZE 512
#define SHA_BLKBYTES (SHA_BLKSIZE/8)
#define SHA_BLKWORDS (SHA_BLKBYTES/4)
#define SHA_VALSIZE 256
#define SHA_VALBYTES (SHA_VALSIZE/8)
#define SHA_VALWORDS (SHA_VALBYTES/4)
#define RSA_PPK_MODULAR_SIZE 256
#define RSA_PPK_MODULAR_EXT_SIZE 256
@ -142,40 +78,6 @@ extern "C" {
#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */
#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */
/*
* SHA-256 context structure
* Includes SHA-256 state, coalescing buffer to collect the processed strings, and
* total byte length counter (used both to manage the buffer and for padding)
*/
typedef struct
{
unsigned int state[8];
unsigned char buffer[SHA_BLKBYTES];
unsigned long long bytes;
} sha2_context;
/*
* RSA-2048 user interfaces
*/
void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
const unsigned char *modular_ext, const unsigned char *exponent,
unsigned char *result);
void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
/*
* SHA-256 user interfaces
*/
void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
void sha2_starts(sha2_context *ctx);
void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
void sha2_finish(sha2_context *ctx, unsigned char* output);
/*
* Preprocessing interface (pre-computation of R*R mod M)
*/
void modular_ext(const unsigned char *modular, unsigned char *res);
void SetPpk(void );
u32 AuthenticatePartition(u8 *Buffer, u32 Size);
u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash);