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srio: Add srio standalone driver support.

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This patch adds the SRIO standalone driver support for
SRIO Gen2 Core.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This commit is contained in:
Kedareswara rao Appana 2014-04-19 11:25:11 +05:30 • committed by Jagannadha Sutradharudu Teki
parent 55a9795fc2
commit 234ca56569
10 changed files with 3464 additions and 0 deletions
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55
XilinxProcessorIPLib/drivers/srio/data/srio.mdd Executable file
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##############################################################################
#
# (c) Copyright 2014 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information of Xilinx, Inc.
# and is protected under U.S. and international copyright and other
# intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any rights to the
# materials distributed herewith. Except as otherwise provided in a valid
# license issued to you by Xilinx, and to the maximum extent permitted by
# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
# MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
# and (2) Xilinx shall not be liable (whether in contract or tort, including
# negligence, or under any other theory of liability) for any loss or damage
# of any kind or nature related to, arising under or in connection with these
# materials, including for any direct, or any indirect, special, incidental,
# or consequential loss or damage (including loss of data, profits, goodwill,
# or any type of loss or damage suffered as a result of any action brought by
# a third party) even if such damage or loss was reasonably foreseeable or
# Xilinx had been advised of the possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-safe, or for use in
# any application requiring fail-safe performance, such as life-support or
# safety devices or systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any other applications
# that could lead to death, personal injury, or severe property or
# environmental damage (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and liability of any use of
# Xilinx products in Critical Applications, subject only to applicable laws
# and regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
# AT ALL TIMES.
#
# MODIFICATION HISTORY:
# Ver Who Date Changes
# -------- ------ -------- --------------------------------------------------
# 1.0 adk 16/04/14 Initial release
##############################################################################
OPTION psf_version = 2.1;
BEGIN driver srio
OPTION supported_peripherals = (srio_gen2);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = srio;
END driver

268
XilinxProcessorIPLib/drivers/srio/data/srio.tcl Executable file
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##############################################################################
#
# (c) Copyright 2014 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information of Xilinx, Inc.
# and is protected under U.S. and international copyright and other
# intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any rights to the
# materials distributed herewith. Except as otherwise provided in a valid
# license issued to you by Xilinx, and to the maximum extent permitted by
# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
# MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
# and (2) Xilinx shall not be liable (whether in contract or tort, including
# negligence, or under any other theory of liability) for any loss or damage
# of any kind or nature related to, arising under or in connection with these
# materials, including for any direct, or any indirect, special, incidental,
# or consequential loss or damage (including loss of data, profits, goodwill,
# or any type of loss or damage suffered as a result of any action brought by
# a third party) even if such damage or loss was reasonably foreseeable or
# Xilinx had been advised of the possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-safe, or for use in
# any application requiring fail-safe performance, such as life-support or
# safety devices or systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any other applications
# that could lead to death, personal injury, or severe property or
# environmental damage (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and liability of any use of
# Xilinx products in Critical Applications, subject only to applicable laws
# and regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
# AT ALL TIMES.
#
##############################################################################
##############################################################################
#
# Modification History
#
# Ver Who Date Changes
# ----- ---- -------- -----------------------------------------------
# 1.0 adk 16/04/14 Initial release
#
##############################################################################
#uses "xillib.tcl"
set periph_config_params_srio 0
set periph_ninstances_srio 0
proc init_periph_config_struct_srio { deviceid } {
global periph_config_params_srio
set periph_config_params_srio($deviceid) [list]
}
proc add_field_to_periph_config_struct_srio { deviceid fieldval } {
global periph_config_params_srio
lappend periph_config_params_srio($deviceid) $fieldval
}
proc get_periph_config_struct_fields_srio { deviceid } {
global periph_config_params_srio
return $periph_config_params_srio($deviceid)
}
proc xdefine_srio_include_file {drv_handle file_name drv_string} {
global periph_ninstances
# Open include file
set file_handle [xopen_include_file $file_name]
# Get all peripherals connected to this driver
set periphs [xget_sw_iplist_for_driver $drv_handle]
# Handle NUM_INSTANCES
set periph_ninstances 0
puts $file_handle "/* Definitions for driver [string toupper [get_property NAME $drv_handle]] */"
foreach periph $periphs {
init_periph_config_struct_srio $periph_ninstances
incr periph_ninstances 1
}
puts $file_handle "\#define [xget_dname $drv_string NUM_INSTANCES] $periph_ninstances"
# Now print all useful parameters for all peripherals
set device_id 0
foreach periph $periphs {
puts $file_handle ""
xdefine_srio_params_instance $file_handle $periph $device_id
xdefine_srio_params_canonical $file_handle $periph $device_id
incr device_id
puts $file_handle "\n"
}
puts $file_handle "\n/******************************************************************/\n"
close $file_handle
}
proc xdefine_srio_params_instance {file_handle periph device_id} {
set sriois_memory [get_property CONFIG.C_PE_MEMORY $periph]
if {$sriois_memory == 0} {
set sriois_memory 0
}
set sriois_processor [get_property CONFIG.C_PE_PROC $periph]
if {$sriois_processor == 0} {
set sriois_processor 0
} else {
set sriois_processor 2
}
set sriois_bridge [get_property CONFIG.C_PE_BRIDGE $periph]
if {$sriois_bridge == 0} {
set sriois_bridge 0
} else {
set sriois_bridge 3
}
puts $file_handle "/* Definitions for peripheral [string toupper [get_property NAME $periph]] */"
puts $file_handle "\#define [xget_dname $periph "DEVICE_ID"] $device_id"
set value [get_property CONFIG.C_BASEADDR $periph]
if {[llength $value] == 0} {
set value 0
}
puts $file_handle "\#define [xget_dname $periph "C_BASEADDR"] $value"
set value [get_property CONFIG.C_HIGHADDR $periph]
if {[llength $value] == 0} {
set value 0
}
puts $file_handle "\#define [xget_dname $periph "C_HIGHADDR"] $value"
set value [get_property CONFIG.C_DEVICEID_WIDTH $periph]
if {[llength $value] == 0} {
set value 0
}
puts $file_handle "\#define [xget_dname $periph "C_DEVICEID_WIDTH"] $value"
set value [get_property CONFIG.C_IS_HOST $periph]
if {[llength $value] == 0} {
set value 0
}
puts $file_handle "\#define [xget_dname $periph "C_IS_HOST"] $value"
set value [get_property CONFIG.C_TX_DEPTH $periph]
if {[llength $value] == 0} {
set value 0
}
puts $file_handle "\#define [xget_dname $periph "C_TX_DEPTH"] $value"
set value [get_property CONFIG.C_RX_DEPTH $periph]
if {[llength $value] == 0} {
set value 0
}
puts $file_handle "\#define [xget_dname $periph "C_RX_DEPTH"] $value"
set value [get_property CONFIG.C_DISCOVERED $periph]
if {[llength $value] == 0} {
set value 0
}
puts $file_handle "\#define [xget_dname $periph "C_DISCOVERED"] $value"
puts $file_handle "\#define [xget_dname $periph "PE_MEMORY"] $sriois_memory"
puts $file_handle "\#define [xget_dname $periph "PE_PROC"] $sriois_processor"
puts $file_handle "\#define [xget_dname $periph "PE_BRIDGE"] $sriois_bridge"
}
proc xdefine_srio_params_canonical {file_handle periph device_id} {
set sriois_memory [get_property CONFIG.C_PE_MEMORY $periph]
if {$sriois_memory == 0} {
set sriois_memory 0
}
set sriois_processor [get_property CONFIG.C_PE_PROC $periph]
if {$sriois_processor == 0} {
set sriois_processor 0
} else {
set sriois_processor 2
}
set sriois_bridge [get_property CONFIG.C_PE_BRIDGE $periph]
if {$sriois_bridge == 0} {
set sriois_bridge 0
} else {
set sriois_bridge 3
}
puts $file_handle "\n/* Canonical definitions for peripheral [string toupper [get_property NAME $periph]] */"
set canonical_tag [string toupper [format "XPAR_SRIO_%d" $device_id]]
# Handle device ID
set canonical_name [format "%s_DEVICE_ID" $canonical_tag]
puts $file_handle "\#define $canonical_name $device_id"
add_field_to_periph_config_struct_srio $device_id $canonical_name
set canonical_name [format "%s_BASEADDR" $canonical_tag]
set value [get_property CONFIG.C_BASEADDR $periph]
if {[llength $value] == 0} {
set value 0
}
puts $file_handle "\#define $canonical_name $value"
add_field_to_periph_config_struct_srio $device_id $canonical_name
set canonical_name [format "%s_PE_MEMORY" $canonical_tag]
puts $file_handle "\#define $canonical_name $sriois_memory"
add_field_to_periph_config_struct_srio $device_id $canonical_name
set canonical_name [format "%s_PE_PROC" $canonical_tag]
puts $file_handle "\#define $canonical_name $sriois_processor"
add_field_to_periph_config_struct_srio $device_id $canonical_name
set canonical_name [format "%s_PE_BRIDGE" $canonical_tag]
puts $file_handle "\#define $canonical_name $sriois_bridge"
add_field_to_periph_config_struct_srio $device_id $canonical_name
}
proc xdefine_srio_config_file {file_name drv_string} {
global periph_ninstances
set filename [file join "src" $file_name]
file delete $filename
set config_file [open $filename w]
xprint_generated_header $config_file "Driver configuration"
puts $config_file "\#include \"xparameters.h\""
puts $config_file "\#include \"[string tolower $drv_string].h\""
puts $config_file "\n/*"
puts $config_file "* The configuration table for devices"
puts $config_file "*/\n"
puts $config_file [format "%s_Config %s_ConfigTable\[\] =" $drv_string $drv_string]
puts $config_file "\{"
set start_comma ""
for {set i 0} {$i < $periph_ninstances} {incr i} {
puts $config_file [format "%s\t\{" $start_comma]
set comma ""
foreach field [get_periph_config_struct_fields_srio $i] {
puts -nonewline $config_file [format "%s\t\t%s" $comma $field]
set comma ",\n"
}
puts -nonewline $config_file "\n\t\}"
set start_comma ",\n"
}
puts $config_file "\n\};\n"
close $config_file
}
proc generate {drv_handle} {
xdefine_srio_include_file $drv_handle "xparameters.h" "XSrio"
xdefine_srio_config_file "xsrio_g.c" "XSrio"
}

17
XilinxProcessorIPLib/drivers/srio/examples/index.html Executable file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
<html>
<head>
<meta http-equiv="Content-Language" content="en-us">
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
<title>Driver example applications</title>
<link rel="stylesheet" type="text/css" href="../help.css">
</head>
<body bgcolor="#FFFFFF">
<h1> Example Applications for the driver srio_v1_0 </h1>
<HR>
<ul>
<li>xsrio_dma_loopback_example.c <a href="xsrio_dma_loopback_example.c">(source)</a> </li>
</ul>
<p><font face="Times New Roman" color="#800000">Copyright © 2014 Xilinx, Inc. All rights reserved.</font></p>
</body>
</html>

315
XilinxProcessorIPLib/drivers/srio/examples/xsrio_dma_loopback_example.c Executable file
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/******************************************************************************
*
* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsrio_dma_loopback_example.c
*
* This file demonstrates how to use xsrio driver on the Xilinx SRIO Gen2 Core.
* The SRIO Gen2 comprised of phy, logical and transport and buffer layers.
* Using this IP We can generate both messaging and read/write semantics.
*
* This example demonstartes how to generate SWRITE(Streaming Write)
* transactions on the core.
*
* Inorder to test this example external loopback is required at the boardlevel
* Between the SRIO Tx and Rx pins.
*
* H/W Requirments:
* Inorder to test this example at the h/w level the the SRIO Initiator Request
* is connected to the AXI DMA MM2S Channel and SRIO Target Request is connected
* to the AXI DMA S2MM Channel.
*
* S/W Flow:
* 1) The system consists of two different memories.Processor runs this example
* Code in one memory and the SRIO packet is formed in another memory.
* 2) The SRIO Packet is framed in the Memory
* 3) Configure the AXI DMA MM2S source address and S2MM for Destiantion address
* and specify the byte count for both the channels and then start the dma.
* 4) Compare the Data.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 adk 16/04/14 Initial release
*
* </pre>
*
* ***************************************************************************
*/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xil_printf.h"
#include "xil_types.h"
#include "xstatus.h"
#include "xsrio.h"
#include "xbram.h"
#include "xaxidma.h"
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define SRIO_DEVICE_ID XPAR_SRIO_0_DEVICE_ID
#define MEM_ADDR XPAR_AXI_BRAM_CTRL_1_S_AXI_BASEADDR
#define DMA_DEV_ID XPAR_AXIDMA_0_DEVICE_ID
#define DATA_SIZE 256
/******************** Variable Definitions **********************************/
XSrio Srio; /* Instance of the XSrio */
XAxiDma AxiDma; /* Instance of the XAxiDma */
/******************** Function Prototypes ************************************/
int XSrioDmaLoopbackExample(XSrio *InstancePtr, u16 DeviceId);
/*****************************************************************************/
/**
*
* Main function
*
* This function is the main entry of the SRIO DMA Loopback test.
*
* @param None
*
* @return - XST_SUCCESS if tests pass
* - XST_FAILURE if fails.
*
* @note None
*
******************************************************************************/
int main()
{
int Status;
xil_printf("Entering main\n\r");
Status = XSrioDmaLoopbackExample(&Srio, SRIO_DEVICE_ID);
if (Status != XST_SUCCESS) {
xil_printf("SRIO DMA Loopback Test Failed\n\r");
xil_printf("--- Exiting main() ---\n\r");
return XST_FAILURE;
}
xil_printf("SRIO DMA Loopback Test passed\n\r");
xil_printf("--- Exiting main() ---\n\r");
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* XSrioDmaLoopbackExample This function does a minimal test on the XSrio device
* and driver as a design example. The purpose of this function is to illustrate
* how to use the XSrio Component.
*
* This function does the following:
* - Initialize the SRIO device
* - Initialize the DMA engine
* - Clearing the Memory
* - Framing the SRIO Packet in the Memory
* - Configuring the SRIO
* - Configuring the DMA
* - Verifying the Data
*
* @param InstancePtr is a pointer to the instance of the
* XSrio driver.
* @param DeviceId is Device ID of the SRIO Gen2 Device.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XSrioDmaLoopbackExample(XSrio *InstancePtr, u16 DeviceId)
{
XSrio_Config *SrioConfig;
XAxiDma_Config *DmaConfig;
int Status = XST_SUCCESS;
int Count = 0;
/* Initialize the SRIO Device Configuration Interface driver */
SrioConfig = XSrio_LookupConfig(DeviceId);
if (!SrioConfig) {
xil_printf("No SRIO config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/**< This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XSrio_CfgInitialize(InstancePtr, SrioConfig,
SrioConfig->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed for SRIO\n\r");
return Status;
}
/* Check for PE Configuration */
Status = XSrio_GetPEType(InstancePtr);
if (Status != XSRIO_IS_MEMORY) {
xil_printf("SRIO is not configured as the Memory \n\r");
return XST_FAILURE;
}
/* Clearing the Memory */
for(Count=0; Count<(128*1024); Count += 4) {
*(u32 *)(MEM_ADDR + Count) = 0;
}
/**< Check whether Streaming Write Operation is Supported by the
* Core or not Since it is a loopback Example Checking at the both
* Target and source Operations.
*/
Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
XSRIO_DIR_TX);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
XSRIO_DIR_RX);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/**< Frame the SRIO Write-Stream Packet in the Memory
* The Packet-format used here is HELLO Packet format
* More details look into pg 3.1 version:73 page(HELLO PACKET FORMAT).
*/
*(u32 *)(MEM_ADDR + 0x00) = 0x50000600; /**< Lower word of the
* HELLO Packet
*/
*(u32 *)(MEM_ADDR + 0x04) = 0x08602F74; /**< Upper word of the
* HELLO packet
*/
Count = 8;
while(Count<(DATA_SIZE * 2)) {
*(u32 *)(MEM_ADDR + Count) = Count;
Count += 4;
}
/* SRIO Configuration */
/* Set the Local Configuration Space Base Address */
XSrio_SetLCSBA(InstancePtr, 0xFFF);
/* Set the Water Mark Level to transfer priority 0 packet */
XSrio_SetWaterMark0(InstancePtr, 0x5);
/* Set the Water Mark Level to transfer priority 1 packet */
XSrio_SetWaterMark1(InstancePtr, 0x4);
/* Set the Water Mark Level to transfer priority 2 packet */
XSrio_SetWaterMark2(InstancePtr, 0x3);
/* Set the Port Response timeout value */
XSrio_SetPortRespTimeOutValue(InstancePtr, 0x010203);
/* DMA Configuration */
DmaConfig = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!DmaConfig) {
xil_printf("No DMA config found for %d\r\n", DMA_DEV_ID);
return XST_FAILURE;
}
/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, DmaConfig);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
/**< Configure the DMA Tx Side
* MEM_ADDR is the address where Tx packet is formed
*/
XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_CR_OFFSET,
XAXIDMA_CR_RUNSTOP_MASK);
XAxiDma_IntrEnable(&AxiDma,XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_SRCADDR_OFFSET, MEM_ADDR);
/**< Configure the DMA Rx Side
* MEM_ADDR+0x5000 is the address where Rx packet is formed
*/
XAxiDma_WriteReg(DmaConfig->BaseAddr,
XAXIDMA_RX_OFFSET+XAXIDMA_CR_OFFSET, XAXIDMA_CR_RUNSTOP_MASK);
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
XAxiDma_WriteReg(DmaConfig->BaseAddr,
XAXIDMA_RX_OFFSET + XAXIDMA_DESTADDR_OFFSET, MEM_ADDR+0x5000);
for(Count=8; Count<DATA_SIZE; Count += 4) {
*(u32 *)(MEM_ADDR + Count) = Count;
}
XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_BUFFLEN_OFFSET, 256);
/* Wait till DMA MM2S Transfer Complete */
while(!(XAxiDma_ReadReg(DmaConfig->BaseAddr, XAXIDMA_SR_OFFSET)
& 0x1000));
XAxiDma_WriteReg(DmaConfig->BaseAddr,
XAXIDMA_RX_OFFSET+XAXIDMA_BUFFLEN_OFFSET, 256);
/* Wait till S2MM Transfer Complete */
while(!( XAxiDma_ReadReg(DmaConfig->BaseAddr,
XAXIDMA_RX_OFFSET+XAXIDMA_SR_OFFSET) & 0x1000));
/* Verifying the Data */
for(Count=8; Count<DATA_SIZE; Count += 4) {
if(*(u32 *)(MEM_ADDR + 0x5000 + Count)
!= *(u32 *)(MEM_ADDR + Count)) {
xil_printf("\n ERROR in Transfer\n\r");
return XST_FAILURE;
}
}
/* Clearing the Memory */
for(Count=0x5000; Count<(0x6000); Count += 4) {
*(u32 *)(MEM_ADDR + Count) = 0;
}
for(Count=0; Count<DATA_SIZE; Count += 4) {
if(*(u32 *)(MEM_ADDR + 0x5000+ Count) != 0x00) {
xil_printf("\n ERROR in Clearing Memory\n\r");
return XST_FAILURE;
}
}
return Status;
}

29
XilinxProcessorIPLib/drivers/srio/src/Makefile Executable file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
LEVEL=0
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling srio"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

244
XilinxProcessorIPLib/drivers/srio/src/xsrio.c Executable file
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/******************************************************************************
*
* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a Result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsrio.c
* This file contains the required functions for the XSrio driver. See the
* xsrio.h header file for more details on this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 adk 16/04/14 Initial release
* </pre>
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsrio.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
* Initialize the XSrio instance provided by the caller based on the
* given Config structure.
*
* @param InstancePtr is the XSrio instance to operate on.
* @param Config is the device configuration structure containing
* information about a specific SRIO Device.
* @param EffectiveAddress is the Physical address of the hardware in a
* Virtual Memory operating system environment.It is the Base
* Address in a stand alone environment.
*
* @return
* - XST_SUCCESS Initialization was successful.
*
* @note None.
*****************************************************************************/
int XSrio_CfgInitialize(XSrio *InstancePtr,
XSrio_Config *Config, u32 EffectiveAddress)
{
u32 Portwidth;
InstancePtr->IsReady = 0;
/* Setup the instance */
memset(InstancePtr, 0, sizeof(XSrio));
InstancePtr->Config.BaseAddress = EffectiveAddress;
InstancePtr->Config.DeviceId = Config->DeviceId;
/* Initialization is successful */
InstancePtr->IsReady = 1;
/* Configuration of the Device */
InstancePtr->Config.IsPEMemory = Config->IsPEMemory;
InstancePtr->Config.IsPEProcessor = Config->IsPEProcessor;
InstancePtr->Config.IsPEBridge = Config->IsPEBridge;
/* Port width for the Device */
Portwidth = XSrio_ReadReg(InstancePtr->Config.BaseAddress,
XSRIO_PORT_N_ERR_STS_CSR_OFFSET + XSRIO_PORT_N_CTL_CSR_OFFSET);
InstancePtr->PortWidth = ((Portwidth & XSRIO_PORT_N_CTL_PW_CSR_MASK) >>
XSRIO_PORT_N_CTL_PW_CSR_SHIFT);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* XSrio_GetPortStatus will check the status of the port and returns the status
* of the port to the user
*
* @param InstancePtr is the XSrio instance to operate on.
*
* @return
* - XSRIO_PORT_OK Port is initialized with no errors.
* - XSRIO_PORT_UNINITIALIZED Port is not intilized.
* No Serial Rapidio link is present.
* - XSRIO_PORT_HAS_ERRORS Port is initialized but has errors.
*
* @note: None.
*
****************************************************************************/
int XSrio_GetPortStatus(XSrio *InstancePtr)
{
u32 Result;
Xil_AssertNonvoid(InstancePtr != NULL);
Result = XSrio_ReadReg(InstancePtr->Config.BaseAddress,
XSRIO_PORT_N_ERR_STS_CSR_OFFSET);
if(Result & XSRIO_PORT_N_ERR_STS_POK_CSR_MASK)
Result = XSRIO_PORT_OK;
else if(Result & XSRIO_PORT_N_ERR_STS_PUINT_CSR_MASK)
Result = XSRIO_PORT_UNINITIALIZED;
else if(Result & XSRIO_PORT_N_ERR_STS_PERR_CSR_MASK)
Result = XSRIO_PORT_HAS_ERRORS;
return Result;
}
/*****************************************************************************/
/**
* XSrio_GetPEType API will check for the Processing Element type and
* return the type of type of Processing Element
*
* @param InstancePtr is the XSrio instance to operate on.
*
* @return
* - XSRIO_IS_MEMORY if the core is configured as a memory
* - XSRIO_IS_PROCESSOR if the core is configured as a processor
* - XSRIO_IS_BRIDGE if the core is configured as a bridge.
*
* @note: None.
*
*****************************************************************************/
int XSrio_GetPEType(XSrio *InstancePtr)
{
int Result;
Xil_AssertNonvoid(InstancePtr != NULL);
Result = XSrio_ReadReg(InstancePtr->Config.BaseAddress,
XSRIO_PEF_CAR_OFFSET);
if(Result & XSRIO_PEF_MEMORY_CAR_MASK)
Result = XSRIO_IS_MEMORY;
else if(Result & XSRIO_PEF_PROCESSOR_CAR_MASK)
Result = XSRIO_IS_PROCESSOR;
else if(Result & XSRIO_PEF_BRIDGE_CAR_MASK)
Result = XSRIO_IS_BRIDGE;
return Result;
}
/*****************************************************************************/
/**
* XSrio_IsOperationSupported tells whether the operation is supported by the
* SRIO Gen2 core or not.
*
*
* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
* worked on.
* @param Operation type is the operation type of the SRIO Packet
* @param Direction type
*
* @return
* - XST_SUCCESS if the operation is supported by the core.
* - XST_FAILURE if the operation is not supported by the core.
*
* @note None.
*
*****************************************************************************/
int XSrio_IsOperationSupported(XSrio *InstancePtr, u8 Operation, u8 Direction)
{
u32 OperationCar;
u32 Status = XST_FAILURE;
Xil_AssertNonvoid(InstancePtr != NULL);
if (Direction & XSRIO_DIR_TX) {
OperationCar = XSrio_ReadSrcOps(InstancePtr);
} else {
OperationCar = XSrio_ReadDstOps(InstancePtr);
}
switch (Operation) {
case XSRIO_OP_MODE_NREAD:
if(OperationCar & XSRIO_SRCDST_OPS_READ_CAR_MASK)
Status = XST_SUCCESS;
break;
case XSRIO_OP_MODE_NWRITE:
if(OperationCar & XSRIO_SRCDST_OPS_WRITE_CAR_MASK)
Status = XST_SUCCESS;
break;
case XSRIO_OP_MODE_SWRITE:
if(OperationCar & XSRIO_SRCDST_OPS_SWRITE_CAR_MASK)
Status = XST_SUCCESS;
break;
case XSRIO_OP_MODE_NWRITE_R:
if(OperationCar & XSRIO_SRCDST_OPS_WRITE_RESPONSE_CAR_MASK)
Status = XST_SUCCESS;
break;
case XSRIO_OP_MODE_DATA_MESSAGE:
if(OperationCar & XSRIO_SRCDST_OPS_DATA_MSG_CAR_MASK)
Status = XST_SUCCESS;
break;
case XSRIO_OP_MODE_DOORBELL:
if(OperationCar & XSRIO_SRCDST_OPS_DOORBELL_CAR_MASK)
Status = XST_SUCCESS;
break;
case XSRIO_OP_MODE_ATOMIC:
if(OperationCar & XSRIO_SRCDST_OPS_ATOMIC_SET_CAR_MASK)
Status = XST_SUCCESS;
break;
default:
Status = XST_FAILURE;
}
return Status;
}

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77
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/******************************************************************************
*
* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsrio_g.c
*
* This file contains a configuration table that specifies the configuration of
* SRIO devices in the system. Each SRIO device in the system should have an entry
* in the table.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 adk 16/04/14 Initial release
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xsrio.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
XSrio_Config XSrio_ConfigTable[] =
{
{
XPAR_SRIO_0_DEVICE_ID,
XPAR_SRIO_0_BASEADDR,
XPAR_SRIO_0_PE_MEMORY,
XPAR_SRIO_0_PE_PROC,
XPAR_SRIO_0_PE_BRIDGE
}
};

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/******************************************************************************
*
* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/**
*
* @file xsrio_hw.h
*
* This header file contains identifiers and macros that can be used to access
* the Axi srio gen2 device. The driver APIs/functions are defined in
* xsrio.h.
*
* @note
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 adk 16/04/14 Initial release.
*
******************************************************************************/
#ifndef XSRIO_HW_H /* prevent circular inclusions */
#define XSRIO_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#include "xil_io.h"
/*
* Register offset definitions. Unless otherwise noted, register access is
* 32 bit.
*/
/** @name Device registers
* @{
*/
/**
* Capability Address Register Space 0x00-0x3C Resisters
*/
#define XSRIO_DEV_ID_CAR_OFFSET 0x00 /**< Device Identity CAR */
#define XSRIO_DEV_INFO_CAR_OFFSET 0x04 /**< Device Information CAR */
#define XSRIO_ASM_ID_CAR_OFFSET 0x08 /**< Assembly Identity CAR */
#define XSRIO_ASM_INFO_CAR_OFFSET 0x0C /**< Assembly Information CAR */
#define XSRIO_PEF_CAR_OFFSET 0x10 /**< Processing Element
* Features CAR
*/
#define XSRIO_SWP_INFO_CAR_OFFSET 0x14 /**< Switch Port Information CAR */
#define XSRIO_SRC_OPS_CAR_OFFSET 0x18 /**< Source operations CAR */
#define XSRIO_DST_OPS_CAR_OFFSET 0x1c /**< Destination operations CAR */
/**
* Command and Status Register Space 0x040-0xFC Registers
*/
#define XSRIO_PELL_CTRL_CSR_OFFSET 0x4c /**< PE Logical layer
* Control CSR
*/
#define XSRIO_LCS0_BASEADDR_CSR_OFFSET 0x58 /**< Local Configuration
* Space 0 Base Address CSR
*/
#define XSRIO_LCS1_BASEADDR_CSR_OFFSET 0x5c /**< Local Configuration
* Space 1 Base Address CSR
*/
#define XSRIO_BASE_DID_CSR_OFFSET 0x60 /**< Base Device ID CSR */
#define XSRIO_HOST_DID_LOCK_CSR_OFFSET 0x68 /**< Host Base Device ID
* Lock CSR
*/
#define XSRIO_COMPONENT_TAG_CSR_OFFSET 0x6c /**< Component Tag CSR */
/**
* Extended Feature Register Space 0x0100-0xFFFC Registers
*/
#define XSRIO_EFB_HEADER_OFFSET 0x100 /**< Extended features LP Serial
* Register Block Header
*/
#define XSRIO_PORT_TOUT_CSR_OFFSET 0x120 /**< Port Link Timeout CSR */
#define XSRIO_RSP_TOUT_CSR_OFFSET 0x124 /**< Port Response Timeout CSR */
#define XSRIO_GEN_CTL_CSR_OFFSET 0x13c /**< General Control CSR */
#define XSRIO_PORT_N_MNT_REQ_CSR_OFFSET 0x140 /**< Port n Link Maintenance
* Request CSR
*/
#define XSRIO_PORT_N_MNT_RES_CSR_OFFSET 0X144 /**< Port n Maintenance
* Response CSR
*/
#define XSRIO_PORT_N_ACKID_CSR_OFFSET 0x148 /**< Port n Local Ack ID CSR */
#define XSRIO_PORT_N_ERR_STS_CSR_OFFSET 0x158 /**< Port n Error and
* Status CSR
*/
#define XSRIO_PORT_N_CTL_CSR_OFFSET 0x15c /**< Port n Control CSR */
#define XSRIO_EFB_LPSL_OFFSET 0x0400 /**< LP-Serial Lane Extended
* Features offset
*/
#define XSRIO_SL_HEADER_OFFSET 0x00 /**< Serial Lane Block Header */
#define XSRIO_SLS0_CSR_OFFSET(x) (0x10 + x*0x20)
/**< Serial Lane N
* Status 0 CSR
*/
#define XSRIO_SLS1_CSR_OFFSET(x) (0x14 + x*0x20)
/**< Serial Lane N
* Status 1 CSR
*/
/**
* Implementation Defined Space 0x010000 - 0xFFFFFC Registers
*/
#define XSRIO_IMP_WCSR_OFFSET 0x10000 /**< Water Mark CSR */
#define XSRIO_IMP_BCSR_OFFSET 0x10004 /**< Buffer Control CSR */
#define XSRIO_IMP_MRIR_OFFSET 0x10100 /**< Maintenace Request
* Information Register
*/
/*@}*/
/** @name Device Identity CAR bit definitions.
* These bits are associated with the XSRIO_DEV_ID_CAR_OFFSET register.
* @{
*/
#define XSRIO_DEV_ID_DEVID_CAR_MASK 0xFFFF0000 /**< Device ID Mask */
#define XSRIO_DEV_ID_VDRID_CAR_MASK 0x0000FFFF /**< Device Vendor ID Mask */
#define XSRIO_DEV_ID_DEVID_CAR_SHIFT 16 /**< Device ID shift */
/*@}*/
/** @name Device Inforamtion CAR bit definitions.
* These bits are associated with the XSRIO_DEV_INFO_CAR_OFFSET register.
* @{
*/
#define XSRIO_DEV_INFO_PATCH_CAR_MASK 0x0000000F /**< Patch Mask */
#define XSRIO_DEV_INFO_MINREV_CAR_MASK 0x000000F0 /**< Minor Revision Mask */
#define XSRIO_DEV_INFO_MAJREV_CAR_MASK 0x00000F00 /**< Major Revision Mask */
#define XSRIO_DEV_INFO_DREV_CAR_MASK 0x000F0000 /**< Device Revision
* Lable Mask
*/
/*@}*/
/** @name Assembly Identity CAR bit definitions.
* These bits are associated with the XSRIO_ASM_ID_CAR_OFFSET register.
* @{
*/
#define XSRIO_ASM_ID_ASMID_CAR_MASK 0xFFFF0000 /**< Assembly ID Mask */
#define XSRIO_ASM_ID_ASMVID_CAR_MASK 0x0000FFFF /**< Assembly Vendor ID Mask */
#define XSRIO_ASM_ID_ASMID_CAR_SHIFT 16 /**< Assembly ID Shift */
/*@}*/
/** @name Assembly Device Information CAR bit definitions.
* These bits are associated with the XSRIO_ASM_INFO_CAR_OFFSET register.
* @{
*/
#define XSRIO_ASM_INFO_ASR_CAR_MASK 0xFFFF0000 /**< Assembly Revision Mask */
#define XSRIO_ASM_INFO_EFP_CAR_MASK 0x0000FFFF /**< Extended Features
* Pointer Mask
*/
#define XSRIO_ASM_INFO_ASR_CAR_SHIFT 16 /**< Assembly Revision Shift */
/*@}*/
/** @name Processing Element Features CAR bit definitions.
* These bits are associated with the XSRIO_PEF_CAR_OFFSET register.
* @{
*/
#define XSRIO_PEF_EAS_CAR_MASK 0x00000007 /**< Extended Addressing
* Support Mask
*/
#define XSRIO_PEF_EF_CAR_MASK 0x00000008 /**< Extended Features Mask */
#define XSRIO_PEF_CTS_CAR_MASK 0x00000010 /**< Common Transport Large
* System support Mask
*/
#define XSRIO_PEF_CRF_CAR_MASK 0x00000020 /**< CRF Support Mask */
#define XSRIO_PEF_MPORT_CAR_MASK 0x08000000 /**< Multi Port Mask */
#define XSRIO_PEF_SWITCH_CAR_MASK 0x10000000 /**< Switch Mask */
#define XSRIO_PEF_PROCESSOR_CAR_MASK 0x20000000 /**< Processor Mask */
#define XSRIO_PEF_MEMORY_CAR_MASK 0x40000000 /**< Memory Mask */
#define XSRIO_PEF_BRIDGE_CAR_MASK 0x80000000 /**< Bridge Mask */
/*@}*/
/** @name Source Operations CAR bit definitions.
* These bits are associated with the XSRIO_SRC_OPS_CAR_OFFSET
* register and XSRIO_DST_OPS_CAR register.
* @{
*/
#define XSRIO_SRCDST_OPS_PORT_WRITE_CAR_MASK 0x00000004 /**< Port write
* operation Mask
*/
#define XSRIO_SRCDST_OPS_ATOMIC_SWP_CAR_MASK 0x00000008 /**< Atomic Swap
* Mask
*/
#define XSRIO_SRCDST_OPS_ATOMIC_CLR_CAR_MASK 0x00000010 /**< Atomic Clear
* Mask
*/
#define XSRIO_SRCDST_OPS_ATOMIC_SET_CAR_MASK 0x00000020 /**< Atomic Set
* Mask
*/
#define XSRIO_SRCDST_OPS_ATOMIC_DCR_CAR_MASK 0x00000040 /**< Atomic
* Decrement Mask
*/
#define XSRIO_SRCDST_OPS_ATOMIC_INCR_CAR_MASK 0x00000080 /**< Atomic
* Increment Mask
*/
#define XSRIO_SRCDST_OPS_ATOMIC_TSWP_CAR_MASK 0x00000100 /**< Atomic test
* and swap Mask
*/
#define XSRIO_SRCDST_OPS_ATIOMIC_CSWP_CAR_MASK 0x00000200 /**< Atomic compare
* and Swap Mask
*/
#define XSRIO_SRCDST_OPS_DOORBELL_CAR_MASK 0x00000400 /**< Doorbell Mask */
#define XSRIO_SRCDST_OPS_DATA_MSG_CAR_MASK 0x00000800 /**< Data Message
* Mask
*/
#define XSRIO_SRCDST_OPS_WRITE_RESPONSE_CAR_MASK 0x00001000 /**< Write with
* Response Mask
*/
#define XSRIO_SRCDST_OPS_SWRITE_CAR_MASK 0x00002000 /**< Streaming
* Write Mask
*/
#define XSRIO_SRCDST_OPS_WRITE_CAR_MASK 0x00004000 /**< Write Mask */
#define XSRIO_SRCDST_OPS_READ_CAR_MASK 0x00008000 /**< Read Mask */
/*@}*/
/** @name PE Logical layer Control CSR bit definitions.
* These bits are associated with the XSRIO_PELL_CTRL_CSR_OFFSET register.
* @{
*/
#define XSRIO_PELL_CTRL_EAC_CSR_MASK 0x00000007 /**< Extended Addressing
* Control Mask
*/
/*@}*/
/** @name Local Configuration Space Base Address 1 CSR bit definitions.
* These bits are associated with the XSRIO_LCS1_BASEADDR_CSR_OFFSET register.
* @{
*/
#define XSRIO_LCS1_BASEADDR_LCSBA_CSR_MASK 0x7FE00000 /**< LCSBA Mask */
#define XSRIO_LCS1_BASEADDR_LCSBA_CSR_SHIFT 21 /**< LCSBA Shift */
/*@}*/
/** @name Base Device ID CSR bit definitions.
* These bits are associated with the XSRIO_BASE_DID_CSR_OFFSET register.
* @{
*/
#define XSRIO_BASE_DID_LBDID_CSR_MASK 0x0000FFFF /**< Large Base Device ID
* Mask(16-bit device ID)
*/
#define XSRIO_BASI_DID_BDID_CSR_MASK 0x00FF0000 /**< Base Device ID
* Mask(8-bit device ID)
*/
#define XSRIO_BASI_DID_BDID_CSR_SHIFT 16 /**< Base Device ID Shift */
/*@}*/
/** @name Host Base Device ID CSR bit definitions.
* These bits are associated with the XSRIO_HOST_DID_LOCK_CSR_OFFSET register.
* @{
*/
#define XSRIO_HOST_DID_LOCK_HBDID_CSR_MASK 0x0000FFFF /**< Host Base
* Device ID Mask
*/
/*@}*/
/** @name LP - Serial Register Block header bit definitions.
* These bits are associated with the XSRIO_EFB_HEADER_OFFSET register.
* @{
*/
#define XSRIO_EFB_HEADER_EFID_MASK 0x0000FFFF /**< Extended Features ID
* Mask
*/
#define XSRIO_EFB_HEADER_EFP_MASK 0xFFFF0000 /**< Extended Features
* Pointer Mask
*/
#define XSRIO_EFB_HEADER_EFP_SHIFT 16 /**< Extended Features
* Pointer Shift
*/
/*@}*/
/** @name Port Link timeout value CSR bit definitions.
* These bits are associated with the XSRIO_PORT_TOUT_CSR_OFFSET register.
* @{
*/
#define XSRIO_PORT_TOUT_TOUTVAL_CSR_MASK 0xFFFFFF00 /**< Timeout Value Mask */
#define XSRIO_PORT_TOUT_TOUTVAL_CSR_SHIFT 8 /**< Timeout Value Shift */
/*@}*/
/** @name Port response timeout value CSR bit definitions.
* These bits are associated with the XSRIO_RSP_TOUT_CSR_OFFSET register.
* @{
*/
#define XSRIO_RSP_TOUT_TOUTVAL_CSR_MASK 0xFFFFFF00 /**< Response Timeout
* Value Mask
*/
#define XSRIO_RSP_TOUT_TOUTVAL_CSR_SHIFT 8 /**< Response Timeout Shift */
/*@}*/
/** @name Port General Control CSR bit definitions.
* These bits are associated with the XSRIO_GEN_CTL_CSR_OFFSET register.
* @{
*/
#define XSRIO_GEN_CTL_DISCOVERED_CSR_MASK 0x20000000 /**< Discovered Mask */
#define XSRIO_GEN_CTL_MENABLE_CSR_MASK 0x40000000 /**< Master Enable Mask */
#define XSRIO_GEN_CTL_HOST_CSR_MASK 0x80000000 /**< Host Mask */
/*@}*/
/** @name Port n maintenance request CSR bit definitions.
* These bits are associated with the XSRIO_PORT_N_MNT_REQ_CSR_OFFSET register.
* @{
*/
#define XSRIO_PORT_N_MNT_REQ_CMD_CSR_MASK 0x00000007 /**< Command Mask */
/*@}*/
/** @name Port n maintenance response CSR bit definitions.
* These bits are associated with the XSRIO_PORT_N_MNT_RES_CSR_OFFSET register.
* @{
*/
#define XSRIO_PORT_N_MNT_RES_LS_CSR_MASK 0x0000001F /**< link status Mask */
#define XSRIO_PORT_N_MNT_RES_ACKS_CSR_MASK 0x000007E0 /**< Ack ID status
* Mask
*/
#define XSRIO_PORT_N_MNT_RES_RVALID_CSR_MASK 0x80000000 /**< Response Valid
* Mask
*/
/*@}*/
/** @name Port n local ack ID CSR bit definitions.
* These bits are associated with the XSRIO_PORT_N_ACKID_CSR_OFFSET register.
* @{
*/
#define XSRIO_PORT_N_ACKID_OBACKID_CSR_MASK 0x0000003F /**< Out bound
* ACK ID Mask
*/
#define XSRIO_PORT_N_ACKID_OSACKID_CSR_MASK 0x00003F00 /**< Out Standing
* ACK ID Mask
*/
#define XSRIO_PORT_N_ACKID_IBACKID_CSR_MASK 0x3F000000 /**< In bound
* ACK ID Mask
*/
#define XSRIO_PORT_N_ACKID_CLSACKID_CSR_MASK 0x80000000 /**< Clear
* Outstanding
* ACK ID Mask
*/
#define XSRIO_PORT_N_ACKID_RESET_OBACKID_CSR_MASK 0xFFFFFFC0 /**< Out bound ACK
* ID Reset Mask
*/
#define XSRIO_PORT_N_ACKID_RESET_IBACKID_CSR_MASK 0xC0FFFFFF /**< In bound ACK
* ID Reset Mask
*/
#define XSRIO_PORT_N_ACKID_IBACKID_CSR_SHIFT 24 /**< In bound
* ACK ID shift
*/
/*@}*/
/** @name Port n Error and Status CSR bit definitions.
* These bits are associated with the XSRIO_PORT_N_ERR_STS_CSR_OFFSET register.
* @{
*/
#define XSRIO_PORT_N_ERR_STS_PUINT_CSR_MASK 0x00000001 /**< Port
* un-initialized Mask
*/
#define XSRIO_PORT_N_ERR_STS_POK_CSR_MASK 0x00000002 /**< Port Ok Mask */
#define XSRIO_PORT_N_ERR_STS_PERR_CSR_MASK 0x00000004 /**< Port Error Mask */
#define XSRIO_PORT_N_ERR_STS_IERRS_CSR_MASK 0x00000100 /**< Input Error
* stopped Mask
*/
#define XSRIO_PORT_N_ERR_STS_IERRE_CSR_MASK 0x00000200 /**< Input Error
* encountered Mask
*/
#define XSRIO_PORT_N_ERR_STS_IRTS_CSR_MASK 0x00000400 /**< Input Retry
* Stopped Mask
*/
#define XSRIO_PORT_N_ERR_STS_OERRS_CSR_MASK 0x00010000 /**< Output error
* Stopped Mask
*/
#define XSRIO_PORT_N_ERR_STS_OERRE_CSR_MASK 0x00020000 /**< Output error
* encountered Mask
*/
#define XSRIO_PORT_N_ERR_STS_ORTS_CSR_MASK 0x00040000 /**< Output Retry
* Stopped Mask
*/
#define XSRIO_PORT_N_ERR_STS_OR_CSR_MASK 0x00080000 /**< Output
* Retried Mask
*/
#define XSRIO_PORT_N_ERR_STS_ORE_CSR_MASK 0x00100000 /**< Output Retry
* Encountered Mask
*/
#define XSRIO_PORT_N_ERR_STS_FLOWCNTL_CSR_MASK 0x08000000 /**< Flow Control
* Mode Mask
*/
#define XSRIO_PORT_N_ERR_STS_IDL_SEQ_CSR_MASK 0x20000000 /**< Idle sequence
* Mask
*/
#define XSRIO_PORT_N_ERR_STS_IDL_SEQE_CSR_MASK 0x40000000 /**< Idle sequence 2
* Enable Mask
*/
#define XSRIO_PORT_N_ERR_STS_IDL_SEQS_CSR_MASK 0x80000000 /**< Idle sequence 2
* support Mask
*/
#define XSRIO_PORT_N_ERR_STS_ERR_ALL_CSR_MASK 0x001FFF07 /**< Port Errors Mask */
/*@}*/
/** @name Port n Control CSR bit definitions.
* These bits are associated with the XSRIO_PORT_N_CTL_CSR_OFFSET register.
* @{
*/
#define XSRIO_PORT_N_CTL_PTYPE_CSR_MASK 0x00000001 /**< Port Type Mask */
#define XSRIO_PORT_N_CTL_EPWDS_CSR_MASK 0x00003000 /**< Extended Port
* Width Support Mask
*/
#define XSRIO_PORT_N_CTL_EPWOR_CSR_MASK 0x0000C000 /**< Extended Port
* Width Override Mask
*/
#define XSRIO_PORT_N_CTL_ENUMB_CSR_MASK 0x00020000 /**< Enumeration
* Boundary Mask
*/
#define XSRIO_PORT_N_CTL_MCENT_CSR_MASK 0x00080000 /**< Multi-cast Event
* Participant Mask
*/
#define XSRIO_PORT_N_CTL_ERRD_CSR_MASK 0x00100000 /**< Error Checking
* Disable Mask
*/
#define XSRIO_PORT_N_CTL_IPE_CSR_MASK 0x00200000 /**< Input port
* enable Mask
*/
#define XSRIO_PORT_N_CTL_OPE_CSR_MASK 0x00400000 /**< Output port
* enable Mask
*/
#define XSRIO_PORT_N_CTL_PD_CSR_MASK 0x00800000 /**< Output port
* disable Mask
*/
#define XSRIO_PORT_N_CTL_PWO_CSR_MASK 0x07000000 /**< Port width
* Override Mask
*/
#define XSRIO_PORT_N_CTL_RESET_PWO_CSR_MASK 0xF8FFFFFF /**< Port wdith
* Override Reset Mask
*/
#define XSRIO_PORT_N_CTL_IPW_CSR_MASK 0x38000000 /**< Initialized
* Port width Mask
*/
#define XSRIO_PORT_N_CTL_PW_CSR_MASK 0xc0000000 /**< Port width Mask */
#define XSRIO_PORT_N_CTRL_CSR_STATUS_ALL_MASK 0x00F00000 /**< Port Status All
* Mask
*/
#define XSRIO_PORT_N_CTL_PWO_CSR_SHIFT 24 /**< Port width
* Override Shift
*/
#define XSRIO_PORT_N_CTL_PW_CSR_SHIFT 30 /**< Port width
* Shift
*/
/*@}*/
/** @name LP -Serial Lane Register Block Header bit definitions.
* These bits are associated with the XSRIO_SL_HEADER_OFFSET register.
* @{
*/
#define XSRIO_SL_HEADER_EFID_MASK 0x0000FFFF /**< Extended
* Features ID Mask
*/
#define XSRIO_SL_HEADER_EFP_MASK 0xFFFF0000 /**< Extended Features
* Pointer Mask
*/
#define XSRIO_SL_HEADER_EFP_SHIFT 16 /**< Extended Features
* Pointer Shift
*/
/*@}*/
/** @name LP -Seral Lane n Status 0 CSRS bit definitions.
* These bits are associated with the XSRIO_SLS0_CSR(x) register.
* @{
*/
#define XSRIO_SLS0_CSR_PORT_NUM_MASK 0xFF000000 /**< Port Number Mask */
#define XSRIO_SLS0_CSR_LANE_NUM_MASK 0x00F00000 /**< Lane Number Mask */
#define XSRIO_SLS0_CSR_TRANSMIT_TYPE_MASK 0x00080000 /**< Transmitter
* Type Mask
*/
#define XSRIO_SLS0_CSR_TRANSMIT_MODE_MASK 0x00040000 /**< Transmitter
* Mode Mask
*/
#define XSRIO_SLS0_CSR_RCV_INPUT_INV_MASK 0x00008000 /**< Receiver Input
* Inverted Mask
*/
#define XSRIO_SLS0_CSR_RCV_TRAINED_MASK 0x00004000 /**< Receiver
* Trained Mask
*/
#define XSRIO_SLS0_CSR_RCVLANE_SYNC_MASK 0x00002000 /**< Receive Lane
* Sync Mask
*/
#define XSRIO_SLS0_CSR_RCVLANE_RDY_MASK 0x00001000 /**< Receive Lane
* Ready Mask
*/
#define XSRIO_SLS0_CSR_DECODING_ERRORS_MASK 0x00000F00 /**< 8B/10B Decoding
* errors Mask
*/
#define XSRIO_SLS0_CSR_LANESYNC_CHAN_MASK 0x00000080 /**< lane_sync state
* change Mask
*/
#define XSRIO_SLS0_CSR_RCVTRAINED_CHAN_MASK 0x00000040 /**< rcvr_train state
* changed Mask
*/
#define XSRIO_SLS0_CSR_STAT1_IMP_MASK 0x00000008 /**< Status 1 CSR
* Implemented Mask
*/
#define XSRIO_SLS0_CSR_DECODING_ERRORS_SHIFT 8
/*@}*/
/** @name LP -Seral Lane n Status 1 CSRS bit definitions.
* These bits are associated with the XSRIO_SLS1_CSR(x) register.
* @{
*/
#define XSRIO_SLS1_CSR_SCRDSCR_EN_MASK 0x00008000 /**< Connected port
* Scrambling/Descrambling
* Enabled Mask
*/
#define XSRIO_SLS1_CSR_CPTEIS_MASK 0x00030000 /**< Connected port transmit
* Emphasis Tap(+1) Status
* Mask
*/
#define XSRIO_SLS1_CSR_CPTEDS_MASK 0x000C0000 /**< Connected port transmit
* Emphasis Tap(-1) Status
* Mask
*/
#define XSRIO_SLS1_CSR_LANENUM_MASK 0x00F00000 /**< Lane number within
* connected port
*/
#define XSRIO_SLS1_CSR_RXPORT_WIDTH_MASK 0x07000000 /**< Receive port width
* Mask
*/
#define XSRIO_SLS1_CSR_CPLR_TRAINED_MASK 0x08000000 /**< Connected port lane
* Receiver trained Mask
*/
#define XSRIO_SLS1_CSR_IMPDEFINED_MASK 0x10000000 /**< Implementation defined
* Mask
*/
#define XSRIO_SLS1_CSR_VALCHANGED_MASK 0x20000000 /**< Values Changed Mask */
#define XSRIO_SLS1_CSR_IDLE2_INFO_MASK 0x40000000 /**< IDLE2 Information
* Current Mask
*/
#define XSRIO_SLS1_CSR_IDLE2_REC_MASK 0x80000000 /**< IDLE2 Received Mask */
/*@}*/
/** @name Water Mark CSRS bit definitions.
* These bits are associated with the XSRIO_IMP_WCSR_OFFSET register.
* @{
*/
#define XSRIO_IMP_WCSR_WM2_MASK 0x003F0000 /**< Water Mark 2 Mask */
#define XSRIO_IMP_WCSR_WM1_MASK 0x00003F00 /**< Water Mark 1 Mask */
#define XSRIO_IMP_WCSR_WM0_MASK 0x0000003F /**< Water Mark 0 Mask */
#define XSRIO_IMP_WCSR_RESET_WM0_MASK 0xFFFFFFC0 /**< Water Mark 0 ResetMask */
#define XSRIO_IMP_WCSR_RESET_WM1_MASK 0xFFFFC0FF /**< Water Mark 1 ResetMask */
#define XSRIO_IMP_WCSR_RESET_WM2_MASK 0xFFC0FFFF /**< Water Mark 2 ResetMask */
#define XSRIO_IMP_WCSR_WM1_SHIFT 8 /**< Water Mark 1 Shift */
#define XSRIO_IMP_WCSR_WM2_SHIFT 16 /**< Water Mark 2 Shift */
/*@}*/
/** @name Buffer Control CSRS bit definitions.
* These bits are associated with the XSRIO_IMP_BCSR_OFFSET register.
* @{
*/
#define XSRIO_IMP_BCSR_RXFLOW_CNTLONLY_MASK 0x80000000 /**< Rx Flow Control
* Only Mask
*/
#define XSRIO_IMP_BCSR_UNIFIED_CLK_MASK 0x40000000 /**< Buffer Control
* Mask
*/
#define XSRIO_IMP_BCSR_TX_FLOW_CNTL_MASK 0x20000000 /**< Tx Flow
* Control Mask
*/
#define XSRIO_IMP_BCSR_TXREQ_REORDER_MASK 0x10000000 /**< Tx Request
* Reorder Mask */
#define XSRIO_IMP_BCSR_TXSIZE_MASK 0x07FF0000 /**< Tx size Mask */
#define XSRIO_IMP_BCSR_FRX_FLOW_CNTL_MASK 0x00008000 /**< Force Rx flow
* Control Mask
*/
#define XSRIO_IMP_BCSR_RXSIZE_MASK 0x000000FF /**< Rx size Mask */
#define XSRIO_IMP_BCSR_TXSIZE_SHIFT 16 /**< Tx size shift */
/*@}*/
/** @name Maintenance Request Information Register bit definitions.
* These bits are associated with the XSRIO_IMP_MRIR_OFFSET register.
* @{
*/
#define XSRIO_IMP_MRIR_REQ_TID_MASK 0xFF000000 /**< Request TID Mask */
#define XSRIO_IMP_MRIR_REQ_PRIO_MASK 0x00060000 /**< Request Priority Mask */
#define XSRIO_IMP_MRIR_REQ_CRF_MASK 0x00010000 /**< Request CRF Mask */
#define XSRIO_IMP_MRIR_REQ_DESTID_MASK 0x0000FFFF /**< Request Destination
* ID Mask
*/
#define XSRIO_IMP_MRIR_RST_REQ_DESTID_MASK 0xFFFF0000
#define XSRIO_IMP_MRIR_RST_REQ_PRIO_MASK 0xFFF9FFFF
#define XSRIO_IMP_MRIR_REQ_RST_TID_MASK 0x00FFFFFF
#define XSRIO_IMP_MRIR_REQ_PRIO_SHIFT 17
#define XSRIO_IMP_MRIR_REQ_CRF_SHIFT 16
#define XSRIO_IMP_MRIR_REQ_TID_SHIFT 24
/*@}*/
/****************** Macros (Inline Functions) Definitions ********************/
/*****************************************************************************/
/**
* Macro to read register.
*
* @param BaseAddress is the base address of the SRIO
* @param RegOffset is the register offset.
*
* @return Value of the register.
*
* @note C-style signature:
* u32 XSrio_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XSrio_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/*****************************************************************************/
/**
* Macro to write register.
*
* @param BaseAddress is the base address of the SRIO.
* @param RegOffset is the register offset.
* @param Data is the data to write.
*
* @return None
*
* @note C-style signature:
* void XSRIO_WriteReg(u32 BaseAddress, u32 RegOffset,
* u32 Data)
*
******************************************************************************/
#define XSrio_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (Data))
/*************************** Variable Definitions ****************************/
/*************************** Function Prototypes *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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XilinxProcessorIPLib/drivers/srio/src/xsrio_sinit.c Executable file
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@ -0,0 +1,97 @@
/******************************************************************************
*
* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsrio_sinit.c
*
* This file contains static Initialization functionality for Xilinx SRIO Gen2
* Core driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 adk 16/04/14 Initial release.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xsrio.h"
/*****************************************************************************/
/**
* Looks up the device configuration based on the unique device ID. The table
* XSrio_ConfigTable contains the configuration info for each device in the
* system.
*
* @param DeviceId is the unique device ID of the device to lookup for
*
* @return
* The configuration structure for the device. If the device ID is
* not found,a NULL pointer is returned.
*
* @note None
*
******************************************************************************/
XSrio_Config *XSrio_LookupConfig(u32 DeviceId)
{
extern XSrio_Config XSrio_ConfigTable[];
XSrio_Config *CfgPtr;
u32 Index;
CfgPtr = NULL;
for (Index = 0; Index < XPAR_XSRIO_NUM_INSTANCES; Index++) {
if (XSrio_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XSrio_ConfigTable[Index];
break;
}
}
return CfgPtr;
}