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uartps_v3_1 : Modified code to support latest RTL changes.

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This patch adds support code for Zynq Ultrascale+ MP

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This commit is contained in:
Venkata Naga Sai Krishna Kolapalli 2015-04-10 17:17:27 +05:30 • committed by Nava kishore Manne
parent f43b10aa77
commit 520e483d61
4 changed files with 76 additions and 10 deletions
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4
XilinxProcessorIPLib/drivers/uartps/src/xuartps.c
View file

@ -46,6 +46,7 @@
* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
* baud rate. CR# 804281.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
* </pre>
*
*****************************************************************************/
@ -157,6 +158,9 @@ s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
/* Initialize the platform data */
InstancePtr->Platform = XGetPlatform_Info();
/*
* Flag that the driver instance is ready to use
*/

17
XilinxProcessorIPLib/drivers/uartps/src/xuartps.h
View file

@ -154,6 +154,8 @@
* baud rate. CR# 804281.
* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
* Support for Zynq Ultrascale Mp added.
* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
* platform variable in driver instance structure.
*
* </pre>
*
@ -172,6 +174,7 @@ extern "C" {
#include "xil_assert.h"
#include "xstatus.h"
#include "xuartps_hw.h"
#include "xplatform_info.h"
/************************** Constant Definitions ****************************/
@ -253,11 +256,14 @@ extern "C" {
*
* @{
*/
#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
* error detected */
#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
/*@}*/
@ -328,6 +334,7 @@ typedef struct {
XUartPs_Handler Handler;
void *CallBackRef; /* Callback reference for event handler */
u32 Platform;
} XUartPs;

27
XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h
View file

@ -52,6 +52,7 @@
* 1.05a hk 08/22/13 Added prototype for uart reset and related
* constant definitions.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
*
* </pre>
*
@ -92,6 +93,7 @@ extern "C" {
#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
/* @} */
/** @name Control Register
@ -165,6 +167,7 @@ extern "C" {
*
* @{
*/
#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
@ -320,6 +323,30 @@ extern "C" {
#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
/* @} */
/** @name Receiver FIFO Byte Status Register
*
* The Receiver FIFO Status register is used to have a continuous
* monitoring of the raw unmasked byte status information. The register
* contains frame, parity and break status information for the top
* four bytes in the RX FIFO.
*
* Receiver FIFO Byte Status Register Bit Definition
* @{
*/
#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
#define XUARTPS_RXBS_MASK 0x00000FFFU /**< 24 bit RX byte status mask */
/* @} */
/*

38
XilinxProcessorIPLib/drivers/uartps/src/xuartps_intr.c
View file

@ -43,6 +43,7 @@
* ----- ------ -------- -----------------------------------------------
* 1.00 drg/jz 01/13/10 First Release
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
* </pre>
*
*****************************************************************************/
@ -220,8 +221,9 @@ void XUartPs_InterruptHandler(XUartPs *InstancePtr)
SendDataHandler(InstancePtr, IsrStatus);
}
if((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
(u32)XUARTPS_IXR_PARITY)) != (u32)0) {
/* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
(u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
/* Received Error Status interrupt */
ReceiveErrorHandler(InstancePtr);
}
@ -259,6 +261,14 @@ void XUartPs_InterruptHandler(XUartPs *InstancePtr)
*****************************************************************************/
static void ReceiveErrorHandler(XUartPs *InstancePtr)
{
u32 ByteStatusValue, EventData;
u32 Event;
if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
ByteStatusValue = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_RXBS_OFFSET);
}
/*
* If there are bytes still to be received in the specified buffer
* go ahead and receive them. Removing bytes from the RX FIFO will
@ -268,15 +278,33 @@ static void ReceiveErrorHandler(XUartPs *InstancePtr)
(void)XUartPs_ReceiveBuffer(InstancePtr);
}
/* Platform Zynq Ultrascale+ MP */
if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
EventData = ByteStatusValue;
Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
}
else {
EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
InstancePtr->ReceiveBuffer.RemainingBytes;
Event = XUARTPS_EVENT_RECV_ORERR;
}
}
/* Platform Zynq */
else {
Event = XUARTPS_EVENT_RECV_ERROR;
EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
InstancePtr->ReceiveBuffer.RemainingBytes;
}
/*
* Call the application handler to indicate that there is a receive
* error or a break interrupt, if the application cares about the
* error it call a function to get the last errors.
*/
InstancePtr->Handler(InstancePtr->CallBackRef,
XUARTPS_EVENT_RECV_ERROR,
(InstancePtr->ReceiveBuffer.RequestedBytes -
InstancePtr->ReceiveBuffer.RemainingBytes));
Event,
EventData);
}
/****************************************************************************/