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emacps: Add support for Zynq Ultrascale Mp and misra c guidelines

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Add support for Zynq Ultrascale Mp and misra c compliant

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This commit is contained in:
Punnaiah Choudary Kalluri 2014-12-09 20:22:21 +05:30 • committed by Suneel Garapati
parent 35e0aac333
commit 54cf0f4cfa
15 changed files with 1506 additions and 1004 deletions
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2
XilinxProcessorIPLib/drivers/emacps/data/emacps.mdd
View file

@ -33,7 +33,7 @@ OPTION psf_version = 2.1;
BEGIN driver emacps
OPTION supported_peripherals = (ps7_ethernet);
OPTION supported_peripherals = (ps7_ethernet ps8_ethernet pss_ethernet);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 3.0;

8
XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example.h
View file

@ -93,7 +93,7 @@
* specific to the GNU compiler
*/
typedef char EthernetFrame[XEMACPS_MAX_VLAN_FRAME_SIZE]
__attribute__ ((aligned(32)));
__attribute__ ((aligned(64)));
/************************** Function Prototypes *****************************/
@ -105,11 +105,11 @@ typedef char EthernetFrame[XEMACPS_MAX_VLAN_FRAME_SIZE]
void EmacPsUtilSetupUart(void);
void EmacPsUtilFrameHdrFormatMAC(EthernetFrame * FramePtr, char *DestAddr);
void EmacPsUtilFrameHdrFormatType(EthernetFrame * FramePtr, u16 FrameType);
void EmacPsUtilFrameSetPayloadData(EthernetFrame * FramePtr, int PayloadSize);
int EmacPsUtilFrameVerify(EthernetFrame * CheckFrame,
void EmacPsUtilFrameSetPayloadData(EthernetFrame * FramePtr, u32 PayloadSize);
LONG EmacPsUtilFrameVerify(EthernetFrame * CheckFrame,
EthernetFrame * ActualFrame);
void EmacPsUtilFrameMemClear(EthernetFrame * FramePtr);
int EmacPsUtilEnterLoopback(XEmacPs * XEmacPsInstancePtr, int Speed);
LONG EmacPsUtilEnterLoopback(XEmacPs * XEmacPsInstancePtr, u32 Speed);
void EmacPsUtilstrncpy(char *Destination, const char *Source, u32 n);
void EmacPsUtilErrorTrap(const char *Message);

251
XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_intr_dma.c
View file

@ -103,6 +103,8 @@
* XEmacPsRecvHandler so that invalidation happens after the
* received data is available in the memory. The variable
* TxFrameLength is now made global.
* 2.1 srt 07/11/14 Implemented 64-bit changes and modified as per
* Zynq Ultrascale Mp GEM specification
*
* </pre>
*
@ -145,12 +147,27 @@
#define SLCR_UNLOCK_KEY_VALUE 0xDF0D
#define SLCR_ADDR_GEM_RST_CTRL (XPS_SYS_CTRL_BASEADDR + 0x214)
/* FIXME: These are constants to enable GEM0 */
#define GPIO_DATA2_REG 0xFF008048
#define GPIO_DATA2_DIR 0xFF008284
#define GPIO_GEM_MASK (3<<18)
#define GPIO_GEM_VAL_1G (1<<18)
/*************************** Variable Definitions ***************************/
EthernetFrame TxFrame; /* Transmit buffer */
EthernetFrame RxFrame; /* Receive buffer */
/*
* Buffer descriptors are allocated in uncached memory. The memory is made
* uncached by setting the attributes appropriately in the MMU table.
*/
/* FIXME: This example is tested without caches */
#define RXBD_SPACE_BYTES XEmacPs_BdRingMemCalc(XEMACPS_BD_ALIGNMENT, RXBD_CNT)
#define TXBD_SPACE_BYTES XEmacPs_BdRingMemCalc(XEMACPS_BD_ALIGNMENT, TXBD_CNT)
/*
* Buffer descriptors are allocated in uncached memory. The memory is made
* uncached by setting the attributes appropriately in the MMU table.
@ -163,9 +180,9 @@ EthernetFrame RxFrame; /* Receive buffer */
/*
* Counters to be incremented by callbacks
*/
volatile int FramesRx; /* Frames have been received */
volatile int FramesTx; /* Frames have been sent */
volatile int DeviceErrors; /* Number of errors detected in the device */
volatile s32 FramesRx; /* Frames have been received */
volatile s32 FramesTx; /* Frames have been sent */
volatile s32 DeviceErrors; /* Number of errors detected in the device */
u32 TxFrameLength;
@ -173,22 +190,24 @@ u32 TxFrameLength;
static XScuGic IntcInstance;
#endif
u32 GemVersion;
/*************************** Function Prototypes ****************************/
/*
* Example
*/
int EmacPsDmaIntrExample(XScuGic *IntcInstancePtr,
LONG EmacPsDmaIntrExample(XScuGic *IntcInstancePtr,
XEmacPs *EmacPsInstancePtr,
u16 EmacPsDeviceId, u16 EmacPsIntrId);
int EmacPsDmaSingleFrameIntrExample(XEmacPs * EmacPsInstancePtr);
LONG EmacPsDmaSingleFrameIntrExample(XEmacPs * EmacPsInstancePtr);
/*
* Interrupt setup and Callbacks for examples
*/
static int EmacPsSetupIntrSystem(XScuGic * IntcInstancePtr,
static LONG EmacPsSetupIntrSystem(XScuGic * IntcInstancePtr,
XEmacPs * EmacPsInstancePtr,
u16 EmacPsIntrId);
@ -202,7 +221,7 @@ static void XEmacPsErrorHandler(void *Callback, u8 direction, u32 word);
/*
* Utility routines
*/
static int EmacPsResetDevice(XEmacPs * EmacPsInstancePtr);
static LONG EmacPsResetDevice(XEmacPs * EmacPsInstancePtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor);
/****************************************************************************/
@ -221,7 +240,7 @@ void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor);
#ifndef TESTAPP_GEN
int main(void)
{
int Status;
LONG Status;
xil_printf("Entering into main() \r\n");
@ -264,12 +283,12 @@ int main(void)
* @note None.
*
*****************************************************************************/
int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
LONG EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
XEmacPs * EmacPsInstancePtr,
u16 EmacPsDeviceId,
u16 EmacPsIntrId)
{
int Status;
LONG Status;
XEmacPs_Config *Config;
XEmacPs_Bd BdTemplate;
#ifndef PEEP
@ -280,6 +299,32 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
/* Setup device for first-time usage */
/*************************************/
/*
* Initialize instance. Should be configured for DMA
* This example calls _CfgInitialize instead of _Initialize due to
* retiring _Initialize. So in _CfgInitialize we use
* XPAR_(IP)_BASEADDRESS to make sure it is not virtual address.
*/
Config = XEmacPs_LookupConfig(EmacPsDeviceId);
Status = XEmacPs_CfgInitialize(EmacPsInstancePtr, Config,
Config->BaseAddress);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error in initialize");
return XST_FAILURE;
}
GemVersion = ((Xil_In32(Config->BaseAddress + 0xFC)) >> 16) & 0xFFF;
if (GemVersion == 2)
{
/*************************************/
/* Setup device for first-time usage */
/*************************************/
/* SLCR unlock */
*(volatile unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
#ifdef PEEP
@ -315,23 +360,9 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
sleep(1);
/*
* Initialize instance. Should be configured for DMA
* This example calls _CfgInitialize instead of _Initialize due to
* retiring _Initialize. So in _CfgInitialize we use
* XPAR_(IP)_BASEADDRESS to make sure it is not virtual address.
*/
Config = XEmacPs_LookupConfig(EmacPsDeviceId);
Status = XEmacPs_CfgInitialize(EmacPsInstancePtr, Config,
Config->BaseAddress);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error in initialize");
return XST_FAILURE;
}
/*
* Set the MAC address
*/
@ -340,7 +371,6 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
EmacPsUtilErrorTrap("Error setting MAC address");
return XST_FAILURE;
}
/*
* Setup callbacks
*/
@ -362,11 +392,6 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
return XST_FAILURE;
}
/*
* The BDs need to be allocated in uncached memory. Hence the 1 MB
* address range that starts at address 0xFF00000 is made uncached.
*/
Xil_SetTlbAttributes(0x0FF00000, 0xc02);
/*
* Setup RxBD space.
*
@ -386,8 +411,8 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
*/
Status = XEmacPs_BdRingCreate(&(XEmacPs_GetRxRing
(EmacPsInstancePtr)),
RX_BD_LIST_START_ADDRESS,
RX_BD_LIST_START_ADDRESS,
(UINTPTR) RX_BD_LIST_START_ADDRESS,
(UINTPTR)RX_BD_LIST_START_ADDRESS,
XEMACPS_BD_ALIGNMENT,
RXBD_CNT);
if (Status != XST_SUCCESS) {
@ -404,6 +429,16 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
return XST_FAILURE;
}
if (GemVersion == 2)
{
/*
* The BDs need to be allocated in uncached memory. Hence the 1 MB
* address range that starts at address 0xFF00000 is made uncached.
*/
Xil_SetTlbAttributes(0x0FF00000, 0xc02);
}
/*
* Setup TxBD space.
*
@ -422,8 +457,8 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
*/
Status = XEmacPs_BdRingCreate(&(XEmacPs_GetTxRing
(EmacPsInstancePtr)),
TX_BD_LIST_START_ADDRESS,
TX_BD_LIST_START_ADDRESS,
(UINTPTR) TX_BD_LIST_START_ADDRESS,
(UINTPTR) TX_BD_LIST_START_ADDRESS,
XEMACPS_BD_ALIGNMENT,
TXBD_CNT);
if (Status != XST_SUCCESS) {
@ -442,10 +477,16 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
/*
* Set emacps to phy loopback
*/
if (GemVersion == 2)
{
#ifndef PEEP /* For Zynq board */
XEmacPs_SetMdioDivisor(EmacPsInstancePtr, MDC_DIV_224);
sleep(1);
#endif
}
/*
* Set emacps to phy loopback
*/
EmacPsUtilEnterLoopback(EmacPsInstancePtr, EMACPS_LOOPBACK_SPEED_1G);
XEmacPs_SetOperatingSpeed(EmacPsInstancePtr, EMACPS_LOOPBACK_SPEED_1G);
@ -454,6 +495,7 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
*/
Status = EmacPsSetupIntrSystem(IntcInstancePtr,
EmacPsInstancePtr, EmacPsIntrId);
/*
* Run the EmacPs DMA Single Frame Interrupt example
*/
@ -492,9 +534,9 @@ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
* @note None.
*
*****************************************************************************/
int EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr)
LONG EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr)
{
int Status;
LONG Status;
u32 PayloadSize = 1000;
u32 NumRxBuf = 0;
XEmacPs_Bd *Bd1Ptr;
@ -520,43 +562,74 @@ int EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr)
EmacPsUtilFrameHdrFormatType(&TxFrame, PayloadSize);
EmacPsUtilFrameSetPayloadData(&TxFrame, PayloadSize);
Xil_DCacheFlushRange((u32)&TxFrame, TxFrameLength);
Xil_DCacheFlushRange((UINTPTR)&TxFrame, sizeof(EthernetFrame));
/*
* Clear out receive packet memory area
*/
EmacPsUtilFrameMemClear(&RxFrame);
Xil_DCacheFlushRange((u32)&RxFrame, TxFrameLength);
Xil_DCacheFlushRange((UINTPTR)&RxFrame, sizeof(EthernetFrame));
/*
* Allocate RxBDs since we do not know how many BDs will be used
* in advance, use RXBD_CNT here.
*/
if (GemVersion == 2)
{
Status = XEmacPs_BdRingAlloc(&
(XEmacPs_GetRxRing(EmacPsInstancePtr)),
2, &BdRxPtr);
}
if (GemVersion == 7)
{
Status = XEmacPs_BdRingAlloc(&
(XEmacPs_GetRxRing(EmacPsInstancePtr)),
1, &BdRxPtr);
}
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error allocating RxBD");
return XST_FAILURE;
}
/*
* Setup the BD. The XEmacPs_BdRingClone() call will mark the
* "wrap" field for last RxBD. Setup buffer address to associated
* BD.
*/
XEmacPs_BdSetAddressRx(BdRxPtr, &RxFrame);
XEmacPs_BdSetAddressRx(BdRxPtr, (UINTPTR)&RxFrame);
/*
* Enqueue to HW
*/
if (GemVersion == 2)
{
Status = XEmacPs_BdRingToHw(&(XEmacPs_GetRxRing(EmacPsInstancePtr)),
1, BdRxPtr);
2, BdRxPtr);
}
if (GemVersion == 7)
{
Status = XEmacPs_BdRingToHw(&(XEmacPs_GetRxRing(EmacPsInstancePtr)),
1, BdRxPtr);
}
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error committing RxBD to HW");
return XST_FAILURE;
}
/*
* Though the max BD size is 16 bytes for extended desc mode, performing
* cache flush for 64 bytes. which is equal to the cache line size.
*/
if (GemVersion == 7)
{
Xil_DCacheFlushRange((UINTPTR)BdRxPtr, 64);
}
/*
* Allocate, setup, and enqueue 2 TxBDs. The first BD will
* describe the first 32 bytes of TxFrame and the rest of BDs
@ -565,8 +638,18 @@ int EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr)
* The function below will allocate 2 adjacent BDs with Bd1Ptr
* being set as the lead BD.
*/
if (GemVersion == 2)
{
Status = XEmacPs_BdRingAlloc(&(XEmacPs_GetTxRing(EmacPsInstancePtr)),
2, &Bd1Ptr);
}
if (GemVersion == 7)
{
Status = XEmacPs_BdRingAlloc(&(XEmacPs_GetTxRing(EmacPsInstancePtr)),
1, &Bd1Ptr);
}
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error allocating TxBD");
return XST_FAILURE;
@ -575,10 +658,10 @@ int EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr)
/*
* Setup first TxBD
*/
XEmacPs_BdSetAddressTx(Bd1Ptr, &TxFrame);
XEmacPs_BdSetLength(Bd1Ptr, FIRST_FRAGMENT_SIZE);
XEmacPs_BdSetAddressTx(Bd1Ptr, (UINTPTR)&TxFrame);
XEmacPs_BdSetLength(Bd1Ptr, TxFrameLength);
XEmacPs_BdClearTxUsed(Bd1Ptr);
XEmacPs_BdClearLast(Bd1Ptr);
XEmacPs_BdSetLast(Bd1Ptr);
/*
* Setup second TxBD
@ -586,20 +669,43 @@ int EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr)
Bd2Ptr = XEmacPs_BdRingNext(&(XEmacPs_GetTxRing(EmacPsInstancePtr)),
Bd1Ptr);
XEmacPs_BdSetAddressTx(Bd2Ptr,
(u32) (&TxFrame) + FIRST_FRAGMENT_SIZE);
(UINTPTR) (&TxFrame) + FIRST_FRAGMENT_SIZE);
XEmacPs_BdSetLength(Bd2Ptr, TxFrameLength - FIRST_FRAGMENT_SIZE);
XEmacPs_BdClearTxUsed(Bd2Ptr);
XEmacPs_BdSetLast(Bd2Ptr);
/*
* Enqueue to HW
*/
if (GemVersion == 2)
{
Status = XEmacPs_BdRingToHw(&(XEmacPs_GetTxRing(EmacPsInstancePtr)),
2, Bd1Ptr);
}
if (GemVersion == 7)
{
Status = XEmacPs_BdRingToHw(&(XEmacPs_GetTxRing(EmacPsInstancePtr)),
1, Bd1Ptr);
}
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error committing TxBD to HW");
return XST_FAILURE;
}
Xil_DCacheFlushRange((UINTPTR)Bd1Ptr, 64);
/*
* Set the Queue pointers
*/
XEmacPs_SetQueuePtr(EmacPsInstancePtr, EmacPsInstancePtr->RxBdRing.BaseBdAddr, 0, XEMACPS_RECV);
if (GemVersion == 7) {
XEmacPs_SetQueuePtr(EmacPsInstancePtr, EmacPsInstancePtr->TxBdRing.BaseBdAddr, 1, XEMACPS_SEND);
}else {
XEmacPs_SetQueuePtr(EmacPsInstancePtr, EmacPsInstancePtr->TxBdRing.BaseBdAddr, 0, XEMACPS_SEND);
}
/*
* Start the device
@ -619,12 +725,26 @@ int EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr)
* Since we have only submitted 2 to hardware, then there should
* be only 2 ready for post processing.
*/
if (GemVersion == 2)
{
if (XEmacPs_BdRingFromHwTx(&(XEmacPs_GetTxRing(EmacPsInstancePtr)),
2, &Bd1Ptr) == 0) {
EmacPsUtilErrorTrap
("TxBDs were not ready for post processing");
return XST_FAILURE;
}
}
if (GemVersion == 7)
{
if (XEmacPs_BdRingFromHwTx(&(XEmacPs_GetTxRing(EmacPsInstancePtr)),
1, &Bd1Ptr) == 0) {
EmacPsUtilErrorTrap
("TxBDs were not ready for post processing");
return XST_FAILURE;
}
}
/*
* Examine the TxBDs.
@ -633,8 +753,11 @@ int EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr)
* exception bits. But this would also be caught in the error
* handler. So we just return these BDs to the free list.
*/
Status = XEmacPs_BdRingFree(&(XEmacPs_GetTxRing(EmacPsInstancePtr)),
2, Bd1Ptr);
1, Bd1Ptr);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error freeing up TxBDs");
return XST_FAILURE;
@ -714,13 +837,14 @@ int EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr)
* @note None.
*
*****************************************************************************/
static int EmacPsResetDevice(XEmacPs * EmacPsInstancePtr)
static LONG EmacPsResetDevice(XEmacPs * EmacPsInstancePtr)
{
int Status = 0;
LONG Status = 0;
u8 MacSave[6];
u32 Options;
XEmacPs_Bd BdTemplate;
/*
* Stop device
*/
@ -785,8 +909,8 @@ static int EmacPsResetDevice(XEmacPs * EmacPsInstancePtr)
*/
Status = XEmacPs_BdRingCreate(&(XEmacPs_GetRxRing
(EmacPsInstancePtr)),
RX_BD_LIST_START_ADDRESS,
RX_BD_LIST_START_ADDRESS,
(UINTPTR) RX_BD_LIST_START_ADDRESS,
(UINTPTR) RX_BD_LIST_START_ADDRESS,
XEMACPS_BD_ALIGNMENT,
RXBD_CNT);
if (Status != XST_SUCCESS) {
@ -822,8 +946,8 @@ static int EmacPsResetDevice(XEmacPs * EmacPsInstancePtr)
*/
Status = XEmacPs_BdRingCreate(&(XEmacPs_GetTxRing
(EmacPsInstancePtr)),
TX_BD_LIST_START_ADDRESS,
TX_BD_LIST_START_ADDRESS,
(UINTPTR) TX_BD_LIST_START_ADDRESS,
(UINTPTR) TX_BD_LIST_START_ADDRESS,
XEMACPS_BD_ALIGNMENT,
TXBD_CNT);
if (Status != XST_SUCCESS) {
@ -865,11 +989,11 @@ static int EmacPsResetDevice(XEmacPs * EmacPsInstancePtr)
* @note None.
*
*****************************************************************************/
static int EmacPsSetupIntrSystem(XScuGic *IntcInstancePtr,
static LONG EmacPsSetupIntrSystem(XScuGic *IntcInstancePtr,
XEmacPs *EmacPsInstancePtr,
u16 EmacPsIntrId)
{
int Status;
LONG Status;
#ifndef TESTAPP_GEN
XScuGic_Config *GicConfig;
@ -976,6 +1100,9 @@ static void XEmacPsSendHandler(void *Callback)
*/
XEmacPs_IntDisable(EmacPsInstancePtr, (XEMACPS_IXR_TXCOMPL_MASK |
XEMACPS_IXR_TX_ERR_MASK));
if (GemVersion == 7) {
XEmacPs_IntQ1Disable(EmacPsInstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
}
/*
* Increment the counter so that main thread knows something
* happened.
@ -1011,7 +1138,10 @@ static void XEmacPsRecvHandler(void *Callback)
* happened.
*/
FramesRx++;
Xil_DCacheInvalidateRange((u32)&RxFrame, TxFrameLength);
Xil_DCacheInvalidateRange((UINTPTR)&RxFrame, sizeof(EthernetFrame));
if (GemVersion == 7) {
Xil_DCacheInvalidateRange((UINTPTR)RX_BD_LIST_START_ADDRESS, 64);
}
}
@ -1058,6 +1188,8 @@ static void XEmacPsErrorHandler(void *Callback, u8 Direction, u32 ErrorWord)
if (ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK) {
EmacPsUtilErrorTrap("Transmit DMA error");
}
/* FIXME: Interrupt Q1 Status register has Tx AHB error and
this has to be handled */
if (ErrorWord & XEMACPS_TXSR_URUN_MASK) {
EmacPsUtilErrorTrap("Transmit under run");
}
@ -1075,5 +1207,12 @@ static void XEmacPsErrorHandler(void *Callback, u8 Direction, u32 ErrorWord)
}
break;
}
/*
* Bypassing the reset functionality as the default tx status for q0 is
* USED BIT READ. so, the first interrupt will be tx used bit and it resets
* the core always.
*/
if (GemVersion == 2) {
EmacPsResetDevice(EmacPsInstancePtr);
}
}

31
XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_util.c
View file

@ -85,7 +85,7 @@ void EmacPsUtilFrameHdrFormatMAC(EthernetFrame * FramePtr, char *DestAddr)
{
char *Frame = (char *) FramePtr;
char *SourceAddress = EmacPsMAC;
int Index;
s32 Index;
/* Destination address */
for (Index = 0; Index < XEMACPS_MAC_ADDR_SIZE; Index++) {
@ -147,9 +147,9 @@ void EmacPsUtilFrameHdrFormatType(EthernetFrame * FramePtr, u16 FrameType)
* @note None.
*
*****************************************************************************/
void EmacPsUtilFrameSetPayloadData(EthernetFrame * FramePtr, int PayloadSize)
void EmacPsUtilFrameSetPayloadData(EthernetFrame * FramePtr, u32 PayloadSize)
{
unsigned BytesLeft = PayloadSize;
u32 BytesLeft = PayloadSize;
u8 *Frame;
u16 Counter = 0;
@ -197,14 +197,14 @@ void EmacPsUtilFrameSetPayloadData(EthernetFrame * FramePtr, int PayloadSize)
*
* @note None.
*****************************************************************************/
int EmacPsUtilFrameVerify(EthernetFrame * CheckFrame,
LONG EmacPsUtilFrameVerify(EthernetFrame * CheckFrame,
EthernetFrame * ActualFrame)
{
char *CheckPtr = (char *) CheckFrame;
char *ActualPtr = (char *) ActualFrame;
u16 BytesLeft;
u16 Counter;
int Index;
u32 Index;
/*
* Compare the headers
@ -348,7 +348,7 @@ void EmacPsUtilEnterLocalLoopback(XEmacPs * EmacPsInstancePtr)
u32 XEmacPsDetectPHY(XEmacPs * EmacPsInstancePtr)
{
u32 PhyAddr;
int Status;
u32 Status;
u16 PhyReg1;
u16 PhyReg2;
@ -394,9 +394,9 @@ u32 XEmacPsDetectPHY(XEmacPs * EmacPsInstancePtr)
#define PHY_R20_DFT_SPD_10 0x0040
#define PHY_R20_DFT_SPD_100 0x0050
#define PHY_R20_DFT_SPD_1000 0x0060
int EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, int Speed)
LONG EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, u32 Speed)
{
int Status;
LONG Status;
u16 PhyReg0 = 0;
u16 PhyReg20 = 0;
u32 PhyAddr;
@ -450,7 +450,8 @@ int EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, int Speed)
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0, PhyReg0);
Status |= XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddr, 0,
(PhyReg0 | PHY_REG0_RESET));
sleep(1);
/* FIXME: Sleep doesn't seem to work */
//sleep(1);
Status |= XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, 0, &PhyReg0);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error setup phy speed");
@ -480,14 +481,16 @@ int EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, int Speed)
#define PHY_REG21_100 0x2030
#define PHY_REG21_1000 0x0070
int EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, int Speed)
LONG EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, u32 Speed)
{
int Status;
LONG Status;
u16 PhyReg0 = 0;
u16 PhyReg21 = 0;
u16 PhyReg22 = 0;
u32 PhyAddr;
u32 i =0;
/*
* Detect the PHY address
*/
@ -581,7 +584,9 @@ int EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, int Speed)
/*
* Delay loop
*/
sleep(1);
for(i=0;i<0xfffff;i++);
/* FIXME: Sleep doesn't seem to work */
//sleep(1);
return XST_SUCCESS;
}
@ -603,7 +608,7 @@ int EmacPsUtilEnterLoopback(XEmacPs * EmacPsInstancePtr, int Speed)
*****************************************************************************/
void EmacPsUtilErrorTrap(const char *Message)
{
static int Count = 0;
static u32 Count = 0;
Count++;

194
XilinxProcessorIPLib/drivers/emacps/src/xemacps.c
View file

@ -44,6 +44,9 @@
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
* 64-bit changes.
*
* </pre>
******************************************************************************/
@ -88,8 +91,8 @@ void XEmacPs_StubHandler(void); /* Default handler routine */
* - XST_SUCCESS if initialization was successful
*
******************************************************************************/
int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
u32 EffectiveAddress)
LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
UINTPTR EffectiveAddress)
{
/* Verify arguments */
Xil_AssertNonvoid(InstancePtr != NULL);
@ -100,15 +103,15 @@ int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
InstancePtr->Config.BaseAddress = EffectiveAddress;
/* Set callbacks to an initial stub routine */
InstancePtr->SendHandler = (XEmacPs_Handler) XEmacPs_StubHandler;
InstancePtr->RecvHandler = (XEmacPs_Handler) XEmacPs_StubHandler;
InstancePtr->ErrorHandler = (XEmacPs_ErrHandler) XEmacPs_StubHandler;
InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
/* Reset the hardware and set default options */
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
XEmacPs_Reset(InstancePtr);
return (XST_SUCCESS);
return (LONG)(XST_SUCCESS);
}
@ -145,19 +148,15 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
/* Assert bad arguments and conditions */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
/* If already started, then there is nothing to do */
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
return;
}
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Start DMA */
/* When starting the DMA channels, both transmit and receive sides
* need an initialized BD list.
*/
if (InstancePtr->Version == 2) {
Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXQBASE_OFFSET,
InstancePtr->RxBdRing.BaseBdAddr);
@ -165,37 +164,42 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQBASE_OFFSET,
InstancePtr->TxBdRing.BaseBdAddr);
}
/* clear any existed int status */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
XEMACPS_IXR_ALL_MASK);
/* Enable transmitter if not already enabled */
if (InstancePtr->Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) {
if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
if (!(Reg & XEMACPS_NWCTRL_TXEN_MASK)) {
if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
Reg | XEMACPS_NWCTRL_TXEN_MASK);
Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
}
}
/* Enable receiver if not already enabled */
if (InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) {
if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
if (!(Reg & XEMACPS_NWCTRL_RXEN_MASK)) {
if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
Reg | XEMACPS_NWCTRL_RXEN_MASK);
Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
}
}
/* Enable TX and RX interrupts */
XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
XEMACPS_IXR_RX_ERR_MASK | XEMACPS_IXR_FRAMERX_MASK |
XEMACPS_IXR_TXCOMPL_MASK));
XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
(u32)XEMACPS_IXR_TXCOMPL_MASK));
/* Enable TX Q1 Interrupts */
if (InstancePtr->Version == 7)
XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
/* Mark as started */
InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
@ -234,7 +238,7 @@ void XEmacPs_Stop(XEmacPs *InstancePtr)
u32 Reg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Disable all interrupts */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
@ -243,13 +247,13 @@ void XEmacPs_Stop(XEmacPs *InstancePtr)
/* Disable the receiver & transmitter */
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg &= ~XEMACPS_NWCTRL_RXEN_MASK;
Reg &= ~XEMACPS_NWCTRL_TXEN_MASK;
Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
/* Mark as stopped */
InstancePtr->IsStarted = 0;
InstancePtr->IsStarted = 0U;
}
@ -289,49 +293,71 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
{
u32 Reg;
u8 i;
char EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Stop the device and reset hardware */
XEmacPs_Stop(InstancePtr);
InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
/* Setup hardware with default values */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
(XEMACPS_NWCTRL_STATCLR_MASK |
XEMACPS_NWCTRL_MDEN_MASK) &
~XEMACPS_NWCTRL_LOOPEN_MASK);
(u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET,
XEMACPS_NWCFG_100_MASK |
XEMACPS_NWCFG_FDEN_MASK |
XEMACPS_NWCFG_UCASTHASHEN_MASK);
((u32)XEMACPS_NWCFG_100_MASK |
(u32)XEMACPS_NWCFG_FDEN_MASK |
(u32)XEMACPS_NWCFG_UCASTHASHEN_MASK));
if (InstancePtr->Version == 7) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
XEMACPS_NWCFG_DWIDTH_64_MASK));
}
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET,
((((XEMACPS_RX_BUF_SIZE / XEMACPS_RX_BUF_UNIT) +
((XEMACPS_RX_BUF_SIZE %
XEMACPS_RX_BUF_UNIT) ? 1 : 0)) <<
XEMACPS_DMACR_RXBUF_SHIFT) &
XEMACPS_DMACR_RXBUF_MASK) |
XEMACPS_DMACR_RXSIZE_MASK |
XEMACPS_DMACR_TXSIZE_MASK);
(((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
(((((u32)XEMACPS_RX_BUF_SIZE %
(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
(u32)(XEMACPS_DMACR_RXBUF_MASK)) |
(u32)XEMACPS_DMACR_RXSIZE_MASK |
(u32)XEMACPS_DMACR_TXSIZE_MASK);
/* Single bursts */
/* FIXME: Why Single bursts? */
if (InstancePtr->Version == 7) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
(u32)XEMACPS_DMACR_INCR4_AHB_BURST));
}
#if EXTENDED_DESC_MODE
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
XEMACPS_DMACR_TXEXTEND_MASK |
XEMACPS_DMACR_RXEXTEND_MASK));
#endif
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET, 0x0);
XEMACPS_TXSR_OFFSET, 0x0U);
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
if (InstancePtr->Version == 7)
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXQBASE_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQBASE_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET, 0x0);
XEMACPS_RXSR_OFFSET, 0x0U);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
XEMACPS_IXR_ALL_MASK);
@ -342,26 +368,26 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
Reg);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_PHYMNTNC_OFFSET, 0x0);
XEMACPS_PHYMNTNC_OFFSET, 0x0U);
XEmacPs_ClearHash(InstancePtr);
for (i = 1; i < 5; i++) {
XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
XEmacPs_SetTypeIdCheck(InstancePtr, 0x0, i);
for (i = 1U; i < 5U; i++) {
(void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
(void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
}
/* clear all counters */
for (i = 0; i < (XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4;
for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
i++) {
XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_OCTTXL_OFFSET + i * 4);
(void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
}
/* Disable the receiver */
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg &= ~XEMACPS_NWCTRL_RXEN_MASK;
Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
@ -370,11 +396,11 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
* XEMACPS_TRANSMITTER_ENABLE_OPTION and
* XEMACPS_RECEIVER_ENABLE_OPTION are set.
*/
XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
~(XEMACPS_TRANSMITTER_ENABLE_OPTION |
XEMACPS_RECEIVER_ENABLE_OPTION));
(void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
(u32)XEMACPS_RECEIVER_ENABLE_OPTION));
XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
(void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
}
@ -390,3 +416,53 @@ void XEmacPs_StubHandler(void)
{
Xil_AssertVoidAlways();
}
/*****************************************************************************/
/**
* This function sets the start address of the transmit/receive buffer queue.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @QPtr Address of the Queue to be written
* @QueueNum Buffer Queue Index
* @Direction Transmit/Recive
*
* @note
* The buffer queue addresses has to be set before starting the transfer, so
* this function has to be called in prior to XEmacPs_Start()
*
******************************************************************************/
void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
u16 Direction)
{
/* Assert bad arguments and conditions */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* If already started, then there is nothing to do */
if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
return;
}
if (QueueNum == 0x00U) {
if (Direction == XEMACPS_SEND) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQBASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
} else {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXQBASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
}
}
else {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQ1BASE_OFFSET,
(QPtr & ULONG64_LO_MASK));
}
#if EXTENDED_DESC_MODE
/* Set the MSB of Queue start address */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_MSBBUF_QBASE_OFFSET,
(u32)((QPtr & (u32)ULONG64_HI_MASK) >> 32U));
#endif
}

160
XilinxProcessorIPLib/drivers/emacps/src/xemacps.h
View file

@ -296,6 +296,8 @@
* 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
* address in xparameters.h when GMII to RGMII converter
* is present in hw.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
* changes.
* 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
* 1000BASE-X mode export proper values to the xparameters.h
* file. Changes are made in the driver tcl file.
@ -341,32 +343,32 @@ extern "C" {
* @{
*/
#define XEMACPS_PROMISC_OPTION 0x00000001
#define XEMACPS_PROMISC_OPTION 0x00000001U
/**< Accept all incoming packets.
* This option defaults to disabled (cleared) */
#define XEMACPS_FRAME1536_OPTION 0x00000002
#define XEMACPS_FRAME1536_OPTION 0x00000002U
/**< Frame larger than 1516 support for Tx & Rx.
* This option defaults to disabled (cleared) */
#define XEMACPS_VLAN_OPTION 0x00000004
#define XEMACPS_VLAN_OPTION 0x00000004U
/**< VLAN Rx & Tx frame support.
* This option defaults to disabled (cleared) */
#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010
#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
/**< Enable recognition of flow control frames on Rx
* This option defaults to enabled (set) */
#define XEMACPS_FCS_STRIP_OPTION 0x00000020
#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
* stripped.
* This option defaults to enabled (set) */
#define XEMACPS_FCS_INSERT_OPTION 0x00000040
#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
/**< Generate FCS field and add PAD automatically for outgoing frames.
* This option defaults to disabled (cleared) */
#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080
#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
/**< Enable Length/Type error checking for incoming frames. When this option is
* set, the MAC will filter frames that have a mismatched type/length field
* and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
@ -375,41 +377,41 @@ extern "C" {
*
* This option defaults to disabled (cleared) */
#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100
#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
/**< Enable the transmitter.
* This option defaults to enabled (set) */
#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200
#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
/**< Enable the receiver
* This option defaults to enabled (set) */
#define XEMACPS_BROADCAST_OPTION 0x00000400
#define XEMACPS_BROADCAST_OPTION 0x00000400U
/**< Allow reception of the broadcast address
* This option defaults to enabled (set) */
#define XEMACPS_MULTICAST_OPTION 0x00000800
#define XEMACPS_MULTICAST_OPTION 0x00000800U
/**< Allows reception of multicast addresses programmed into hash
* This option defaults to disabled (clear) */
#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000
#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
/**< Enable the RX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000
#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
/**< Enable the TX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_DEFAULT_OPTIONS \
(XEMACPS_FLOW_CONTROL_OPTION | \
XEMACPS_FCS_INSERT_OPTION | \
XEMACPS_FCS_STRIP_OPTION | \
XEMACPS_BROADCAST_OPTION | \
XEMACPS_LENTYPE_ERR_OPTION | \
XEMACPS_TRANSMITTER_ENABLE_OPTION | \
XEMACPS_RECEIVER_ENABLE_OPTION | \
XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
XEMACPS_TX_CHKSUM_ENABLE_OPTION)
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
@ -419,9 +421,9 @@ extern "C" {
* These constants are used as parameters to XEmacPs_SetHandler()
* @{
*/
#define XEMACPS_HANDLER_DMASEND 1
#define XEMACPS_HANDLER_DMARECV 2
#define XEMACPS_HANDLER_ERROR 3
#define XEMACPS_HANDLER_DMASEND 1U
#define XEMACPS_HANDLER_DMARECV 2U
#define XEMACPS_HANDLER_ERROR 3U
/*@}*/
/* Constants to determine the configuration of the hardware device. They are
@ -432,12 +434,12 @@ extern "C" {
/* The next few constants help upper layers determine the size of memory
* pools used for Ethernet buffers and descriptor lists.
*/
#define XEMACPS_MAC_ADDR_SIZE 6 /* size of Ethernet header */
#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
#define XEMACPS_MTU 1500 /* max MTU size of Ethernet frame */
#define XEMACPS_HDR_SIZE 14 /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
@ -445,10 +447,10 @@ extern "C" {
/* DMACR Bust length hash defines */
#define XEMACPS_SINGLE_BURST 1
#define XEMACPS_4BYTE_BURST 4
#define XEMACPS_8BYTE_BURST 8
#define XEMACPS_16BYTE_BURST 16
#define XEMACPS_SINGLE_BURST 0x00000001
#define XEMACPS_4BYTE_BURST 0x00000004
#define XEMACPS_8BYTE_BURST 0x00000008
#define XEMACPS_16BYTE_BURST 0x00000010
/**************************** Type Definitions ******************************/
@ -490,7 +492,7 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress;/**< Physical base address of IPIF registers */
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
} XEmacPs_Config;
@ -499,7 +501,7 @@ typedef struct {
* structure of this type for every XEmacPs device in the system. A pointer
* to a structure of this type is then passed to the driver API functions.
*/
typedef struct XEmacPs {
typedef struct XEmacPs_Instance {
XEmacPs_Config Config; /* Hardware configuration */
u32 IsStarted; /* Device is currently started */
u32 IsReady; /* Device is initialized and ready */
@ -515,6 +517,7 @@ typedef struct XEmacPs {
XEmacPs_ErrHandler ErrorHandler;
void *ErrorRef;
u32 Version;
} XEmacPs;
@ -572,7 +575,7 @@ typedef struct XEmacPs {
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
(Mask & XEMACPS_IXR_ALL_MASK));
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -593,7 +596,49 @@ typedef struct XEmacPs {
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
(Mask & XEMACPS_IXR_ALL_MASK));
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -610,9 +655,9 @@ typedef struct XEmacPs {
*
*****************************************************************************/
#define XEmacPs_Transmit(InstancePtr) \
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
/****************************************************************************/
@ -635,7 +680,7 @@ typedef struct XEmacPs {
*****************************************************************************/
#define XEmacPs_IsRxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
/****************************************************************************/
@ -658,7 +703,7 @@ typedef struct XEmacPs {
*****************************************************************************/
#define XEmacPs_IsTxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
/************************** Function Prototypes *****************************/
@ -666,11 +711,13 @@ typedef struct XEmacPs {
/*
* Initialization functions in xemacps.c
*/
int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
u32 EffectiveAddress);
LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
UINTPTR EffectiveAddress);
void XEmacPs_Start(XEmacPs *InstancePtr);
void XEmacPs_Stop(XEmacPs *InstancePtr);
void XEmacPs_Reset(XEmacPs *InstancePtr);
void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
u16 Direction);
/*
* Lookup configuration in xemacps_sinit.c
@ -681,21 +728,22 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
* Interrupt-related functions in xemacps_intr.c
* DMA only and FIFO is not supported. This DMA does not support coalescing.
*/
int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPtr, void *CallBackRef);
void XEmacPs_IntrHandler(void *InstancePtr);
LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPointer, void *CallBackRef);
void XEmacPs_IntrHandler(void *XEmacPsPtr);
/*
* MAC configuration/control functions in XEmacPs_control.c
*/
int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
@ -703,14 +751,14 @@ void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 *PhyDataPtr);
int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 PhyData);
int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
int XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength);
LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
#ifdef __cplusplus
}

163
XilinxProcessorIPLib/drivers/emacps/src/xemacps_bd.h
View file

@ -61,6 +61,9 @@
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Ronaldo GEM specification and 64-bit
* changes.
*
* </pre>
*
* ***************************************************************************
@ -82,15 +85,21 @@ extern "C" {
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
#ifdef __aarch64__
#define EXTENDED_DESC_MODE 1
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
#else
#define EXTENDED_DESC_MODE 0
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
#endif
/**
* The XEmacPs_Bd is the type for buffer descriptors (BDs).
*/
#define XEMACPS_BD_NUM_WORDS 2
typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
#define XEMACPS_BD_NUM_WORDS 2U
typedef UINTPTR XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
/***************** Macros (Inline Functions) Definitions *********************/
@ -123,11 +132,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdRead(u32 BaseAddress, u32 Offset)
* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
*
*****************************************************************************/
#define XEmacPs_BdRead(BaseAddress, Offset) \
(*(u32*)((u32)(BaseAddress) + (u32)(Offset)))
(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
/****************************************************************************/
/**
@ -142,11 +151,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* void XEmacPs_BdWrite(u32 BaseAddress, u32 Offset, u32 Data)
* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
(*(u32*)((u32)(BaseAddress) + (u32)(Offset)) = (Data))
(*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
/*****************************************************************************/
/**
@ -158,12 +167,19 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* @note :
*
* C-style signature:
* void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, u32 Addr)
* void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#if EXTENDED_DESC_MODE
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr)))
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
(u32)((Addr) & ULONG64_LO_MASK)); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
#endif
/*****************************************************************************/
/**
@ -176,14 +192,22 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* read-modify-write is performed.
*
* C-style signature:
* void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, u32 Addr)
* void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#if EXTENDED_DESC_MODE
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | (u32)(Addr)))
~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
#endif
/*****************************************************************************/
/**
@ -194,12 +218,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, u32 Data)
* void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdSetStatus(BdPtr, Data) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | Data)
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
/*****************************************************************************/
@ -229,11 +253,36 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#ifdef EXTENDED_DESC_MODE
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
#else
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |)
#endif
/*****************************************************************************/
/**
* Set transfer length in bytes for the given BD. The length must be set each
* time a BD is submitted to hardware.
*
* @param BdPtr is the BD pointer to operate on
* @param LenBytes is the number of bytes to transfer.
*
* @note
* C-style signature:
* void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
*
*****************************************************************************/
#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
/*****************************************************************************/
@ -271,7 +320,7 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
* XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
*
*****************************************************************************/
@ -290,12 +339,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsLast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -346,11 +395,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetRxWrap(BdPtr) \
/*#define XEmacPs_BdSetRxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
XEMACPS_RXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
@ -361,12 +410,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
* u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_WRAP_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -381,11 +430,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxWrap(BdPtr) \
/*#define XEmacPs_BdSetTxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
@ -396,12 +445,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
* u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_WRAP_MASK) ? TRUE : FALSE)
XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -432,12 +481,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxNew(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_NEW_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -487,12 +536,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUsed(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_USED_MASK) ? TRUE : FALSE)
XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -503,12 +552,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxRetry(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_RETRY_MASK) ? TRUE : FALSE)
XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -520,12 +569,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUrun(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_URUN_MASK) ? TRUE : FALSE)
XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -537,12 +586,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxExh(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_EXH_MASK) ? TRUE : FALSE)
XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -558,7 +607,7 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* u32 XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxNoCRC(BdPtr) \
@ -580,7 +629,7 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* u32 XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxNoCRC(BdPtr) \
@ -597,12 +646,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxBcast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_BCAST_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -613,12 +662,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxMultiHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_MULTIHASH_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -629,12 +678,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxUniHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_UNIHASH_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -645,12 +694,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxVlan(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_VLAN_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -662,12 +711,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxPri(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_PRI_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -679,12 +728,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxCFI(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_CFI_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -695,12 +744,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxEOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
@ -711,12 +760,12 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
* UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxSOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_SOF_MASK) ? TRUE : FALSE)
XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
/************************** Function Prototypes ******************************/

554
XilinxProcessorIPLib/drivers/emacps/src/xemacps_bdring.c
View file

@ -54,6 +54,8 @@
* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
* removed. It is expected that all BDs are allocated in
* from uncached area. Fix for CR #663885.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
*
* </pre>
******************************************************************************/
@ -82,7 +84,7 @@
* @note Assume BdPtr is always a valid BD in the ring
****************************************************************************/
#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
((u32)BdPtr + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
/****************************************************************************
* Compute the physical address of a descriptor from its virtual address
@ -94,7 +96,7 @@
* @note Assume BdPtr is always a valid BD in the ring
****************************************************************************/
#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
((u32)BdPtr - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
/****************************************************************************
* Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
@ -113,15 +115,15 @@
****************************************************************************/
#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \
{ \
u32 Addr = (u32)BdPtr; \
UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
\
Addr += ((RingPtr)->Separation * NumBd); \
if ((Addr > (RingPtr)->HighBdAddr) || ((u32)BdPtr > Addr)) \
Addr += ((RingPtr)->Separation * (NumBd)); \
if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \
{ \
Addr -= (RingPtr)->Length; \
} \
\
BdPtr = (XEmacPs_Bd*)Addr; \
(BdPtr) = (XEmacPs_Bd*)(void *)Addr; \
}
/****************************************************************************
@ -141,20 +143,22 @@
****************************************************************************/
#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \
{ \
u32 Addr = (u32)BdPtr; \
UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
\
Addr -= ((RingPtr)->Separation * NumBd); \
if ((Addr < (RingPtr)->BaseBdAddr) || ((u32)BdPtr < Addr)) \
Addr -= ((RingPtr)->Separation * (NumBd)); \
if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \
{ \
Addr += (RingPtr)->Length; \
} \
\
BdPtr = (XEmacPs_Bd*)Addr; \
(BdPtr) = (XEmacPs_Bd*)(void*)Addr; \
}
/************************** Function Prototypes ******************************/
static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
/************************** Variable Definitions *****************************/
@ -181,9 +185,9 @@
* channel.
* - XST_INVALID_PARAM under any of the following conditions:
* 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
* parameter;
* parameter.
* 2) Alignment parameter does not meet minimum requirements or is not a
* power of 2 value;
* power of 2 value.
* 3) BdCount is 0.
* - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
* over address 0x00000000 in virtual address space.
@ -191,84 +195,85 @@
* @note
* Make sure to pass in the right alignment value.
*****************************************************************************/
int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr,
u32 VirtAddr, u32 Alignment, unsigned BdCount)
LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
{
unsigned i;
u32 BdVirtAddr;
u32 BdPhyAddr;
u32 i;
UINTPTR BdVirtAddr;
UINTPTR BdPhyAddr;
UINTPTR VirtAddrLoc = VirtAddr;
/* In case there is a failure prior to creating list, make sure the
* following attributes are 0 to prevent calls to other functions
* from doing anything.
*/
RingPtr->AllCnt = 0;
RingPtr->FreeCnt = 0;
RingPtr->HwCnt = 0;
RingPtr->PreCnt = 0;
RingPtr->PostCnt = 0;
RingPtr->AllCnt = 0U;
RingPtr->FreeCnt = 0U;
RingPtr->HwCnt = 0U;
RingPtr->PreCnt = 0U;
RingPtr->PostCnt = 0U;
/* Make sure Alignment parameter meets minimum requirements */
if (Alignment < XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
return (XST_INVALID_PARAM);
if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
return (LONG)(XST_INVALID_PARAM);
}
/* Make sure Alignment is a power of 2 */
if ((Alignment - 1) & Alignment) {
return (XST_INVALID_PARAM);
if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
return (LONG)(XST_INVALID_PARAM);
}
/* Make sure PhysAddr and VirtAddr are on same Alignment */
if ((PhysAddr % Alignment) || (VirtAddr % Alignment)) {
return (XST_INVALID_PARAM);
if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
return (LONG)(XST_INVALID_PARAM);
}
/* Is BdCount reasonable? */
if (BdCount == 0) {
return (XST_INVALID_PARAM);
if (BdCount == 0x00000000U) {
return (LONG)(XST_INVALID_PARAM);
}
/* Figure out how many bytes will be between the start of adjacent BDs */
RingPtr->Separation =
(sizeof(XEmacPs_Bd) + (Alignment - 1)) & ~(Alignment - 1);
((u32)sizeof(XEmacPs_Bd) + (Alignment - (u32)1)) & ~(Alignment - (u32)1);
/* Must make sure the ring doesn't span address 0x00000000. If it does,
* then the next/prev BD traversal macros will fail.
*/
if (VirtAddr > (VirtAddr + (RingPtr->Separation * BdCount) - 1)) {
return (XST_DMA_SG_LIST_ERROR);
if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
/* Initial ring setup:
* - Clear the entire space
* - Setup each BD's BDA field with the physical address of the next BD
*/
memset((void *) VirtAddr, 0, (RingPtr->Separation * BdCount));
(void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
BdVirtAddr = VirtAddr;
BdVirtAddr = VirtAddrLoc;
BdPhyAddr = PhysAddr + RingPtr->Separation;
for (i = 1; i < BdCount; i++) {
for (i = 1U; i < BdCount; i++) {
BdVirtAddr += RingPtr->Separation;
BdPhyAddr += RingPtr->Separation;
}
/* Setup and initialize pointers and counters */
RingPtr->RunState = XST_DMA_SG_IS_STOPPED;
RingPtr->BaseBdAddr = VirtAddr;
RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
RingPtr->BaseBdAddr = VirtAddrLoc;
RingPtr->PhysBaseAddr = PhysAddr;
RingPtr->HighBdAddr = BdVirtAddr;
RingPtr->Length =
RingPtr->HighBdAddr - RingPtr->BaseBdAddr + RingPtr->Separation;
RingPtr->AllCnt = BdCount;
RingPtr->FreeCnt = BdCount;
RingPtr->FreeHead = (XEmacPs_Bd *) VirtAddr;
RingPtr->PreHead = (XEmacPs_Bd *) VirtAddr;
RingPtr->HwHead = (XEmacPs_Bd *) VirtAddr;
RingPtr->HwTail = (XEmacPs_Bd *) VirtAddr;
RingPtr->PostHead = (XEmacPs_Bd *) VirtAddr;
RingPtr->BdaRestart = (XEmacPs_Bd *) PhysAddr;
((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
RingPtr->AllCnt = (u32)BdCount;
RingPtr->FreeCnt = (u32)BdCount;
RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
return (XST_SUCCESS);
return (LONG)(XST_SUCCESS);
}
@ -296,37 +301,38 @@ int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr,
* - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
*
*****************************************************************************/
int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
u8 Direction)
{
unsigned i;
u32 CurBd;
u32 i;
UINTPTR CurBd;
/* Can't do this function if there isn't a ring */
if (RingPtr->AllCnt == 0) {
return (XST_DMA_SG_NO_LIST);
if (RingPtr->AllCnt == 0x00000000U) {
return (LONG)(XST_DMA_SG_NO_LIST);
}
/* Can't do this function with the channel running */
if (RingPtr->RunState == XST_DMA_SG_IS_STARTED) {
return (XST_DEVICE_IS_STARTED);
if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
return (LONG)(XST_DEVICE_IS_STARTED);
}
/* Can't do this function with some of the BDs in use */
if (RingPtr->FreeCnt != RingPtr->AllCnt) {
return (XST_DMA_SG_LIST_ERROR);
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
if ((Direction != XEMACPS_SEND) && (Direction != XEMACPS_RECV)) {
return (XST_INVALID_PARAM);
if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
return (LONG)(XST_INVALID_PARAM);
}
/* Starting from the top of the ring, save BD.Next, overwrite the entire
* BD with the template, then restore BD.Next
*/
for (i = 0, CurBd = (u32) RingPtr->BaseBdAddr;
i < RingPtr->AllCnt; i++, CurBd += RingPtr->Separation) {
CurBd = RingPtr->BaseBdAddr;
for (i = 0U; i < RingPtr->AllCnt; i++) {
memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
CurBd += RingPtr->Separation;
}
CurBd -= RingPtr->Separation;
@ -338,7 +344,7 @@ int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
XEmacPs_BdSetTxWrap(CurBd);
}
return (XST_SUCCESS);
return (LONG)(XST_SUCCESS);
}
@ -350,45 +356,45 @@ int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
* order which they were allocated here. Example:
*
* <pre>
* NumBd = 2;
* Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet);
* NumBd = 2,
* Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
*
* if (Status != XST_SUCCESS)
* {
* // Not enough BDs available for the request
* *Not enough BDs available for the request*
* }
*
* CurBd = MyBdSet;
* CurBd = MyBdSet,
* for (i=0; i<NumBd; i++)
* {
* // Prepare CurBd.....
* * Prepare CurBd *.....
*
* // Onto next BD
* CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd);
* * Onto next BD *
* CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
* }
*
* // Give list to hardware
* Status = XEmacPs_BdRingToHw(MyRingPtr, NumBd, MyBdSet);
* * Give list to hardware *
* Status = XEmacPs_BdRingToHw(MyRingPtr, NumBd, MyBdSet),
* </pre>
*
* A more advanced use of this function may allocate multiple sets of BDs.
* They must be allocated and given to hardware in the correct sequence:
* <pre>
* // Legal
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
* XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1);
* * Legal *
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
* XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
*
* // Legal
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2);
* XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1);
* XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2);
* * Legal *
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
* XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
* XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
*
* // Not legal
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2);
* XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2);
* XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1);
* * Not legal *
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
* XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
* XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
* XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
* </pre>
*
* Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
@ -414,20 +420,22 @@ int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
* instability.
*
*****************************************************************************/
int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd ** BdSetPtr)
{
LONG Status;
/* Enough free BDs available for the request? */
if (RingPtr->FreeCnt < NumBd) {
return (XST_FAILURE);
}
Status = (LONG)(XST_FAILURE);
} else {
/* Set the return argument and move FreeHead forward */
*BdSetPtr = RingPtr->FreeHead;
XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
RingPtr->FreeCnt -= NumBd;
RingPtr->PreCnt += NumBd;
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
return Status;
}
/*****************************************************************************/
@ -448,30 +456,30 @@ int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
* Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
*
* <pre>
* Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr);
* Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
* ...
* if (Error)
* {
* Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr);
* Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
* }
* </pre>
*
* A partial UnAlloc means some of the BDs Alloc'd will be returned:
*
* <pre>
* Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr);
* BdsLeft = 10;
* CurBdPtr = BdPtr;
* Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
* BdsLeft = 10,
* CurBdPtr = BdPtr,
*
* while (BdsLeft)
* {
* if (Error)
* {
* Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr);
* Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
* }
*
* CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr);
* BdsLeft--;
* CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
* BdsLeft--,
* }
* </pre>
*
@ -492,21 +500,25 @@ int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
* provide a mutual exclusion mechanism.
*
*****************************************************************************/
int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr)
{
(void)BdSetPtr;
LONG Status;
(void *)BdSetPtr;
Xil_AssertNonvoid(RingPtr != NULL);
Xil_AssertNonvoid(BdSetPtr != NULL);
/* Enough BDs in the free state for the request? */
if (RingPtr->PreCnt < NumBd) {
return (XST_FAILURE);
}
Status = (LONG)(XST_FAILURE);
} else {
/* Set the return argument and move FreeHead backward */
XEMACPS_RING_SEEKBACK(RingPtr, RingPtr->FreeHead, NumBd);
XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
RingPtr->FreeCnt += NumBd;
RingPtr->PreCnt -= NumBd;
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
return Status;
}
@ -536,34 +548,34 @@ int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
* provide a mutual exclusion mechanism.
*
*****************************************************************************/
int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd,
LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr)
{
XEmacPs_Bd *CurBdPtr;
unsigned i;
u32 i;
LONG Status;
/* if no bds to process, simply return. */
if (0 == NumBd)
return (XST_SUCCESS);
if (0U == NumBd){
Status = (LONG)(XST_SUCCESS);
} else {
/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
return (XST_DMA_SG_LIST_ERROR);
}
Status = (LONG)(XST_DMA_SG_LIST_ERROR);
} else {
CurBdPtr = BdSetPtr;
for (i = 0; i < NumBd; i++) {
CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
for (i = 0U; i < NumBd; i++) {
CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
}
/* Adjust ring pointers & counters */
XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
RingPtr->PreCnt -= NumBd;
RingPtr->HwTail = CurBdPtr;
RingPtr->HwCnt += NumBd;
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
}
return Status;
}
@ -575,44 +587,43 @@ int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd,
* in the same order which they were retrieved here. Example:
*
* <pre>
* NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet);
*
* NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
* if (NumBd == 0)
* {
* // hardware has nothing ready for us yet
* * hardware has nothing ready for us yet*
* }
*
* CurBd = MyBdSet;
* CurBd = MyBdSet,
* for (i=0; i<NumBd; i++)
* {
* // Examine CurBd for post processing.....
* * Examine CurBd for post processing *.....
*
* // Onto next BD
* CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd);
* * Onto next BD *
* CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
* }
*
* XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet); // Return list
* XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet), *Return list*
* }
* </pre>
*
* A more advanced use of this function may allocate multiple sets of BDs.
* They must be retrieved from hardware and freed in the correct sequence:
* <pre>
* // Legal
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1);
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
* * Legal *
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
*
* // Legal
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1);
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2);
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
* XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2);
* * Legal *
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
* XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
*
* // Not legal
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1);
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2);
* XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2);
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
* * Not legal *
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
* XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
* XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
* </pre>
*
* If hardware has only partially completed a packet spanning multiple BDs,
@ -634,43 +645,45 @@ int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd,
* provide a mutual exclusion mechanism.
*
*****************************************************************************/
unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr)
{
XEmacPs_Bd *CurBdPtr;
u32 BdStr = 0;
unsigned BdCount;
unsigned BdPartialCount;
unsigned int Sop = 0;
u32 BdStr = 0U;
u32 BdCount;
u32 BdPartialCount;
u32 Sop = 0U;
u32 BdLimitLoc = BdLimit;
CurBdPtr = RingPtr->HwHead;
BdCount = 0;
BdPartialCount = 0;
BdCount = 0U;
BdPartialCount = 0U;
u32 Status;
/* If no BDs in work group, then there's nothing to search */
if (RingPtr->HwCnt == 0) {
if (RingPtr->HwCnt == 0x00000000U) {
*BdSetPtr = NULL;
return (0);
Status = 0U;
} else {
if (BdLimitLoc > RingPtr->HwCnt){
BdLimitLoc = RingPtr->HwCnt;
}
if (BdLimit > RingPtr->HwCnt)
BdLimit = RingPtr->HwCnt;
/* Starting at HwHead, keep moving forward in the list until:
* - A BD is encountered with its new/used bit set which means
* hardware has not completed processing of that BD.
* - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
* - The number of requested BDs has been processed
*/
while (BdCount < BdLimit) {
while (BdCount < BdLimitLoc) {
/* Read the status */
if(CurBdPtr != NULL){
BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
}
if ((Sop == 0) && (BdStr & XEMACPS_TXBUF_USED_MASK))
Sop = 1;
if (Sop == 1) {
if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
Sop = 1U;
}
if (Sop == 0x00000001U) {
BdCount++;
BdPartialCount++;
}
@ -679,9 +692,9 @@ unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
* If it is clear, then there are more BDs for the current
* packet. Keep a count of these partial packet BDs.
*/
if ((Sop == 1) && (BdStr & XEMACPS_TXBUF_LAST_MASK)) {
Sop = 0;
BdPartialCount = 0;
if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
Sop = 0U;
BdPartialCount = 0U;
}
/* Move on to next BD in work group */
@ -694,17 +707,18 @@ unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
/* If BdCount is non-zero then BDs were found to return. Set return
* parameters, update pointers and counters, return success
*/
if (BdCount > 0) {
if (BdCount > 0x00000000U) {
*BdSetPtr = RingPtr->HwHead;
RingPtr->HwCnt -= BdCount;
RingPtr->PostCnt += BdCount;
XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
return (BdCount);
Status = (BdCount);
} else {
*BdSetPtr = NULL;
Status = 0U;
}
else {
*BdSetPtr = NULL;
return (0);
}
return Status;
}
@ -716,44 +730,44 @@ unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
* in the same order which they were retrieved here. Example:
*
* <pre>
* NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet);
* NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
*
* if (NumBd == 0)
* {
* // hardware has nothing ready for us yet
* *hardware has nothing ready for us yet*
* }
*
* CurBd = MyBdSet;
* CurBd = MyBdSet,
* for (i=0; i<NumBd; i++)
* {
* // Examine CurBd for post processing.....
* * Examine CurBd for post processing *.....
*
* // Onto next BD
* CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd);
* * Onto next BD *
* CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
* }
*
* XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet); // Return list
* XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet), * Return list *
* }
* </pre>
*
* A more advanced use of this function may allocate multiple sets of BDs.
* They must be retrieved from hardware and freed in the correct sequence:
* <pre>
* // Legal
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1);
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
* * Legal *
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
*
* // Legal
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1);
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2);
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
* XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2);
* * Legal *
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
* XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
*
* // Not legal
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1);
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2);
* XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2);
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
* * Not legal *
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
* XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
* XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
* XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
* </pre>
*
* If hardware has only partially completed a packet spanning multiple BDs,
@ -775,23 +789,24 @@ unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
* provide a mutual exclusion mechanism.
*
*****************************************************************************/
unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr)
{
XEmacPs_Bd *CurBdPtr;
u32 BdStr = 0;
unsigned BdCount;
unsigned BdPartialCount;
u32 BdStr = 0U;
u32 BdCount;
u32 BdPartialCount;
u32 Status;
CurBdPtr = RingPtr->HwHead;
BdCount = 0;
BdPartialCount = 0;
BdCount = 0U;
BdPartialCount = 0U;
/* If no BDs in work group, then there's nothing to search */
if (RingPtr->HwCnt == 0) {
if (RingPtr->HwCnt == 0x00000000U) {
*BdSetPtr = NULL;
return (0);
}
Status = 0U;
} else {
/* Starting at HwHead, keep moving forward in the list until:
* - A BD is encountered with its new/used bit set which means
@ -802,9 +817,10 @@ unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
while (BdCount < BdLimit) {
/* Read the status */
if(CurBdPtr!=NULL){
BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
if (!(XEmacPs_BdIsRxNew(CurBdPtr))) {
}
if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
break;
}
@ -814,10 +830,9 @@ unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
* it is clear, then there are more BDs for the current packet.
* Keep a count of these partial packet BDs.
*/
if (BdStr & XEMACPS_RXBUF_EOF_MASK) {
BdPartialCount = 0;
}
else {
if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
BdPartialCount = 0U;
} else {
BdPartialCount++;
}
@ -831,18 +846,20 @@ unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
/* If BdCount is non-zero then BDs were found to return. Set return
* parameters, update pointers and counters, return success
*/
if (BdCount > 0) {
if (BdCount > 0x00000000U) {
*BdSetPtr = RingPtr->HwHead;
RingPtr->HwCnt -= BdCount;
RingPtr->PostCnt += BdCount;
XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
return (BdCount);
Status = (BdCount);
}
else {
*BdSetPtr = NULL;
return (0);
Status = 0U;
}
}
return Status;
}
/*****************************************************************************/
@ -865,23 +882,26 @@ unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
* provide a mutual exclusion mechanism.
*
*****************************************************************************/
int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd,
LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr)
{
LONG Status;
/* if no bds to process, simply return. */
if (0 == NumBd)
return (XST_SUCCESS);
if (0x00000000U == NumBd){
Status = (LONG)(XST_SUCCESS);
} else {
/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
return (XST_DMA_SG_LIST_ERROR);
}
Status = (LONG)(XST_DMA_SG_LIST_ERROR);
} else {
/* Update pointers and counters */
RingPtr->FreeCnt += NumBd;
RingPtr->PostCnt -= NumBd;
XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
}
return Status;
}
@ -913,70 +933,70 @@ int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd,
* provide a mutual exclusion mechanism.
*
*****************************************************************************/
int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
{
u32 AddrV, AddrP;
unsigned i;
UINTPTR AddrV, AddrP;
u32 i;
if ((Direction != XEMACPS_SEND) && (Direction != XEMACPS_RECV)) {
return (XST_INVALID_PARAM);
if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
return (LONG)(XST_INVALID_PARAM);
}
/* Is the list created */
if (RingPtr->AllCnt == 0) {
return (XST_DMA_SG_NO_LIST);
if (RingPtr->AllCnt == 0x00000000U) {
return (LONG)(XST_DMA_SG_NO_LIST);
}
/* Can't check if channel is running */
if (RingPtr->RunState == XST_DMA_SG_IS_STARTED) {
return (XST_IS_STARTED);
if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
return (LONG)(XST_IS_STARTED);
}
/* RunState doesn't make sense */
else if (RingPtr->RunState != XST_DMA_SG_IS_STOPPED) {
return (XST_DMA_SG_LIST_ERROR);
if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
/* Verify internal pointers point to correct memory space */
AddrV = (u32) RingPtr->FreeHead;
AddrV = (UINTPTR) RingPtr->FreeHead;
if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
return (XST_DMA_SG_LIST_ERROR);
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
AddrV = (u32) RingPtr->PreHead;
AddrV = (UINTPTR) RingPtr->PreHead;
if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
return (XST_DMA_SG_LIST_ERROR);
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
AddrV = (u32) RingPtr->HwHead;
AddrV = (UINTPTR) RingPtr->HwHead;
if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
return (XST_DMA_SG_LIST_ERROR);
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
AddrV = (u32) RingPtr->HwTail;
AddrV = (UINTPTR) RingPtr->HwTail;
if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
return (XST_DMA_SG_LIST_ERROR);
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
AddrV = (u32) RingPtr->PostHead;
AddrV = (UINTPTR) RingPtr->PostHead;
if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
return (XST_DMA_SG_LIST_ERROR);
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
/* Verify internal counters add up */
if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
RingPtr->PostCnt) != RingPtr->AllCnt) {
return (XST_DMA_SG_LIST_ERROR);
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
/* Verify BDs are linked correctly */
AddrV = RingPtr->BaseBdAddr;
AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
for (i = 1; i < RingPtr->AllCnt; i++) {
for (i = 1U; i < RingPtr->AllCnt; i++) {
/* Check BDA for this BD. It should point to next physical addr */
if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
return (XST_DMA_SG_LIST_ERROR);
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
/* Move on to next BD */
@ -986,16 +1006,68 @@ int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
/* Last BD should have wrap bit set */
if (XEMACPS_SEND == Direction) {
if (!XEmacPs_BdIsTxWrap(AddrV)) {
return (XST_DMA_SG_LIST_ERROR);
if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
}
else { /* XEMACPS_RECV */
if (!XEmacPs_BdIsRxWrap(AddrV)) {
return (XST_DMA_SG_LIST_ERROR);
if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
return (LONG)(XST_DMA_SG_LIST_ERROR);
}
}
/* No problems found */
return (XST_SUCCESS);
return (LONG)(XST_SUCCESS);
}
/*****************************************************************************/
/**
* Set this bit to mark the last descriptor in the receive buffer descriptor
* list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
{
u32 DataValueRx;
u32 *TempPtr;
BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
TempPtr = (u32 *)BdPtr;
if(TempPtr != NULL) {
DataValueRx = *TempPtr;
DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
*TempPtr = DataValueRx;
}
}
/*****************************************************************************/
/**
* Sets this bit to mark the last descriptor in the transmit buffer
* descriptor list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
{
u32 DataValueTx;
u32 *TempPtr;
BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
TempPtr = (u32 *)BdPtr;
if(TempPtr != NULL) {
DataValueTx = *TempPtr;
DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
*TempPtr = DataValueTx;
}
}

52
XilinxProcessorIPLib/drivers/emacps/src/xemacps_bdring.h
View file

@ -44,6 +44,8 @@
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
*
* </pre>
*
******************************************************************************/
@ -60,9 +62,9 @@ extern "C" {
/** This is an internal structure used to maintain the DMA list */
typedef struct {
u32 PhysBaseAddr;/**< Physical address of 1st BD in list */
u32 BaseBdAddr; /**< Virtual address of 1st BD in list */
u32 HighBdAddr; /**< Virtual address of last BD in the list */
UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
u32 RunState; /**< Flag to indicate DMA is started */
u32 Separation; /**< Number of bytes between the starting address
@ -76,11 +78,12 @@ typedef struct {
/**< First BD in the post-work group */
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
unsigned HwCnt; /**< Number of BDs in work group */
unsigned PreCnt; /**< Number of BDs in pre-work group */
unsigned FreeCnt; /**< Number of allocatable BDs in the free group */
unsigned PostCnt; /**< Number of BDs in post-work group */
unsigned AllCnt; /**< Total Number of BDs for channel */
u32 HwCnt; /**< Number of BDs in work group */
u32 PreCnt; /**< Number of BDs in pre-work group */
u32 FreeCnt; /**< Number of allocatable BDs in the free group */
u32 PostCnt; /**< Number of BDs in post-work group */
u32 AllCnt; /**< Total Number of BDs for channel */
} XEmacPs_BdRing;
@ -128,7 +131,7 @@ typedef struct {
******************************************************************************/
#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
(u32)((sizeof(XEmacPs_Bd) + ((Alignment)-1)) & \
~((Alignment)-1)) * (NumBd)
~((Alignment)-1)) * ((NumBd))
/****************************************************************************/
/**
@ -178,9 +181,9 @@ typedef struct {
*
*****************************************************************************/
#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
(((u32)(BdPtr) >= (RingPtr)->HighBdAddr) ? \
(XEmacPs_Bd*)(RingPtr)->BaseBdAddr : \
(XEmacPs_Bd*)((u32)(BdPtr) + (RingPtr)->Separation))
(((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
(XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
(XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
/****************************************************************************/
/**
@ -198,32 +201,33 @@ typedef struct {
*
*****************************************************************************/
#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
(((u32)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
(((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
(XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
(XEmacPs_Bd*)((u32)(BdPtr) - (RingPtr)->Separation))
(XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
/************************** Function Prototypes ******************************/
/*
* Scatter gather DMA related functions in xemacps_bdring.c
*/
int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr,
u32 VirtAddr, u32 Alignment, unsigned BdCount);
int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
u8 Direction);
int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd ** BdSetPtr);
int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd,
LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd,
LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
#ifdef __cplusplus
}

448
XilinxProcessorIPLib/drivers/emacps/src/xemacps_control.c
View file

@ -47,6 +47,7 @@
* 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
* register. Added a new API for setting the BURST length
* in DMACR register.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* </pre>
*****************************************************************************/
@ -83,46 +84,49 @@
* - XST_DEVICE_IS_STARTED if the device has not yet been stopped
*
*****************************************************************************/
int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
{
u32 MacAddr;
u8 *Aptr = (u8 *) AddressPtr;
u8 *Aptr = (u8 *)(void *)AddressPtr;
u8 IndexLoc = Index;
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(AddressPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((Index <= XEMACPS_MAX_MAC_ADDR) && (Index > 0));
Xil_AssertNonvoid(Aptr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
/* Be sure device has been stopped */
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
return (XST_DEVICE_IS_STARTED);
if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
Status = (LONG)(XST_DEVICE_IS_STARTED);
}
else{
/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
Index--;
IndexLoc--;
/* Set the MAC bits [31:0] in BOT */
MacAddr = Aptr[0];
MacAddr |= Aptr[1] << 8;
MacAddr |= Aptr[2] << 16;
MacAddr |= Aptr[3] << 24;
MacAddr = *(Aptr);
MacAddr |= ((u32)(*(Aptr+1)) << 8U);
MacAddr |= ((u32)(*(Aptr+2)) << 16U);
MacAddr |= ((u32)(*(Aptr+3)) << 24U);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
(XEMACPS_LADDR1L_OFFSET + Index * 8), MacAddr);
((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
/* There are reserved bits in TOP so don't affect them */
MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
(XEMACPS_LADDR1H_OFFSET + (Index * 8)));
((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
MacAddr &= ~XEMACPS_LADDR_MACH_MASK;
MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
/* Set MAC bits [47:32] in TOP */
MacAddr |= Aptr[4];
MacAddr |= Aptr[5] << 8;
MacAddr |= (u32)(*(Aptr+4));
MacAddr |= (u32)(*(Aptr+5)) << 8U;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
(XEMACPS_LADDR1H_OFFSET + (Index * 8)), MacAddr);
((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
return Status;
}
@ -139,28 +143,28 @@ int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
{
u32 MacAddr;
u8 *Aptr = (u8 *) AddressPtr;
u8 *Aptr = (u8 *)(void *)AddressPtr;
u8 IndexLoc = Index;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(AddressPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Index <= XEMACPS_MAX_MAC_ADDR) && (Index > 0));
Xil_AssertVoid(Aptr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
Index--;
IndexLoc--;
MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
(XEMACPS_LADDR1L_OFFSET + (Index * 8)));
Aptr[0] = (u8) MacAddr;
Aptr[1] = (u8) (MacAddr >> 8);
Aptr[2] = (u8) (MacAddr >> 16);
Aptr[3] = (u8) (MacAddr >> 24);
((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
*Aptr = (u8) MacAddr;
*(Aptr+1) = (u8) (MacAddr >> 8U);
*(Aptr+2) = (u8) (MacAddr >> 16U);
*(Aptr+3) = (u8) (MacAddr >> 24U);
/* Read MAC bits [47:32] in TOP */
MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
(XEMACPS_LADDR1H_OFFSET + (Index * 8)));
Aptr[4] = (u8) MacAddr;
Aptr[5] = (u8) (MacAddr >> 8);
((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
*(Aptr+4) = (u8) MacAddr;
*(Aptr+5) = (u8) (MacAddr >> 8U);
}
@ -222,51 +226,56 @@ void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
* Having Aptr be unsigned type prevents the following operations from sign
* extending.
*****************************************************************************/
int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
{
u32 HashAddr;
u8 *Aptr = (u8 *) AddressPtr;
u8 *Aptr = (u8 *)(void *)AddressPtr;
u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
int Result;
u32 Result;
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(AddressPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Be sure device has been stopped */
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
return (XST_DEVICE_IS_STARTED);
}
Temp1 = Aptr[0] & 0x3F;
Temp2 = ((Aptr[0] >> 6) & 0x3) | ((Aptr[1] & 0xF) << 2);
Temp3 = ((Aptr[1] >> 4) & 0xF) | ((Aptr[2] & 0x3) << 4);
Temp4 = ((Aptr[2] >> 2) & 0x3F);
Temp5 = Aptr[3] & 0x3F;
Temp6 = ((Aptr[3] >> 6) & 0x3) | ((Aptr[4] & 0xF) << 2);
Temp7 = ((Aptr[4] >> 4) & 0xF) | ((Aptr[5] & 0x3) << 4);
Temp8 = ((Aptr[5] >> 2) & 0x3F);
if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
Status = (LONG)(XST_DEVICE_IS_STARTED);
} else {
Temp1 = (*(Aptr+0)) & 0x3FU;
Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
Result = Temp1 ^ Temp2 ^ Temp3 ^ Temp4 ^ Temp5 ^ Temp6 ^ Temp7 ^ Temp8;
Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
Temp5 = (*(Aptr+3)) & 0x3FU;
Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
if (Result >= XEMACPS_MAX_HASH_BITS) {
return (XST_INVALID_PARAM);
}
Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
if (Result < 32) {
if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
Status = (LONG)(XST_INVALID_PARAM);
} else {
if (Result < (u32)32) {
HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHL_OFFSET);
HashAddr |= (1 << Result);
HashAddr |= (u32)(0x00000001U << Result);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHL_OFFSET, HashAddr);
} else {
HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHH_OFFSET);
HashAddr |= (1 << (Result - 32));
HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHH_OFFSET, HashAddr);
}
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
}
return Status;
}
/*****************************************************************************/
@ -287,54 +296,55 @@ int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
* Having Aptr be unsigned type prevents the following operations from sign
* extending.
*****************************************************************************/
int XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
{
u32 HashAddr;
u8 *Aptr = (u8 *) AddressPtr;
u8 *Aptr = (u8 *)(void *)AddressPtr;
u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
int Result;
u32 Result;
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(AddressPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Aptr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Be sure device has been stopped */
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
return (XST_DEVICE_IS_STARTED);
}
Temp1 = Aptr[0] & 0x3F;
Temp2 = ((Aptr[0] >> 6) & 0x3) | ((Aptr[1] & 0xF) << 2);
Temp3 = ((Aptr[1] >> 4) & 0xF) | ((Aptr[2] & 0x3) << 4);
Temp4 = ((Aptr[2] >> 2) & 0x3F);
Temp5 = Aptr[3] & 0x3F;
Temp6 = ((Aptr[3] >> 6) & 0x3) | ((Aptr[4] & 0xF) << 2);
Temp7 = ((Aptr[4] >> 4) & 0xF) | ((Aptr[5] & 0x3) << 4);
Temp8 = ((Aptr[5] >> 2) & 0x3F);
if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
Status = (LONG)(XST_DEVICE_IS_STARTED);
} else {
Temp1 = (*(Aptr+0)) & 0x3FU;
Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
Temp5 = (*(Aptr+3)) & 0x3FU;
Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
Result = Temp1 ^ Temp2 ^ Temp3 ^ Temp4 ^ Temp5 ^ Temp6 ^ Temp7 ^ Temp8;
Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
if (Result >= XEMACPS_MAX_HASH_BITS) {
return (XST_INVALID_PARAM);
}
if (Result < 32) {
if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
Status = (LONG)(XST_INVALID_PARAM);
} else {
if (Result < (u32)32) {
HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHL_OFFSET);
HashAddr &= (~(1 << Result));
HashAddr &= (u32)(~(0x00000001U << Result));
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHL_OFFSET, HashAddr);
} else {
HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHH_OFFSET);
HashAddr &= (~(1 << (Result - 32)));
HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHH_OFFSET, HashAddr);
}
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
}
return Status;
}
/*****************************************************************************/
/**
* Clear the Hash registers for the mac address pointed by AddressPtr.
@ -345,14 +355,14 @@ int XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
void XEmacPs_ClearHash(XEmacPs *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHL_OFFSET, 0x0);
XEMACPS_HASHL_OFFSET, 0x0U);
/* write bits [63:32] in TOP */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHH_OFFSET, 0x0);
XEMACPS_HASHH_OFFSET, 0x0U);
}
@ -367,17 +377,17 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr)
*****************************************************************************/
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
{
u32 *Aptr = (u32 *) AddressPtr;
u32 *Aptr = (u32 *)(void *)AddressPtr;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(AddressPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Aptr[0] = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
*(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHL_OFFSET);
/* Read Hash bits [63:32] in TOP */
Aptr[1] = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
*(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_HASHH_OFFSET);
}
@ -396,25 +406,29 @@ void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
* - XST_DEVICE_IS_STARTED if the device has not yet been stopped
*
*****************************************************************************/
int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
{
u8 IndexLoc = Index;
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((Index <= XEMACPS_MAX_TYPE_ID) && (Index > 0));
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
/* Be sure device has been stopped */
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
return (XST_DEVICE_IS_STARTED);
}
if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
Status = (LONG)(XST_DEVICE_IS_STARTED);
} else {
/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
Index--;
IndexLoc--;
/* Set the ID bits in MATCHx register */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
(XEMACPS_MATCH1_OFFSET + (Index * 4)), Id_Check);
((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
return Status;
}
/*****************************************************************************/
@ -435,19 +449,19 @@ int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
* See xemacps.h for a description of the available options.
*
*****************************************************************************/
int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
{
u32 Reg; /* Generic register contents */
u32 RegNetCfg; /* Reflects original contents of NET_CONFIG */
u32 RegNewNetCfg; /* Reflects new contents of NET_CONFIG */
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Be sure device has been stopped */
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
return (XST_DEVICE_IS_STARTED);
}
if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
Status = (LONG)(XST_DEVICE_IS_STARTED);
} else {
/* Many of these options will change the NET_CONFIG registers.
* To reduce the amount of IO to the device, group these options here
@ -462,47 +476,47 @@ int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
/*
* It is configured to max 1536.
*/
if (Options & XEMACPS_FRAME1536_OPTION) {
if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
}
/* Turn on VLAN packet only, only VLAN tagged will be accepted */
if (Options & XEMACPS_VLAN_OPTION) {
if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
}
/* Turn on FCS stripping on receive packets */
if (Options & XEMACPS_FCS_STRIP_OPTION) {
if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
}
/* Turn on length/type field checking on receive packets */
if (Options & XEMACPS_LENTYPE_ERR_OPTION) {
RegNewNetCfg |= XEMACPS_NWCFG_LENGTHERRDSCRD_MASK;
if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
}
/* Turn on flow control */
if (Options & XEMACPS_FLOW_CONTROL_OPTION) {
if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
}
/* Turn on promiscuous frame filtering (all frames are received) */
if (Options & XEMACPS_PROMISC_OPTION) {
if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
}
/* Allow broadcast address reception */
if (Options & XEMACPS_BROADCAST_OPTION) {
RegNewNetCfg &= ~XEMACPS_NWCFG_BCASTDI_MASK;
if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
}
/* Allow multicast address filtering */
if (Options & XEMACPS_MULTICAST_OPTION) {
if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
}
/* enable RX checksum offload */
if (Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) {
if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
}
@ -515,7 +529,7 @@ int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
}
/* Enable TX checksum offload */
if (Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) {
if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
@ -524,7 +538,7 @@ int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
}
/* Enable transmitter */
if (Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) {
if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg |= XEMACPS_NWCTRL_TXEN_MASK;
@ -533,7 +547,7 @@ int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
}
/* Enable receiver */
if (Options & XEMACPS_RECEIVER_ENABLE_OPTION) {
if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg |= XEMACPS_NWCTRL_RXEN_MASK;
@ -549,7 +563,9 @@ int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
/* Set options word to its new value */
InstancePtr->Options |= Options;
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
return Status;
}
@ -570,19 +586,19 @@ int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
* See xemacps.h for a description of the available options.
*
*****************************************************************************/
int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
{
u32 Reg; /* Generic */
u32 RegNetCfg; /* Reflects original contents of NET_CONFIG */
u32 RegNewNetCfg; /* Reflects new contents of NET_CONFIG */
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Be sure device has been stopped */
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
return (XST_DEVICE_IS_STARTED);
}
if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
Status = (LONG)(XST_DEVICE_IS_STARTED);
} else {
/* Many of these options will change the NET_CONFIG registers.
* To reduce the amount of IO to the device, group these options here
@ -597,48 +613,48 @@ int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
/* There is only RX configuration!?
* It is configured in two different length, upto 1536 and 10240 bytes
*/
if (Options & XEMACPS_FRAME1536_OPTION) {
RegNewNetCfg &= ~XEMACPS_NWCFG_1536RXEN_MASK;
if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
}
/* Turn off VLAN packet only */
if (Options & XEMACPS_VLAN_OPTION) {
RegNewNetCfg &= ~XEMACPS_NWCFG_NVLANDISC_MASK;
if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
}
/* Turn off FCS stripping on receive packets */
if (Options & XEMACPS_FCS_STRIP_OPTION) {
RegNewNetCfg &= ~XEMACPS_NWCFG_FCSREM_MASK;
if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
}
/* Turn off length/type field checking on receive packets */
if (Options & XEMACPS_LENTYPE_ERR_OPTION) {
RegNewNetCfg &= ~XEMACPS_NWCFG_LENGTHERRDSCRD_MASK;
if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
}
/* Turn off flow control */
if (Options & XEMACPS_FLOW_CONTROL_OPTION) {
RegNewNetCfg &= ~XEMACPS_NWCFG_PAUSEEN_MASK;
if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
}
/* Turn off promiscuous frame filtering (all frames are received) */
if (Options & XEMACPS_PROMISC_OPTION) {
RegNewNetCfg &= ~XEMACPS_NWCFG_COPYALLEN_MASK;
if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
}
/* Disallow broadcast address filtering => broadcast reception */
if (Options & XEMACPS_BROADCAST_OPTION) {
if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
}
/* Disallow multicast address filtering */
if (Options & XEMACPS_MULTICAST_OPTION) {
RegNewNetCfg &= ~XEMACPS_NWCFG_MCASTHASHEN_MASK;
if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
}
/* Disable RX checksum offload */
if (Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) {
RegNewNetCfg &= ~XEMACPS_NWCFG_RXCHKSUMEN_MASK;
if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
}
/* Officially change the NET_CONFIG registers if it needs to be
@ -650,28 +666,28 @@ int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
}
/* Disable TX checksum offload */
if (Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) {
if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg &= ~XEMACPS_DMACR_TCPCKSUM_MASK;
Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET, Reg);
}
/* Disable transmitter */
if (Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) {
if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg &= ~XEMACPS_NWCTRL_TXEN_MASK;
Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
}
/* Disable receiver */
if (Options & XEMACPS_RECEIVER_ENABLE_OPTION) {
if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg &= ~XEMACPS_NWCTRL_RXEN_MASK;
Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
}
@ -684,7 +700,9 @@ int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
/* Set options word to its new value */
InstancePtr->Options &= ~Options;
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
return Status;
}
@ -705,7 +723,7 @@ int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
return (InstancePtr->Options);
}
@ -722,25 +740,27 @@ u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
* - XST_DEVICE_IS_STOPPED if the device has not been started.
*
*****************************************************************************/
int XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
{
u32 Reg;
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* Make sure device is ready for this operation */
if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
return (XST_DEVICE_IS_STOPPED);
}
if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
Status = (LONG)(XST_DEVICE_IS_STOPPED);
} else {
/* Send flow control frame */
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
return Status;
}
/*****************************************************************************/
@ -759,22 +779,24 @@ int XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
{
u32 Reg;
u16 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET);
if (Reg & XEMACPS_NWCFG_1000_MASK) {
return (1000);
if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
Status = (u16)(1000);
} else {
if (Reg & XEMACPS_NWCFG_100_MASK) {
return (100);
if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
Status = (u16)(100);
} else {
return (10);
Status = (u16)(10);
}
}
return Status;
}
@ -794,28 +816,35 @@ u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
{
u32 Reg;
u16 Status;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Speed == 10) || (Speed == 100) || (Speed == 1000));
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET);
Reg &= ~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK);
Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
switch (Speed) {
case 10:
case (u16)10:
Status = 0U;
break;
case 100:
case (u16)100:
Status = 0U;
Reg |= XEMACPS_NWCFG_100_MASK;
break;
case 1000:
case (u16)1000:
Status = 0U;
Reg |= XEMACPS_NWCFG_1000_MASK;
break;
default:
Status = 1U;
break;
}
if(Status == (u16)1){
return;
}
@ -860,21 +889,19 @@ void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
{
u32 Reg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Divisor <= 0x7); /* only last three bits are valid */
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET);
/* clear these three bits, could be done with mask */
Reg &= ~XEMACPS_NWCFG_MDCCLKDIV_MASK;
Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
Reg |= (Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET, Reg);
}
@ -915,25 +942,27 @@ void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
* blocked to the current XEmacPs instance.
*
******************************************************************************/
int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 *PhyDataPtr)
{
u32 Mgtcr;
volatile u32 Ipisr;
u32 IpReadTemp;
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
/* Make sure no other PHY operation is currently in progress */
if (!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWSR_OFFSET) &
XEMACPS_NWSR_MDIOIDLE_MASK)) {
return (XST_EMAC_MII_BUSY);
}
XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
Status = (LONG)(XST_EMAC_MII_BUSY);
} else {
/* Construct Mgtcr mask for the operation */
Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
(PhyAddress << XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK) |
(RegisterNum << XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK);
(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
/* Write Mgtcr and wait for completion */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
@ -942,13 +971,15 @@ int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
do {
Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWSR_OFFSET);
} while ((Ipisr & XEMACPS_NWSR_MDIOIDLE_MASK) == 0);
IpReadTemp = Ipisr;
} while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
/* Read data */
*PhyDataPtr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
*PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_PHYMNTNC_OFFSET);
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
return Status;
}
@ -992,25 +1023,26 @@ int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
* blocked to the current XEmacPs instance.
*
******************************************************************************/
int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 PhyData)
{
u32 Mgtcr;
volatile u32 Ipisr;
u32 IpWriteTemp;
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
/* Make sure no other PHY operation is currently in progress */
if (!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWSR_OFFSET) &
XEMACPS_NWSR_MDIOIDLE_MASK)) {
return (XST_EMAC_MII_BUSY);
}
XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
Status = (LONG)(XST_EMAC_MII_BUSY);
} else {
/* Construct Mgtcr mask for the operation */
Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
(PhyAddress << XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK) |
(RegisterNum << XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK) | PhyData;
(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
/* Write Mgtcr and wait for completion */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
@ -1019,9 +1051,12 @@ int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
do {
Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWSR_OFFSET);
} while ((Ipisr & XEMACPS_NWSR_MDIOIDLE_MASK) == 0);
IpWriteTemp = Ipisr;
} while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
return (XST_SUCCESS);
Status = (LONG)(XST_SUCCESS);
}
return Status;
}
/*****************************************************************************/
@ -1034,10 +1069,10 @@ int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
* @return None
*
******************************************************************************/
void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength)
void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
{
u32 Reg;
u32 RegUpdateVal = 0;
u32 RegUpdateVal;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
@ -1063,13 +1098,14 @@ void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength)
break;
default:
RegUpdateVal = 0x00000000U;
break;
}
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg &= (~XEMACPS_DMACR_BLENGTH_MASK);
Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
Reg |= RegUpdateVal;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
Reg);
}
}

10
XilinxProcessorIPLib/drivers/emacps/src/xemacps_g.c
View file

@ -58,8 +58,8 @@
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xemacps.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
@ -78,13 +78,13 @@
XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] = {
{
XPAR_XEMACPS_0_DEVICE_ID, /* Device ID */
XPAR_XEMACPS_0_BASEADDR /* Device base address */
(u16)XPAR_XEMACPS_0_DEVICE_ID, /* Device ID */
(UINTPTR)XPAR_XEMACPS_0_BASEADDR /* Device base address */
},
#ifdef XPAR_XEMACPS_1_DEVICE_ID
{
XPAR_XEMACPS_1_DEVICE_ID, /* Device ID */
XPAR_XEMACPS_1_BASEADDR /* Device base address */
(u16)XPAR_XEMACPS_1_DEVICE_ID, /* Device ID */
(UINTPTR)XPAR_XEMACPS_1_BASEADDR /* Device base address */
}
#endif
};

28
XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.c
View file

@ -48,8 +48,8 @@
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xemacps_hw.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
@ -83,17 +83,17 @@
******************************************************************************/
void XEmacPs_ResetHw(u32 BaseAddr)
{
u32 RegVal = 0;
u32 RegVal;
/* Disable the interrupts */
XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0);
XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
/* Stop transmission,disable loopback and Stop tx and Rx engines */
RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
RegVal &= ~(XEMACPS_NWCTRL_TXEN_MASK|
XEMACPS_NWCTRL_RXEN_MASK|
XEMACPS_NWCTRL_HALTTX_MASK|
XEMACPS_NWCTRL_LOOPEN_MASK);
RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
(u32)XEMACPS_NWCTRL_RXEN_MASK|
(u32)XEMACPS_NWCTRL_HALTTX_MASK|
(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
/* Clear the statistic registers, flush the packets in DPRAM*/
RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
@ -101,19 +101,19 @@ void XEmacPs_ResetHw(u32 BaseAddr)
/* Clear the interrupt status */
XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
/* Clear the tx status */
XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,XEMACPS_TXSR_ERROR_MASK|
XEMACPS_TXSR_TXCOMPL_MASK|
XEMACPS_TXSR_TXGO_MASK);
XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
(u32)XEMACPS_TXSR_TXCOMPL_MASK|
(u32)XEMACPS_TXSR_TXGO_MASK));
/* Clear the rx status */
XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
XEMACPS_RXSR_FRAMERX_MASK);
/* Clear the tx base address */
XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0);
XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
/* Clear the rx base address */
XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0);
XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
/* Update the network config register with reset value */
XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
/* Update the hash address registers with reset value */
XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0);
XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0);
XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
}

514
XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
View file

@ -50,6 +50,7 @@
* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
* </pre>
*
******************************************************************************/
@ -69,12 +70,13 @@ extern "C" {
/************************** Constant Definitions *****************************/
#define XEMACPS_MAX_MAC_ADDR 4 /**< Maxmum number of mac address
#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
supported */
#define XEMACPS_MAX_TYPE_ID 4 /**< Maxmum number of type id supported */
#define XEMACPS_BD_ALIGNMENT 4 /**< Minimum buffer descriptor alignment
#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
on the local bus */
#define XEMACPS_RX_BUF_ALIGNMENT 4 /**< Minimum buffer alignment when using
#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
options that impose alignment
restrictions on the buffer data on
the local bus */
@ -85,275 +87,289 @@ extern "C" {
* to specify whether an operation specifies a send or receive channel.
* @{
*/
#define XEMACPS_SEND 1 /**< send direction */
#define XEMACPS_RECV 2 /**< receive direction */
#define XEMACPS_SEND 1U /**< send direction */
#define XEMACPS_RECV 2U /**< receive direction */
/*@}*/
/** @name MDC clock division
* currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
* @{
*/
typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
} XEmacPs_MdcDiv;
/*@}*/
#define XEMACPS_RX_BUF_SIZE 1536 /**< Specify the receive buffer size in
#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
bytes, 64, 128, ... 10240 */
#define XEMACPS_RX_BUF_UNIT 64 /**< Number of receive buffer bytes as a
#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
unit, this is HW setup */
#define XEMACPS_MAX_RXBD 128 /**< Size of RX buffer descriptor queues */
#define XEMACPS_MAX_TXBD 128 /**< Size of TX buffer descriptor queues */
#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
#define XEMACPS_MAX_HASH_BITS 64 /**< Maximum value for hash bits. 2**6 */
#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
/* Register offset definitions. Unless otherwise noted, register access is
* 32 bit. Names are self explained here.
*/
#define XEMACPS_NWCTRL_OFFSET 0x00000000 /**< Network Control reg */
#define XEMACPS_NWCFG_OFFSET 0x00000004 /**< Network Config reg */
#define XEMACPS_NWSR_OFFSET 0x00000008 /**< Network Status reg */
#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
#define XEMACPS_DMACR_OFFSET 0x00000010 /**< DMA Control reg */
#define XEMACPS_TXSR_OFFSET 0x00000014 /**< TX Status reg */
#define XEMACPS_RXQBASE_OFFSET 0x00000018 /**< RX Q Base address reg */
#define XEMACPS_TXQBASE_OFFSET 0x0000001C /**< TX Q Base address reg */
#define XEMACPS_RXSR_OFFSET 0x00000020 /**< RX Status reg */
#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
#define XEMACPS_ISR_OFFSET 0x00000024 /**< Interrupt Status reg */
#define XEMACPS_IER_OFFSET 0x00000028 /**< Interrupt Enable reg */
#define XEMACPS_IDR_OFFSET 0x0000002C /**< Interrupt Disable reg */
#define XEMACPS_IMR_OFFSET 0x00000030 /**< Interrupt Mask reg */
#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
#define XEMACPS_PHYMNTNC_OFFSET 0x00000034 /**< Phy Maintaince reg */
#define XEMACPS_RXPAUSE_OFFSET 0x00000038 /**< RX Pause Time reg */
#define XEMACPS_TXPAUSE_OFFSET 0x0000003C /**< TX Pause Time reg */
#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
#define XEMACPS_HASHL_OFFSET 0x00000080 /**< Hash Low address reg */
#define XEMACPS_HASHH_OFFSET 0x00000084 /**< Hash High address reg */
#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
#define XEMACPS_LADDR1L_OFFSET 0x00000088 /**< Specific1 addr low reg */
#define XEMACPS_LADDR1H_OFFSET 0x0000008C /**< Specific1 addr high reg */
#define XEMACPS_LADDR2L_OFFSET 0x00000090 /**< Specific2 addr low reg */
#define XEMACPS_LADDR2H_OFFSET 0x00000094 /**< Specific2 addr high reg */
#define XEMACPS_LADDR3L_OFFSET 0x00000098 /**< Specific3 addr low reg */
#define XEMACPS_LADDR3H_OFFSET 0x0000009C /**< Specific3 addr high reg */
#define XEMACPS_LADDR4L_OFFSET 0x000000A0 /**< Specific4 addr low reg */
#define XEMACPS_LADDR4H_OFFSET 0x000000A4 /**< Specific4 addr high reg */
#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
#define XEMACPS_MATCH1_OFFSET 0x000000A8 /**< Type ID1 Match reg */
#define XEMACPS_MATCH2_OFFSET 0x000000AC /**< Type ID2 Match reg */
#define XEMACPS_MATCH3_OFFSET 0x000000B0 /**< Type ID3 Match reg */
#define XEMACPS_MATCH4_OFFSET 0x000000B4 /**< Type ID4 Match reg */
#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
#define XEMACPS_STRETCH_OFFSET 0x000000BC /**< IPG Stretch reg */
#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
#define XEMACPS_OCTTXL_OFFSET 0x00000100 /**< Octects transmitted Low
#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
reg */
#define XEMACPS_OCTTXH_OFFSET 0x00000104 /**< Octects transmitted High
#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
reg */
#define XEMACPS_TXCNT_OFFSET 0x00000108 /**< Error-free Frmaes
#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
transmitted counter */
#define XEMACPS_TXBCCNT_OFFSET 0x0000010C /**< Error-free Broadcast
#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
Frames counter*/
#define XEMACPS_TXMCCNT_OFFSET 0x00000110 /**< Error-free Multicast
#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
Frame counter */
#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114 /**< Pause Frames Transmitted
#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
Counter */
#define XEMACPS_TX64CNT_OFFSET 0x00000118 /**< Error-free 64 byte Frames
#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
Transmitted counter */
#define XEMACPS_TX65CNT_OFFSET 0x0000011C /**< Error-free 65-127 byte
#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
Frames Transmitted
counter */
#define XEMACPS_TX128CNT_OFFSET 0x00000120 /**< Error-free 128-255 byte
#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
Frames Transmitted
counter*/
#define XEMACPS_TX256CNT_OFFSET 0x00000124 /**< Error-free 256-511 byte
#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
Frames transmitted
counter */
#define XEMACPS_TX512CNT_OFFSET 0x00000128 /**< Error-free 512-1023 byte
#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
Frames transmitted
counter */
#define XEMACPS_TX1024CNT_OFFSET 0x0000012C /**< Error-free 1024-1518 byte
#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
Frames transmitted
counter */
#define XEMACPS_TX1519CNT_OFFSET 0x00000130 /**< Error-free larger than
#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
1519 byte Frames
transmitted counter */
#define XEMACPS_TXURUNCNT_OFFSET 0x00000134 /**< TX under run error
#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
counter */
#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138 /**< Single Collision Frame
#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
Counter */
#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013C /**< Multiple Collision Frame
#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
Counter */
#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140 /**< Excessive Collision Frame
#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
Counter */
#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144 /**< Late Collision Frame
#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
Counter */
#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148 /**< Deferred Transmission
#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
Frame Counter */
#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014C /**< Transmit Carrier Sense
#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
Error Counter */
#define XEMACPS_OCTRXL_OFFSET 0x00000150 /**< Octects Received register
#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
Low */
#define XEMACPS_OCTRXH_OFFSET 0x00000154 /**< Octects Received register
#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
High */
#define XEMACPS_RXCNT_OFFSET 0x00000158 /**< Error-free Frames
#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
Received Counter */
#define XEMACPS_RXBROADCNT_OFFSET 0x0000015C /**< Error-free Broadcast
#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
Frames Received Counter */
#define XEMACPS_RXMULTICNT_OFFSET 0x00000160 /**< Error-free Multicast
#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
Frames Received Counter */
#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164 /**< Pause Frames
#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
Received Counter */
#define XEMACPS_RX64CNT_OFFSET 0x00000168 /**< Error-free 64 byte Frames
#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
Received Counter */
#define XEMACPS_RX65CNT_OFFSET 0x0000016C /**< Error-free 65-127 byte
#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
Frames Received Counter */
#define XEMACPS_RX128CNT_OFFSET 0x00000170 /**< Error-free 128-255 byte
#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
Frames Received Counter */
#define XEMACPS_RX256CNT_OFFSET 0x00000174 /**< Error-free 256-512 byte
#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
Frames Received Counter */
#define XEMACPS_RX512CNT_OFFSET 0x00000178 /**< Error-free 512-1023 byte
#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
Frames Received Counter */
#define XEMACPS_RX1024CNT_OFFSET 0x0000017C /**< Error-free 1024-1518 byte
#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
Frames Received Counter */
#define XEMACPS_RX1519CNT_OFFSET 0x00000180 /**< Error-free 1519-max byte
#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
Frames Received Counter */
#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184 /**< Undersize Frames Received
#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
Counter */
#define XEMACPS_RXOVRCNT_OFFSET 0x00000188 /**< Oversize Frames Received
#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
Counter */
#define XEMACPS_RXJABCNT_OFFSET 0x0000018C /**< Jabbers Received
#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
Counter */
#define XEMACPS_RXFCSCNT_OFFSET 0x00000190 /**< Frame Check Sequence
#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
Error Counter */
#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194 /**< Length Field Error
#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
Counter */
#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198 /**< Symbol Error Counter */
#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019C /**< Alignment Error Counter */
#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0 /**< Receive Resource Error
#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
Counter */
#define XEMACPS_RXORCNT_OFFSET 0x000001A4 /**< Receive Overrun Counter */
#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8 /**< IP header Checksum Error
#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
Counter */
#define XEMACPS_RXTCPCCNT_OFFSET 0x000001AC /**< TCP Checksum Error
#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
Counter */
#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0 /**< UDP Checksum Error
#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
Counter */
#define XEMACPS_LAST_OFFSET 0x000001B4 /**< Last statistic counter
#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
offset, for clearing */
#define XEMACPS_1588_SEC_OFFSET 0x000001D0 /**< 1588 second counter */
#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4 /**< 1588 nanosecond counter */
#define XEMACPS_1588_ADJ_OFFSET 0x000001D8 /**< 1588 nanosecond
#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
adjustment counter */
#define XEMACPS_1588_INC_OFFSET 0x000001DC /**< 1588 nanosecond
#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
increment counter */
#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0 /**< 1588 PTP transmit second
#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
counter */
#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4 /**< 1588 PTP transmit
#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
nanosecond counter */
#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8 /**< 1588 PTP receive second
#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
counter */
#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001EC /**< 1588 PTP receive
#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
nanosecond counter */
#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0 /**< 1588 PTP peer transmit
#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
second counter */
#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4 /**< 1588 PTP peer transmit
#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
nanosecond counter */
#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8 /**< 1588 PTP peer receive
#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
second counter */
#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FC /**< 1588 PTP peer receive
#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
nanosecond counter */
#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
reg */
#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
reg */
#define XEMACPS_MSBBUF_QBASE_OFFSET 0x000004C8U /**< MSB Buffer Q Base
reg */
#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
reg */
#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
reg */
#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
reg */
/* Define some bit positions for registers. */
/** @name network control register bit definitions
* @{
*/
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000 /**< Flush a packet from
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
Rx SRAM */
#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800 /**< Transmit zero quantum
#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
pause frame */
#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800 /**< Transmit pause frame */
#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400 /**< Halt transmission
#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
after current frame */
#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200 /**< Start tx (tx_go) */
#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080 /**< Enable writing to
#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
stat counters */
#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040 /**< Increment statistic
#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
registers */
#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020 /**< Clear statistic
#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
registers */
#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010 /**< Enable MDIO port */
#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008 /**< Enable transmit */
#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004 /**< Enable receive */
#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002 /**< local loopback */
#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
/*@}*/
/** @name network configuration register bit definitions
* @{
*/
#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000 /**< disable rejection of
#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
non-standard preamble */
#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000 /**< enable transmit IPG */
#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000 /**< disable rejection of
#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
FCS error */
#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000 /**< RX half duplex */
#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000 /**< enable RX checksum
#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
offload */
#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000 /**< Do not copy pause
#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
Frames to memory */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18 /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000 /**< MDC Mask PCLK divisor */
#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000 /**< Discard FCS from
#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
received frames */
#define XEMACPS_NWCFG_LENGTHERRDSCRD_MASK 0x00010000
#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
/**< RX length error discard */
#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000 /**< RX buffer offset */
#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000 /**< Enable pause RX */
#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000 /**< Retry test */
#define XEMACPS_NWCFG_EXTADDRMATCHEN_MASK 0x00000200
#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
/**< External address match enable */
#define XEMACPS_NWCFG_1000_MASK 0x00000400 /**< 1000 Mbps */
#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100 /**< Enable 1536 byte
#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
frames reception */
#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080 /**< Receive unicast hash
#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
frames */
#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040 /**< Receive multicast hash
#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
frames */
#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020 /**< Do not receive
#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
broadcast frames */
#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010 /**< Copy all frames */
#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008 /**< Jumbo frames */
#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004 /**< Receive only VLAN
#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
frames */
#define XEMACPS_NWCFG_FDEN_MASK 0x00000002 /**< full duplex */
#define XEMACPS_NWCFG_100_MASK 0x00000001 /**< 100 Mbps */
#define XEMACPS_NWCFG_RESET_MASK 0x00080000 /**< reset value */
#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
/*@}*/
/** @name network status register bit definitaions
* @{
*/
#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004 /**< PHY management idle */
#define XEMACPS_NWSR_MDIO_MASK 0x00000002 /**< Status of mdio_in */
#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
/*@}*/
/** @name MAC address register word 1 mask
* @{
*/
#define XEMACPS_LADDR_MACH_MASK 0x0000FFFF /**< Address bits[47:32]
#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
bit[31:0] are in BOTTOM */
/*@}*/
@ -361,55 +377,69 @@ typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
/** @name DMA control register bit definitions
* @{
*/
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000 /**< Mask bit for RX buffer
#define XEMACPS_DMACR_TXEXTEND_MASK 0x02000000U /**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK 0x01000000U /**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT 16 /**< Shift bit for RX buffer
#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800 /**< enable/disable TX
#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400 /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300 /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080 /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001F /**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001 /**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004 /**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008 /**< 8 bytes AHB bursts */
#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010 /**< 16 bytes AHB bursts */
#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
/*@}*/
/** @name transmit status register bit definitions
* @{
*/
#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100 /**< Transmit hresp not OK */
#define XEMACPS_TXSR_URUN_MASK 0x00000040 /**< Transmit underrun */
#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020 /**< Transmit completed OK */
#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010 /**< Transmit buffs exhausted
#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
mid frame */
#define XEMACPS_TXSR_TXGO_MASK 0x00000008 /**< Status of go flag */
#define XEMACPS_TXSR_RXOVR_MASK 0x00000004 /**< Retry limit exceeded */
#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002 /**< Collision tx frame */
#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001 /**< TX buffer used bit set */
#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
#define XEMACPS_TXSR_ERROR_MASK (XEMACPS_TXSR_HRESPNOK_MASK | \
XEMACPS_TXSR_URUN_MASK | \
XEMACPS_TXSR_BUFEXH_MASK | \
XEMACPS_TXSR_RXOVR_MASK | \
XEMACPS_TXSR_FRAMERX_MASK | \
XEMACPS_TXSR_USEDREAD_MASK)
#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
(u32)XEMACPS_TXSR_URUN_MASK | \
(u32)XEMACPS_TXSR_BUFEXH_MASK | \
(u32)XEMACPS_TXSR_RXOVR_MASK | \
(u32)XEMACPS_TXSR_FRAMERX_MASK | \
(u32)XEMACPS_TXSR_USEDREAD_MASK)
/*@}*/
/**
* @name receive status register bit definitions
* @{
*/
#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008 /**< Receive hresp not OK */
#define XEMACPS_RXSR_RXOVR_MASK 0x00000004 /**< Receive overrun */
#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002 /**< Frame received OK */
#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001 /**< RX buffer used bit set */
#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
(u32)XEMACPS_RXSR_RXOVR_MASK | \
(u32)XEMACPS_RXSR_BUFFNA_MASK)
/*@}*/
/**
* @name Interrupt Q1 status register bit definitions
* @{
*/
#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
(u32)XEMACPS_INTQ1SR_TXERR_MASK)
#define XEMACPS_RXSR_ERROR_MASK (XEMACPS_RXSR_HRESPNOK_MASK | \
XEMACPS_RXSR_RXOVR_MASK | \
XEMACPS_RXSR_BUFFNA_MASK)
/*@}*/
/**
@ -418,63 +448,65 @@ typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
* XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
* @{
*/
#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000 /**< PTP Psync transmitted */
#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000 /**< PTP Pdelay_req
#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */
#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req
transmitted */
#define XEMACPS_IXR_PTPSTX_MASK 0x00800000 /**< PTP Sync transmitted */
#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000 /**< PTP Delay_req transmitted
#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */
#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted
*/
#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000 /**< PTP Psync received */
#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000 /**< PTP Pdelay_req received */
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000 /**< PTP Sync received */
#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000 /**< PTP Delay_req received */
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000 /**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000 /**< Pause time has reached
#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */
#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */
#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
zero */
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000 /**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800 /**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK 0x00000400 /**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080 /**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK 0x00000040 /**< Transmit err occurred or
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
no buffers*/
#define XEMACPS_IXR_RETRY_MASK 0x00000020 /**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK 0x00000010 /**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK 0x00000008 /**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK 0x00000004 /**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002 /**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK 0x00000001 /**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK 0x00007FFF /**< Everything! */
#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
#define XEMACPS_IXR_TX_ERR_MASK (XEMACPS_IXR_TXEXH_MASK | \
XEMACPS_IXR_RETRY_MASK | \
XEMACPS_IXR_URUN_MASK | \
XEMACPS_IXR_TXUSED_MASK)
#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
(u32)XEMACPS_IXR_RETRY_MASK | \
(u32)XEMACPS_IXR_URUN_MASK | \
(u32)XEMACPS_IXR_TXUSED_MASK)
#define XEMACPS_IXR_RX_ERR_MASK (XEMACPS_IXR_HRESPNOK_MASK | \
XEMACPS_IXR_RXUSED_MASK | \
XEMACPS_IXR_RXOVR_MASK)
#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
(u32)XEMACPS_IXR_RXUSED_MASK | \
(u32)XEMACPS_IXR_RXOVR_MASK)
/*@}*/
/** @name PHY Maintenance bit definitions
* @{
*/
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000 /**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000 /**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000 /**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000 /**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000 /**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFF /**< data bits */
#define XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK 23 /**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK 18 /**< Shift bits for PHREG */
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
/*@}*/
/* Transmit buffer descriptor status words offset
* @{
*/
#define XEMACPS_BD_ADDR_OFFSET 0x00000000 /**< word 0/addr of BDs */
#define XEMACPS_BD_STAT_OFFSET 0x00000004 /**< word 1/status of BDs */
#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
/*
* @}
*/
@ -488,15 +520,15 @@ typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
* information, whether the frame was transmitted OK or why it had failed.
* @{
*/
#define XEMACPS_TXBUF_USED_MASK 0x80000000 /**< Used bit. */
#define XEMACPS_TXBUF_WRAP_MASK 0x40000000 /**< Wrap bit, last descriptor */
#define XEMACPS_TXBUF_RETRY_MASK 0x20000000 /**< Retry limit exceeded */
#define XEMACPS_TXBUF_URUN_MASK 0x10000000 /**< Transmit underrun occurred */
#define XEMACPS_TXBUF_EXH_MASK 0x08000000 /**< Buffers exhausted */
#define XEMACPS_TXBUF_TCP_MASK 0x04000000 /**< Late collision. */
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000 /**< No CRC */
#define XEMACPS_TXBUF_LAST_MASK 0x00008000 /**< Last buffer */
#define XEMACPS_TXBUF_LEN_MASK 0x00003FFF /**< Mask for length field */
#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
/*
* @}
*/
@ -512,32 +544,32 @@ typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
* useful info.
* @{
*/
#define XEMACPS_RXBUF_BCAST_MASK 0x80000000 /**< Broadcast frame */
#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000 /**< Multicast hashed frame */
#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000 /**< Unicast hashed frame */
#define XEMACPS_RXBUF_EXH_MASK 0x08000000 /**< buffer exhausted */
#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000 /**< Specific address
#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
matched */
#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000 /**< Type ID matched */
#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000 /**< ID matched mask */
#define XEMACPS_RXBUF_VLAN_MASK 0x00200000 /**< VLAN tagged */
#define XEMACPS_RXBUF_PRI_MASK 0x00100000 /**< Priority tagged */
#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000 /**< Vlan priority */
#define XEMACPS_RXBUF_CFI_MASK 0x00010000 /**< CFI frame */
#define XEMACPS_RXBUF_EOF_MASK 0x00008000 /**< End of frame. */
#define XEMACPS_RXBUF_SOF_MASK 0x00004000 /**< Start of frame. */
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFF /**< Mask for length field */
#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002 /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK 0x00000001 /**< Used bit.. */
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFC /**< Mask for address */
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
/*
* @}
*/
/*
* Define appropriate I/O access method to mempry mapped I/O or other
* intarfce if necessary.
* Define appropriate I/O access method to memory mapped I/O or other
* interface if necessary.
*/
#define XEmacPs_In32 Xil_In32
@ -560,7 +592,7 @@ typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
*
*****************************************************************************/
#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
XEmacPs_In32((BaseAddress) + (RegOffset))
XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
/****************************************************************************/
@ -581,7 +613,7 @@ typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
*
*****************************************************************************/
#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
XEmacPs_Out32((BaseAddress) + (RegOffset), (Data))
XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes *****************************/
/*

84
XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c
View file

@ -53,6 +53,8 @@
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
* and 64-bit changes.
* </pre>
******************************************************************************/
@ -83,7 +85,7 @@
* @param HandlerType indicates what interrupt handler type is.
* XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
* XEMACPS_HANDLER_ERROR.
* @param FuncPtr is the pointer to the callback function
* @param FuncPointer is the pointer to the callback function
* @param CallBackRef is the upper layer callback reference passed back when
* when the callback function is invoked.
*
@ -96,30 +98,35 @@
* it is.
*
*****************************************************************************/
int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPtr, void *CallBackRef)
LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPointer, void *CallBackRef)
{
LONG Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(FuncPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(FuncPointer != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
switch (HandlerType) {
case XEMACPS_HANDLER_DMASEND:
InstancePtr->SendHandler = (XEmacPs_Handler) FuncPtr;
Status = (LONG)(XST_SUCCESS);
InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
InstancePtr->SendRef = CallBackRef;
break;
case XEMACPS_HANDLER_DMARECV:
InstancePtr->RecvHandler = (XEmacPs_Handler) FuncPtr;
Status = (LONG)(XST_SUCCESS);
InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
InstancePtr->RecvRef = CallBackRef;
break;
case XEMACPS_HANDLER_ERROR:
InstancePtr->ErrorHandler = (XEmacPs_ErrHandler) FuncPtr;
Status = (LONG)(XST_SUCCESS);
InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
InstancePtr->ErrorRef = CallBackRef;
break;
default:
return (XST_INVALID_PARAM);
Status = (LONG)(XST_INVALID_PARAM);
break;
}
return (XST_SUCCESS);
return Status;
}
/*****************************************************************************/
@ -139,10 +146,11 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
u32 RegISR;
u32 RegSR;
u32 RegCtrl;
u32 RegQ1ISR;
XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/* This ISR will try to handle as many interrupts as it can in a single
* call. However, in most of the places where the user's error handler
@ -152,34 +160,55 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_ISR_OFFSET);
/* Read Transmit Q1 ISR */
if (InstancePtr->Version == 7)
RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET);
/* Clear the interrupt status register */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
RegISR);
/* Receive complete interrupt */
if (RegISR & (XEMACPS_IXR_FRAMERX_MASK)) {
if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
/* Clear RX status register RX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET,
XEMACPS_RXSR_FRAMERX_MASK |
XEMACPS_RXSR_BUFFNA_MASK);
((u32)XEMACPS_RXSR_FRAMERX_MASK |
(u32)XEMACPS_RXSR_BUFFNA_MASK));
InstancePtr->RecvHandler(InstancePtr->RecvRef);
}
/* Transmit Q1 complete interrupt */
if ((InstancePtr->Version == 7) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
/* Clear TX status register TX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET,
XEMACPS_INTQ1SR_TXCOMPL_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET,
((u32)XEMACPS_TXSR_TXCOMPL_MASK |
(u32)XEMACPS_TXSR_USEDREAD_MASK));
InstancePtr->SendHandler(InstancePtr->SendRef);
}
/* Transmit complete interrupt */
if (RegISR & (XEMACPS_IXR_TXCOMPL_MASK)) {
if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
/* Clear TX status register TX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET,
XEMACPS_TXSR_TXCOMPL_MASK |
XEMACPS_TXSR_USEDREAD_MASK);
((u32)XEMACPS_TXSR_TXCOMPL_MASK |
(u32)XEMACPS_TXSR_USEDREAD_MASK));
InstancePtr->SendHandler(InstancePtr->SendRef);
}
/* Receive error conditions interrupt */
if (RegISR & (XEMACPS_IXR_RX_ERR_MASK)) {
if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
/* Clear RX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET);
@ -189,11 +218,11 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
/* Fix for CR # 692702. Write to bit 18 of net_ctrl
* register to flush a packet out of Rx SRAM upon
* an error for receive buffer not available. */
if (RegISR & XEMACPS_IXR_RXUSED_MASK) {
if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
RegCtrl =
XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
RegCtrl |= XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, RegCtrl);
}
@ -205,9 +234,20 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
* will be asserted the same time.
* Have to distinguish this bit to handle the real error condition.
*/
/* Transmit Q1 error conditions interrupt */
if ((InstancePtr->Version == 7) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
/* Clear Interrupt Q1 status register */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
RegQ1ISR);
}
/* Transmit error conditions interrupt */
if (RegISR & (XEMACPS_IXR_TX_ERR_MASK) &&
!(RegISR & (XEMACPS_IXR_TXCOMPL_MASK))) {
if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
(!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
/* Clear TX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET);

11
XilinxProcessorIPLib/drivers/emacps/src/xemacps_sinit.c
View file

@ -50,14 +50,16 @@
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xemacps.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/*************************** Variable Definitions *****************************/
extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
/***************** Macros (Inline Functions) Definitions *********************/
@ -78,16 +80,15 @@
******************************************************************************/
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
{
extern XEmacPs_Config XEmacPs_ConfigTable[];
XEmacPs_Config *CfgPtr = NULL;
int i;
u32 i;
for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) {
for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
CfgPtr = &XEmacPs_ConfigTable[i];
break;
}
}
return (CfgPtr);
return (XEmacPs_Config *)(CfgPtr);
}