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bsp: deprecated the older version 5.1 and created new minor vesion 5.2

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<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
<p class="MsoNormal">I have attached standalone BSP patch for deprecating the older version and creating a new version as it is a big patch<o:p></o:p></p>
<p class="MsoNormal">It is located at <o:p></o:p></p>
<p class="MsoNormal">/proj/epdsw2/kinjal/2015.2/0001-bsp-deprecated-the-older-version-5.1-and-created-new<o:p></o:p></p>
<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">Kinjal<o:p></o:p></p>
<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
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From 256718ca92a9b3407cac916c7c5c3ab048488aaa Mon Sep 17 00:00:00 2001
From: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Date: Thu, 28 May 2015 17:10:25 +0530
Subject: [EMBEDDEDSW PATCH 1/6] bsp: deprecated the older version 5.1 and created new minor vesion 5.2

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2015-05-28 21:14:27 +08:00 • committed by Nava kishore Manne
parent b9158b38d7
commit 54eda83e22
305 changed files with 85121 additions and 0 deletions
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##############################################################################
#
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
##############################################################################
OPTION psf_version = 2.1;
BEGIN OS standalone
OPTION drc = standalone_drc;
OPTION APP_LINKER_FLAGS = "-Wl,--start-group,-lxil,-lgcc,-lc,--end-group";
OPTION DESC = "Standalone is a simple, low-level software layer. It provides access to basic processor features such as caches, interrupts and exceptions as well as the basic features of a hosted environment, such as standard input and output, profiling, abort and exit.";
OPTION copyfiles = all;
OPTION OS_STATE = ACTIVE;
OPTION VERSION = 5.2;
OPTION NAME = standalone;
PARAM name = stdin, desc = "stdin peripheral", type = peripheral_instance, requires_interface = stdin, default=none, range = (ps7_uart, ps7_coresight_comp, iomodule, axi_uartlite, axi_uart16550, mdm);
PARAM name = stdout, desc = "stdout peripheral", type = peripheral_instance, requires_interface = stdout, default=none, range = (ps7_uart, ps7_coresight_comp, iomodule, axi_uartlite, axi_uart16550, mdm);
BEGIN CATEGORY sw_intrusive_profiling
PARAM name = enable_sw_intrusive_profiling, type = bool, default = false, desc = "Enable S/W Intrusive Profiling on Hardware Targets", permit = user;
PARAM name = profile_timer, type = peripheral_instance, range = (opb_timer, xps_timer, axi_timer), default = none, desc = "Specify the Timer to use for Profiling. For PowerPC system, specify none to use PIT timer. For ARM system, specify none to use SCU timer";
END CATEGORY
BEGIN CATEGORY microblaze_exceptions
PARAM name = microblaze_exceptions, type = bool, default = false, desc = "Enable MicroBlaze Exceptions", permit = user;
PARAM name = predecode_fpu_exceptions, desc = "(MicroBlaze) Predecode FPU exceptions and save operand info before invoking user registered exception handler.", type = bool, default = false, permit = user;
END CATEGORY
END OS

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PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER STDIN = *
PARAMETER STDOUT = *
END

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##############################################################################
#
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
##############################################################################
# ----------------------------------------------------------------------------
# The following are hardcoded for Zynq.
# We can obtain the scu timer/gic baseaddr from the xml, but other parameters
# need to be hardcoded. hardcode everything..
# ----------------------------------------------------------------------------
#TODO these hardcoding parameters can be removed. It can directly come from PS7 IP
set scutimer_baseaddr 0xF8F00600
set scutimer_intr 29
set scugic_cpu_base 0xF8F00100
set scugic_dist_base 0xF8F01000
# --------------------------------------
# Tcl procedure standalone_drc
# -------------------------------------
proc standalone_drc {os_handle} {
}
# --------------------------------------
# Tcl procedure generate
# -------------------------------------
proc generate {os_handle} {
global env
set need_config_file "false"
# Copy over the right set of files as src based on processor type
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set proctype [common::get_property IP_NAME $hw_proc_handle]
set procname [common::get_property NAME $hw_proc_handle]
set enable_sw_profile [common::get_property CONFIG.enable_sw_intrusive_profiling $os_handle]
set mb_exceptions false
# proctype should be "microblaze" or psu_cortexa53 or psu_cortexr5 or ps7_cortexa9
set mbsrcdir "./src/microblaze"
set cortexa53srcdir "./src/cortexa53"
set cortexr5srcdir "./src/cortexr5"
set cortexa9srcdir "./src/cortexa9"
set procdrv [hsi::get_sw_processor]
set commonsrcdir "./src/common"
foreach entry [glob -nocomplain [file join $commonsrcdir *]] {
file copy -force $entry "./src"
}
# Only processor specific file should be copied to specified standalone folder
# write a API which needs compiler,
switch $proctype {
"microblaze" {
foreach entry [glob -nocomplain [file join $mbsrcdir *]] {
# Copy over only files that are not related to exception handling. All such files have exception in their names
file copy -force $entry "./src/"
}
set need_config_file "true"
set mb_exceptions [mb_has_exceptions $hw_proc_handle]
}
"psu_microblaze" {
foreach entry [glob -nocomplain [file join $mbsrcdir *]] {
# Copy over only files that are not related to exception handling. All such files have exception in their names
file copy -force $entry "./src/"
}
set need_config_file "true"
set mb_exceptions [mb_has_exceptions $hw_proc_handle]
}
"psu_cortexa53" {
set procdrv [hsi::get_sw_processor]
set ccdir "./src/cortexa53/gcc"
foreach entry [glob -nocomplain [file join $cortexa53srcdir *]] {
file copy -force $entry "./src/"
}
foreach entry [glob -nocomplain [file join $ccdir *]] {
file copy -force $entry "./src/"
}
file delete -force "./src/gcc"
file delete -force "./src/profile"
if { $enable_sw_profile == "true" } {
error "ERROR: Profiling is not supported for A53"
}
set file_handle [::hsi::utils::open_include_file "xparameters.h"]
puts $file_handle "#include \"xparameters_ps.h\""
puts $file_handle ""
close $file_handle
}
"psu_cortexr5" {
set procdrv [hsi::get_sw_processor]
set ccdir "./src/cortexr5/gcc"
foreach entry [glob -nocomplain [file join $cortexr5srcdir *]] {
file copy -force $entry "./src/"
}
foreach entry [glob -nocomplain [file join $ccdir *]] {
file copy -force $entry "./src/"
}
file delete -force "./src/gcc"
file delete -force "./src/profile"
if { $enable_sw_profile == "true" } {
error "ERROR: Profiling is not supported for R5"
}
set file_handle [::hsi::utils::open_include_file "xparameters.h"]
puts $file_handle "#include \"xparameters_ps.h\""
puts $file_handle ""
close $file_handle
}
"ps7_cortexa9" {
set procdrv [hsi::get_sw_processor]
set compiler [common::get_property CONFIG.compiler $procdrv]
if {[string compare -nocase $compiler "armcc"] == 0} {
set ccdir "./src/cortexa9/armcc"
} elseif {[string compare -nocase $compiler "iccarm"] == 0} {
set ccdir "./src/cortexa9/iccarm"
} else {
set ccdir "./src/cortexa9/gcc"
}
foreach entry [glob -nocomplain [file join $cortexa9srcdir *]] {
file copy -force $entry "./src/"
}
foreach entry [glob -nocomplain [file join $ccdir *]] {
file copy -force $entry "./src/"
}
file delete -force "./src/armcc"
file delete -force "./src/gcc"
file delete -force "./src/iccarm"
if {[string compare -nocase $compiler "armcc"] == 0} {
file delete -force "./src/profile"
set enable_sw_profile "false"
}
if {[string compare -nocase $compiler "iccarm"] == 0} {
file delete -force "./src/profile"
set enable_sw_profile "false"
}
set file_handle [::hsi::utils::open_include_file "xparameters.h"]
puts $file_handle "#include \"xparameters_ps.h\""
puts $file_handle ""
close $file_handle
}
"default" {puts "unknown processor type $proctype\n"}
}
# Write the Config.make file
set makeconfig [open "./src/config.make" w]
# print_generated_header_tcl $makeconfig "Configuration parameters for Standalone Makefile"
if { $proctype == "microblaze" || $proctype == "psu_microblaze" } {
puts $makeconfig "LIBSOURCES = *.c *.S"
puts $makeconfig "PROFILE_ARCH_OBJS = profile_mcount_mb.o"
} elseif { $proctype == "psu_cortexr5" } {
puts $makeconfig "LIBSOURCES = *.c *.S"
} elseif { $proctype == "psu_cortexa53" } {
puts $makeconfig "LIBSOURCES = *.c *.s *.S"
} elseif { $proctype == "ps7_cortexa9" } {
if {[string compare -nocase $compiler "armcc"] == 0} {
puts $makeconfig "LIBSOURCES = *.c *.s"
} elseif {[string compare -nocase $compiler "iccarm"] == 0} {
puts $makeconfig "LIBSOURCES = *.c *.s"
} else {
puts $makeconfig "LIBSOURCES = *.c *.S"
puts $makeconfig "PROFILE_ARCH_OBJS = profile_mcount_arm.o"
}
} else {
error "ERROR: processor $proctype is not supported"
}
if { $enable_sw_profile == "true" } {
puts $makeconfig "LIBS = standalone_libs profile_libs"
} else {
puts $makeconfig "LIBS = standalone_libs"
}
close $makeconfig
# Remove microblaze, cortexr5, cortexa53 and common directories...
file delete -force $mbsrcdir
file delete -force $cortexr5srcdir
file delete -force $cortexa53srcdir
file delete -force $cortexa9srcdir
file delete -force $commonsrcdir
# Handle stdin and stdout
::hsi::utils::handle_stdin $os_handle
::hsi::utils::handle_stdout $os_handle
#Handle Profile configuration
if { $enable_sw_profile == "true" } {
handle_profile $os_handle $proctype
}
set file_handle [::hsi::utils::open_include_file "xparameters.h"]
puts $file_handle "\n/******************************************************************/\n"
close $file_handle
# Create config file for microblaze interrupt handling
if { [string compare -nocase $need_config_file "true"] == 0 } {
xhandle_mb_interrupts
}
# Create config files for Microblaze exception handling
if { $proctype == "microblaze" && [mb_has_exceptions $hw_proc_handle] } {
xcreate_mb_exc_config_file $os_handle
}
# Create bspconfig file
set bspcfg_fn [file join "src" "bspconfig.h"]
file delete $bspcfg_fn
set bspcfg_fh [open $bspcfg_fn w]
::hsi::utils::write_c_header $bspcfg_fh "Configurations for Standalone BSP"
if { $proctype == "microblaze" && [mb_has_pvr $hw_proc_handle] } {
set pvr [common::get_property CONFIG.C_PVR $hw_proc_handle]
switch $pvr {
"0" {
puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE"
}
"1" {
puts $bspcfg_fh "#define MICROBLAZE_PVR_BASIC"
}
"2" {
puts $bspcfg_fh "#define MICROBLAZE_PVR_FULL"
}
"default" {
puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE"
}
}
} else {
puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE"
}
close $bspcfg_fh
}
# --------------------------------------
# Tcl procedure xhandle_mb_interrupts
# --------------------------------------
proc xhandle_mb_interrupts {} {
set default_interrupt_handler "XNullHandler"
set default_arg "XNULL"
set source_interrupt_handler $default_interrupt_handler
set source_handler_arg $default_arg
# Handle the interrupt pin
set sw_proc_handle [hsi::get_sw_processor]
set periph [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set source_ports [::hsi::utils::get_interrupt_sources $periph]
if {[llength $source_ports] > 1} {
error "ERROR: Too many interrupting ports on the MicroBlaze. Should only find 1" "" "hsi_error"
return
}
if { [llength $source_ports] != 0 } {
set source_periph [hsi::get_cells -of_objects $source_ports]
if { [llength $source_periph] != 0 } {
set source_driver [hsi::get_drivers -filter "HW_INSTANCE==$source_periph"]
if { [llength $source_driver] != 0 } {
set intr_array [hsi::get_arrays -of_objects $source_driver -filter "NAME==interrupt_handler"]
if { [llength $intr_array] != 0 } {
set array_size [common::get_property PROPERTY.size $intr_array]
for { set i 0 } { $i < $array_size } { incr i } {
set int_port [lindex [common::get_property PARAM.int_port $intr_array] $i]
if { [llength $int_port] != 0 } {
if { [string compare -nocase $int_port $source_ports] == 0 } {
set source_interrupt_handler [lindex [common::get_property PARAM.int_handler $intr_array] $i]
set source_handler_arg [lindex [common::get_property PARAM.int_handler_arg $intr_array] $i]
if { [string compare -nocase $source_handler_arg DEVICE_ID] == 0 } {
set source_handler_arg [::hsi::utils::get_ip_param_name $source_periph "DEVICE_ID"]
} else {
set source_handler_arg [::hsi::utils::get_ip_param_name $source_periph "C_BASEADDR"]
}
}
}
}
}
}
}
}
# Generate microblaze_interrupts_g.c file...
xcreate_mb_intr_config_file $source_interrupt_handler $source_handler_arg
}
# -------------------------------------------
# Tcl procedure xcreate_mb_intr_config file
# -------------------------------------------
proc xcreate_mb_intr_config_file {handler arg} {
set mb_table "MB_InterruptVectorTable"
set filename [file join "src" "microblaze_interrupts_g.c"]
file delete $filename
set config_file [open $filename w]
::hsi::utils::write_c_header $config_file "Interrupt Handler Table for MicroBlaze Processor"
puts $config_file "#include \"microblaze_interrupts_i.h\""
puts $config_file "#include \"xparameters.h\""
puts $config_file "\n"
puts $config_file [format "extern void %s (void *);" $handler]
puts $config_file "\n/*"
puts $config_file "* The interrupt handler table for microblaze processor"
puts $config_file "*/\n"
puts $config_file [format "%sEntry %s\[\] =" $mb_table $mb_table]
puts $config_file "\{"
puts -nonewline $config_file [format "\{\t%s" $handler]
puts -nonewline $config_file [format ",\n\t(void*) %s\}" $arg]
puts -nonewline $config_file "\n\};"
puts $config_file "\n"
close $config_file
}
# -------------------------------------------
# Tcl procedure xcreate_mb_exc_config file
# -------------------------------------------
proc xcreate_mb_exc_config_file {os_handle} {
set hfilename [file join "src" "microblaze_exceptions_g.h"]
file delete $hfilename
set hconfig_file [open $hfilename w]
::hsi::utils::write_c_header $hconfig_file "Exception Handling Header for MicroBlaze Processor"
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set procvlnv [common::get_property VLNV $hw_proc_handle]
set procvlnv [split $procvlnv :]
set procver [lindex $procvlnv 3]
set ibus_ee [common::get_property CONFIG.C_M_AXI_I_BUS_EXCEPTION $hw_proc_handle]
set dbus_ee [common::get_property CONFIG.C_M_AXI_D_BUS_EXCEPTION $hw_proc_handle]
set ill_ee [common::get_property CONFIG.C_ILL_OPCODE_EXCEPTION $hw_proc_handle]
set unalign_ee [common::get_property CONFIG.C_UNALIGNED_EXCEPTIONS $hw_proc_handle]
set div0_ee [common::get_property CONFIG.C_DIV_ZERO_EXCEPTION $hw_proc_handle]
set mmu_ee [common::get_property CONFIG.C_USE_MMU $hw_proc_handle]
if { $mmu_ee == "" } {
set mmu_ee 0
}
set fsl_ee [common::get_property CONFIG.C_FSL_EXCEPTION $hw_proc_handle]
if { $fsl_ee == "" } {
set fsl_ee 0
}
if { [mb_has_fpu_exceptions $hw_proc_handle] } {
set fpu_ee [common::get_property CONFIG.C_FPU_EXCEPTION $hw_proc_handle]
} else {
set fpu_ee 0
}
set sp_ee [common::get_property CONFIG.C_USE_STACK_PROTECTION $hw_proc_handle]
if { $sp_ee == "" } {
set sp_ee 0
}
set ft_ee [common::get_property CONFIG.C_FAULT_TOLERANT $hw_proc_handle]
if { $ft_ee == "" } {
set ft_ee 0
}
if { $ibus_ee == 0 && $dbus_ee == 0 && $ill_ee == 0 && $unalign_ee == 0
&& $div0_ee == 0 && $fpu_ee == 0 && $mmu_ee == 0 && $fsl_ee == 0
&& $sp_ee == 0 && $ft_ee == 0} {
;# NO exceptions are enabled
;# Do not generate any info in either the header or the C file
close $hconfig_file
return
}
puts $hconfig_file "\#define MICROBLAZE_EXCEPTIONS_ENABLED 1"
if { [mb_can_handle_exceptions_in_delay_slots $procver] } {
puts $hconfig_file "#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS"
}
if { $unalign_ee == 0 } {
puts $hconfig_file "\#define NO_UNALIGNED_EXCEPTIONS 1"
}
if { $ibus_ee == 0 && $dbus_ee == 0 && $ill_ee == 0 && $div0_ee == 0
&& $fpu_ee == 0 && $mmu_ee == 0 && $fsl_ee == 0 } {
;# NO other exceptions are enabled
puts $hconfig_file "\#define NO_OTHER_EXCEPTIONS 1"
}
if { $fpu_ee != 0 } {
puts $hconfig_file "\#define MICROBLAZE_FP_EXCEPTION_ENABLED 1"
set predecode_fpu_exceptions [common::get_property CONFIG.predecode_fpu_exceptions $os_handle]
if {$predecode_fpu_exceptions != false } {
puts $hconfig_file "\#define MICROBLAZE_FP_EXCEPTION_DECODE 1"
}
}
puts $hconfig_file "\n"
close $hconfig_file
}
# --------------------------------------
# Tcl procedure post_generate
#
# This proc removes _interrupt_handler.o
# from libxil.a
# --------------------------------------
proc post_generate {os_handle} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set procname [common::get_property NAME $hw_proc_handle]
set proctype [common::get_property IP_NAME $hw_proc_handle]
if {[string compare -nocase $proctype "microblaze"] == 0} {
set procdrv [hsi::get_sw_processor]
# Remove _interrupt_handler.o from libxil.a for mb-gcc
set archiver [common::get_property CONFIG.archiver $procdrv]
set libgloss_a [file join .. .. lib libgloss.a]
if { ![file exists $libgloss_a] } {
set libgloss_a [file join .. .. lib libxil.a]
}
exec $archiver -d $libgloss_a _interrupt_handler.o
# Remove _hw_exception_handler.o from libgloss.a for microblaze_v3_00_a
if { [mb_has_exceptions $hw_proc_handle] } {
exec $archiver -d $libgloss_a _hw_exception_handler.o
}
}
}
# --------------------------------------
# Return true if this MB has
# exception handling support
# --------------------------------------
proc mb_has_exceptions { hw_proc_handle } {
# Check if the following parameters exist on this MicroBlaze's MPD
set ee [common::get_property CONFIG.C_UNALIGNED_EXCEPTIONS $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_ILL_OPCODE_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_IOPB_BUS_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_DOPB_BUS_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_IPLB_BUS_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_DPLB_BUS_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_M_AXI_I_BUS_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_M_AXI_D_BUS_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_DIV_BY_ZERO_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_DIV_ZERO_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_FPU_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_FSL_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
set ee [common::get_property CONFIG.C_USE_MMU $hw_proc_handle]
if { $ee != ""} {
return true
}
set ee [common::get_property CONFIG.C_USE_STACK_PROTECTION $hw_proc_handle]
if { $ee != ""} {
return true
}
set ee [common::get_property CONFIG.C_FAULT_TOLERANT $hw_proc_handle]
if { $ee != ""} {
return true
}
return false
}
# --------------------------------------
# Return true if this MB has
# FPU exception handling support
# --------------------------------------
proc mb_has_fpu_exceptions { hw_proc_handle } {
# Check if the following parameters exist on this MicroBlaze's MPD
set ee [common::get_property CONFIG.C_FPU_EXCEPTION $hw_proc_handle]
if { $ee != "" } {
return true
}
return false
}
# --------------------------------------
# Return true if this MB has PVR support
# --------------------------------------
proc mb_has_pvr { hw_proc_handle } {
# Check if the following parameters exist on this MicroBlaze's MPD
set pvr [common::get_property CONFIG.C_PVR $hw_proc_handle]
if { $pvr != "" } {
return true
}
return false
}
# --------------------------------------
# Return true if MB ver 'procver' has
# support for handling exceptions in
# delay slots
# --------------------------------------
proc mb_can_handle_exceptions_in_delay_slots { procver } {
if { [string compare -nocase $procver "5.00.a"] >= 0 } {
return true
} else {
return false
}
}
# --------------------------------------
# Generate Profile Configuration
# --------------------------------------
proc handle_profile { os_handle proctype } {
global env
variable scutimer_baseaddr
variable scutimer_intr
variable scugic_cpu_base
variable scugic_dist_base
set proc [hsi::get_sw_processor]
if {$proctype == "ps7_cortexa9"} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle]]
set cpu_freq [common::get_property CONFIG.C_CPU_CLK_FREQ_HZ $hw_proc_handle]
if { [string compare -nocase $cpu_freq ""] == 0 } {
puts "WARNING<profile> :: CPU Clk Frequency not specified, Assuming 666Mhz"
set cpu_freq 666000000
}
} else {
set cpu_freq [common::get_property CONFIG.C_FREQ [hsi::get_cells $proc]]
if { [string compare -nocase $cpu_freq ""] == 0 } {
puts "WARNING<profile> :: CPU Clk Frequency not specified, Assuming 100Mhz"
set cpu_freq 100000000
}
}
set filename [file join "src" "profile" "profile_config.h"]
file delete -force $filename
set config_file [open $filename w]
::hsi::utils::write_c_header $config_file "Profiling Configuration parameters. These parameters
* can be overwritten thru run configuration in SDK"
puts $config_file "#ifndef _PROFILE_CONFIG_H"
puts $config_file "#define _PROFILE_CONFIG_H\n"
puts $config_file "#define BINSIZE 4"
puts $config_file "#define CPU_FREQ_HZ $cpu_freq"
puts $config_file "#define SAMPLE_FREQ_HZ 100000"
puts $config_file "#define TIMER_CLK_TICKS [expr $cpu_freq / 100000]"
# proctype should be "microblaze" or "psu_cortexa9"
switch $proctype {
"microblaze" {
# Microblaze Processor.
puts $config_file "#define PROC_MICROBLAZE 1"
set timer_inst [common::get_property CONFIG.profile_timer $os_handle]
if { [string compare -nocase $timer_inst "none"] == 0 } {
# Profile Timer Not Selected
error "ERROR : Timer for Profiling NOT selected.\nS/W Intrusive Profiling on MicroBlaze requires an axi_timer." "" "mdt_error"
} else {
handle_profile_opbtimer $config_file $timer_inst
}
}
"ps7_cortexa9" {
# Cortex A9 Processor.
puts $config_file "#define PROC_CORTEXA9 1"
set timer_inst [common::get_property CONFIG.profile_timer $os_handle]
if { [string compare -nocase $timer_inst "none"] == 0 } {
# SCU Timer
puts $config_file "#define ENABLE_SCU_TIMER 1"
puts $config_file "#define ENABLE_SYS_INTR 1"
puts $config_file "#define PROFILE_TIMER_BASEADDR $scutimer_baseaddr"
puts $config_file "#define PROFILE_TIMER_INTR_ID $scutimer_intr"
puts $config_file "#define SCUGIC_CPU_BASEADDR $scugic_cpu_base"
puts $config_file "#define SCUGIC_DIST_BASEADDR $scugic_dist_base"
}
}
"default" {error "ERROR: unknown processor type\n"}
}
puts $config_file "\n#endif"
puts $config_file "\n/******************************************************************/\n"
close $config_file
}
#***--------------------------------***-----------------------------------***
# Utility process to call a command and pipe it's output to screen.
# Used instead of Tcl's exec
proc execpipe {COMMAND} {
if { [catch {open "| $COMMAND 2>@stdout"} FILEHANDLE] } {
return "Can't open pipe for '$COMMAND'"
}
set PIPE $FILEHANDLE
fconfigure $PIPE -buffering none
set OUTPUT ""
while { [gets $PIPE DATA] >= 0 } {
append OUTPUT $DATA "\n"
}
if { [catch {close $PIPE} ERRORMSG] } {
if { [string compare "$ERRORMSG" "child process exited abnormally"] == 0 } {
# this error means there was nothing on stderr (which makes sense) and
# there was a non-zero exit code - this is OK as we intentionally send
# stderr to stdout, so we just do nothing here (and return the output)
} else {
return "Error '$ERRORMSG' on closing pipe for '$COMMAND'"
}
}
regsub -all -- "\n$" $OUTPUT "" STRIPPED_STRING
return "$STRIPPED_STRING"
}
# - The xps/opb_timer can be connected directly to Microblaze External Intr Pin.
# - (OR) xps/opb_timer can be connected to xps/opb_intc
proc handle_profile_opbtimer { config_file timer_inst } {
set timer_handle [hsi::get_cells $timer_inst]
set timer_baseaddr [common::get_property CONFIG.C_BASEADDR $timer_handle]
puts $config_file "#define PROFILE_TIMER_BASEADDR [::hsi::utils::format_addr_string $timer_baseaddr "C_BASEADDR"]"
# Figure out how Timer is connected.
set timer_intr [hsi::get_pins -of_objects [hsi::get_cells $timer_handle] Interrupt]
if { [string compare -nocase $timer_intr ""] == 0 } {
error "ERROR <profile> :: Timer Interrupt PORT is not specified" "" "mdt_error"
}
#set mhs_handle [xget_handle $timer_handle "parent"]
# CR 302300 - There can be multiple "sink" for the interrupt. So need to iterate through the list
set intr_port_list [::hsi::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells $timer_intr] INTERRUPT]]
set timer_connection 0
foreach intr_port $intr_port_list {
set intc_handle [hsi::get_cells -of_object $intr_port]
# Check if the Sink is a Global Port. If so, Skip the Port Connection
if { [::hsi::utils::is_external_pin $intr_port] } {
continue
}
set iptype [common::get_property CONFIG.EDK_IPTYPE $intc_handle]
if { [string compare -nocase $iptype "PROCESSOR"] == 0 } {
# Timer Directly Connected to the Processor
puts $config_file "#define ENABLE_SYS_INTR 1"
set timer_connection 1
break
}
set ipsptype [common::get_property CONFIG.EDK_SPECIAL $intc_handle]
if { [string compare -nocase $iptype "PERIPHERAL"] == 0 &&
[string compare -nocase $ipsptype "INTR_CTRL"] == 0 } {
# Timer connected to Interrupt controller
puts $config_file "#define TIMER_CONNECT_INTC 1"
puts $config_file "#define INTC_BASEADDR [xget_value $intc_handle "PARAMETER" "C_BASEADDR"]"
set num_intr_inputs [common::get_property CONFIG.C_NUM_INTR_INPUTS $intc_handle]
# if { $num_intr_inputs == 1 } { ## Always enable system interrupt CR 472288
puts $config_file "#define ENABLE_SYS_INTR 1"
# }
#set signals [split [xget_value $intr_port "VALUE"] "&"]
set signals [::hsi::utils::get_source_pins $intr_port]
set i 1
foreach signal $signals {
set signal [string trim $signal]
if {[string compare -nocase $signal $timer_intr] == 0} {
set timer_id [expr ($num_intr_inputs - $i)]
set timer_mask [expr 0x1 << $timer_id]
puts $config_file "#define PROFILE_TIMER_INTR_ID $timer_id"
puts $config_file "#define PROFILE_TIMER_INTR_MASK [format "0x%x" $timer_mask]"
break
}
incr i
}
set timer_connection 1
break
}
}
if { $timer_connection == 0 } {
error "ERROR <profile> :: Profile Timer Interrupt Signal Not Connected Properly"
}
}

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/*****************************************************************************
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
* 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
* cacheable regions
* Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
* generated by the cpu driver, for enabling caches
* 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
* write-thru caches
* 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
* Updated the MMU table to mark OCM in high address space
* as inner cacheable and reserved space as Invalid
* 3.03a sdm 08/20/11 Changes to support FreeRTOS
* Updated the MMU table to mark upper half of the DDR as
* non-cacheable
* Setup supervisor and abort mode stacks
* Do not initialize/enable L2CC in case of AMP
* Initialize UART1 for 9600bps in case of AMP
* 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
* in case of AMP
* 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
* counters
* 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
* xparameters.h file for CR630532 - Xil_DCacheFlush()/
* Xil_DCacheFlushRange() functions in standalone BSP v3_02a
* for MicroBlaze will invalidate data in the cache instead
* of flushing it for writeback caches
* 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
* Remove redundant dsb/dmb instructions in cache maintenance
* APIs
* Remove redundant dsb in mcr instruction
* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
* 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl in xparameters.h. Update the gcc/translationtable.s
* for the QSPI complete address range - DT644567
* Removed profile directory for armcc compiler and changed
* profiling setting to false in standalone_v2_1_0.tcl file
* Deleting boot.S file after preprocessing for armcc compiler
* 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
* invalidate the caches before enabling back the MMU and
* D cache.
* 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
* xil_mmu.c. Now we invalidate UTLB, Branch predictor
* array, flush the D-cache before changing the attributes
* in translation table. The user need not call Xil_DisableMMU
* before calling Xil_SetTlbAttributes.
* 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
* sgd initialization is present. Changes for this were done in
* uart.c and xil-crt0.s.
* Made changes in xil_io.c to use volatile pointers.
* Made changes in xil_mmu.c to correct the function
* Xil_SetTlbAttributes.
* Changes are made xil-crt0.s to initialize the static
* C++ constructors.
* Changes are made in boot.s, to fix the TTBR settings,
* correct the L2 Cache Auxiliary register settings, L2 cache
* latency settings.
* 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
* sgd usleep.c to use global timer intstead of CP15.
* Made changes in cortexa9/gcc/translation_table.s to map
* the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/xil-crt0.s to initialize
* the global timer.
* Made changes in cortexa9/armcc/boot.S to initialize
* the global timer.
* Made changes in cortexa9/armcc/translation_table.s to
* map the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/boot.S to optimize the
* L2 cache settings. Changes the section properties for
* ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
* and cortexa9/gcc/translation_table.S.
* Made changes in cortexa9/xil_cache.c to change the
* cache invalidation order.
* 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
* compilation/linking issues for C++ compiler.
* Made changes in mb_interface.h to remove compilation/
* linking issues for C++ compiler.
* Added macros for swapb and swaph microblaze instructions
* mb_interface.h
* Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
* for CortexA9.
* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
* 3.07a asa 08/31/12 Added xil_printf.h include
* 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
* Corrected L2 cache sequence disable sequence
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
* 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
* irq/fiq handling.
* Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
* fixes the CR #692094.
* 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
* 3.10a srt 04/18/13 Implemented ARM Erratas.
* Cortex A9 Errata - 742230, 743622, 775420, 794073
* L2Cache PL310 Errata - 588369, 727915, 759370
* Please refer to file 'xil_errata.h' for errata
* description.
* 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
* cache APIs were corresponding to only Layer 1 cache
* memories. New APIs were now added and the existing cache
* related APIs were changed to provide a uniform interface
* to flush/invalidate/enable/disable the complete cache
* system which includes both L1 and L2 caches. The changes
* for these were done in:
* src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
* files.
* Four new files were added for supporting L2 cache. They are:
* microblaze_flush_cache_ext.S-> Flushes L2 cache
* microblaze_flush_cache_ext_range.S -> Flushes a range of
* memory in L2 cache.
* microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
* microblaze_invalidate_cache_ext_range -> Invalidates a
* range of memory in L2 cache.
* These changes are done to implement PR #697214.
* 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
* fix the CR #706464. L2 cache disabling happens independent
* of L1 data cache disable operation. Changes are done in the
* same file in cache handling APIs to do a L2 cache sync
* (poll reg7_?cache_?sync). This fixes CR #700542.
* 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
* interrupts for ARM. These are done to fix the CR#699680.
* 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
* sync operation. This fixes the CR# 716781.
* 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
* for armcc toolchain.
* Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
* fix issues related to NEON context saving. The assembly
* routines for IRQ and FIQ handling are modified.
* Deprecated the older BSP (3.10a).
* 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
* various potential issues. Made changes in the function
* Xil_SetAttributes in file xil_mmu.c.
* 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
* in src\cortexa9 and src\microblaze folders.
* 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
* L2 cache sync operation and to fix issues around complete
* L2 cache flush/invalidation by ways.
* 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
* to fix linking issues with armcc/DS-5. Modified the armcc
* makefile to fix issues.
* 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
* 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
* 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
* and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
* src\cortexa9\armcc\) to fix CR#767251
* 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
* Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
* Few cache lines were missed to invalidate when unaligned address
* invalidation was accommodated in Xil_DCacheInvalidateRange.
* In Xil_L1DCacheInvalidate, while invalidating all L1D cache
* stack memory (which contains return address) was invalidated. So
* stack memory is flushed first and then L1D cache is invalidated.
* This is done to fix CR #763829
* 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
* mblaze_nt_types.h file and replace uint32_t with u32 in the
* profile_hist.c to fix the above CR.
* 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
* instead of libxil.a and added prototypes for
* microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
* mb_interface.h
* 4.1 hk 04/18/14 Add sleep function.
* 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
* some of the *.s files inMB BSP source to *.S.
* 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
* 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
* CR#794205
* 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
* common/xil_testcache.c
* Fix for CR#764881.
* 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
* output the DEBUG logs when -DDEBUG flag is enabled in BSP.
* 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
* Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
* 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
* cortexa9/armcc/boot.s. Added default exception handlers for data
* abort and prefetch abort using handlers called
* DataAbortHandler and PrefetchAbortHandler respectively in
* cortexa9/xil_exception.c to fix CR#802862.
* 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
* issue of improper linking of translation_table.s
* 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
* in tool chain to avoid conflicts into some special cases
* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
* Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
* 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
* containing type def u32 defined in xil_types.g to resolve issue of
* CR#805869
* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
* it is not possible to generate timer in nanosecond due to limited
* cpu frequency
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
* uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
* and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
* removed function definition of XSmc_NorInit and XSmc_NorInit from
* cortexa9/smc.h
* 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
* cache_ext_range declarations in mb_interface.h CR#783821.
* Modified profile_mcount_mb.S to fix CR#808412.
* 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
* cortexa9/iccarm to fix CR#816701
* 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
* armcc/translation_table.s and iccarm/translation_table.s
* to properly defined reserved entries according to address map for
* fixing CR#820146
* 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
* and cortexa9/armcc/translation_table.s to resolve compilation
* error for solving CR#822897
* 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for
* MISRA-C:2012 compliance.
* 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
* adding src/common/xplatform_info.*s
* 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
* removed incorrect initialization of TLB lockdown register to fix
* CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
* and iccarm/boot.s
* 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
* for iccarm and armcc compiler of cortexA9
* 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
* and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
* caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
* of L2Cache is done later.
* 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
* Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
* taking long time to fix CR#853097. L2CacheSync is added into
* Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
* Xil_L2CacheInvalidate APIs are modified to flush the complete stack
* instead of just System Stack
* 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
* to update ECC_FLAGS and also take the compiler and archiver as specified
* in settings instead of hardcoding it.
*****************************************************************************************/

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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
*
* @note Dummy File for backwards compatibility
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
* </pre>
*
******************************************************************************/
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
/** @name Legacy types
* Deprecated legacy types.
* @{
*/
typedef unsigned char Xuint8; /**< unsigned 8-bit */
typedef char Xint8; /**< signed 8-bit */
typedef unsigned short Xuint16; /**< unsigned 16-bit */
typedef short Xint16; /**< signed 16-bit */
typedef unsigned long Xuint32; /**< unsigned 32-bit */
typedef long Xint32; /**< signed 32-bit */
typedef float Xfloat32; /**< 32-bit floating point */
typedef double Xfloat64; /**< 64-bit double precision FP */
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
#if !defined __XUINT64__
typedef struct
{
Xuint32 Upper;
Xuint32 Lower;
} Xuint64;
#endif
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XIL_TYPES_H
typedef Xuint32 u32;
typedef Xuint16 u16;
typedef Xuint8 u8;
#endif
#else
#include <linux/types.h>
#endif
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
/*
* Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
* Please use NULL, TRUE and FALSE
*/
#define XNULL NULL
#define XTRUE TRUE
#define XFALSE FALSE
/*
* This file is deprecated and users
* should use xil_types.h and xil_assert.h\n\r
*/
#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
#warning Please refer the Standalone BSP UG647 for further details
#endif /* end of protection macro */

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#ifndef XDEBUG /* prevent circular inclusions */
#define XDEBUG /* by using protection macros */
#if defined(DEBUG) && !defined(NDEBUG)
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
int printf(const char *format, ...);
#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
#define xdbg_current_types (XDBG_DEBUG_GENERAL)
#define xdbg_stmnt(x) x
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
#define xdbg_printf(...)
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#endif /* XDEBUG */

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/*
* Select which target environment we are operating under
*/
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
/* Standalone environment selected */
#else
#include "xenv_standalone.h"
#endif
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implemention MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef s32 XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.c
*
* This file contains basic assert related functions for Xilinx software IP.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 Initial release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/**
* This variable allows testing to be done easier with asserts. An assert
* sets this variable such that a driver can evaluate this variable
* to determine if an assert occurred.
*/
u32 Xil_AssertStatus;
/**
* This variable allows the assert functionality to be changed for testing
* such that it does not wait infinitely. Use the debugger to disable the
* waiting during testing of asserts.
*/
/*s32 Xil_AssertWait = 1*/
/* The callback function to be invoked when an assert is taken */
static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Implement assert. Currently, it calls a user-defined callback function
* if one has been set. Then, it potentially enters an infinite loop depending
* on the value of the Xil_AssertWait variable.
*
* @param file is the name of the filename of the source
* @param line is the linenumber within File
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Assert(const char8 *File, s32 Line)
{
s32 Xil_AssertWait = 1;
/* if the callback has been set then invoke it */
if (Xil_AssertCallbackRoutine != 0) {
(*Xil_AssertCallbackRoutine)(File, Line);
}
/* if specified, wait indefinitely such that the assert will show up
* in testing
*/
while (Xil_AssertWait != 0) {
}
}
/*****************************************************************************/
/**
*
* Set up a callback function to be invoked when an assert occurs. If there
* was already a callback installed, then it is replaced.
*
* @param routine is the callback to be invoked when an assert is taken
*
* @return None.
*
* @note This function has no effect if NDEBUG is set
*
******************************************************************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine)
{
Xil_AssertCallbackRoutine = Routine;
}
/*****************************************************************************/
/**
*
* Null handler function. This follows the XInterruptHandler signature for
* interrupt handlers. It can be used to assign a null handler (a stub) to an
* interrupt controller vector table.
*
* @param NullParameter is an arbitrary void pointer and not used.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XNullHandler(void *NullParameter)
{
(void *) NullParameter;
}

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.h
*
* This file contains assert related functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
#define XIL_ASSERT_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XIL_ASSERT_NONE 0U
#define XIL_ASSERT_OCCURRED 1U
#define XNULL NULL
extern u32 Xil_AssertStatus;
extern void Xil_Assert(const char8 *File, s32 Line);
void XNullHandler(void *NullParameter);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef NDEBUG
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do not return anything
* (void). This in conjunction with the Xil_AssertWait boolean can be used to
* accomodate tests so that asserts which fail allow execution to continue.
*
* @param Expression is the expression to evaluate. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertVoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do return a value. This in
* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
* so that asserts which fail allow execution to continue.
*
* @param Expression is the expression to evaluate. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertNonvoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do not
* return anything (void). Use for instances where an assert should always
* occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertVoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do return
* a value. Use for instances where an assert should always occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertNonvoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
}
#else
#define Xil_AssertVoid(Expression)
#define Xil_AssertVoidAlways()
#define Xil_AssertNonvoid(Expression)
#define Xil_AssertNonvoidAlways()
#endif
/************************** Function Prototypes ******************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_vxworks.h
*
* Contains the cache related functions for VxWorks that is wrapped by
* xil_cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 12/11/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_CACHE_VXWORKS_H
#define XIL_CACHE_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#if (CPU_FAMILY==PPC)
#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
#define Xil_DCacheInvalidateRange(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_DCacheFlushRange(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
#define Xil_ICacheInvalidateRange(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_hal.h
*
* Contains all the HAL header files.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/28/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_HAL_H
#define XIL_HAL_H
#include "xil_cache.h"
#include "xil_io.h"
#include "xil_assert.h"
#include "xil_exception.h"
#include "xil_types.h"
#endif

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testcache.c
*
* Contains utility functions to test cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/28/09 Initial release
* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
* cache line.
* </pre>
*
* @note
*
* This file contain functions that all operate on HAL.
*
******************************************************************************/
#ifdef __ARM__
#include "xil_cache.h"
#include "xil_testcache.h"
#include "xil_types.h"
#include "xpseudo_asm.h"
#ifdef __aarch64__
#include "xreg_cortexa53.h"
#else
#include "xreg_cortexr5.h"
#endif
#include "xil_types.h"
extern void xil_printf(const char8 *ctrl1, ...);
#define DATA_LENGTH 128
#ifdef __aarch64__
static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
#else
static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
#endif
/**
* Perform DCache range related API test such as Xil_DCacheFlushRange and
* Xil_DCacheInvalidateRange. This test function writes a constant value
* to the Data array, flushes the range, writes a new value, then invalidates
* the corresponding range.
*
* @return
*
* - 0 is returned for a pass
* - -1 is returned for a failure
*/
s32 Xil_TestDCacheRange(void)
{
s32 Index;
s32 Status = 0;
u32 CtrlReg;
INTPTR Value;
xil_printf("-- Cache Range Test --\n\r");
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0xA0A00505;
xil_printf(" initialize Data done:\r\n");
Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
xil_printf(" flush range done\r\n");
dsb();
#ifdef __aarch64__
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
mtcp(SCTLR_EL3,CtrlReg);
#else
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
dsb();
Status = 0;
for (Index = 0; Index < DATA_LENGTH; Index++) {
Value = Data[Index];
if (Value != 0xA0A00505) {
Status = -1;
xil_printf("Data[%d] = %x\r\n", Index, Value);
break;
}
}
if (!Status) {
xil_printf(" Flush worked\r\n");
}
else {
xil_printf("Error: flush dcache range not working\r\n");
}
dsb();
#ifdef __aarch64__
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
mtcp(SCTLR_EL3,CtrlReg);
#else
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
dsb();
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0xA0A0C505;
Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = Index + 3;
Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
xil_printf(" invalidate dcache range done\r\n");
dsb();
#ifdef __aarch64__
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
mtcp(SCTLR_EL3,CtrlReg);
#else
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
dsb();
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0xA0A0A05;
dsb();
#ifdef __aarch64__
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
mtcp(SCTLR_EL3,CtrlReg);
#else
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
dsb();
Status = 0;
for (Index = 0; Index < DATA_LENGTH; Index++) {
Value = Data[Index];
if (Value != 0xA0A0A05) {
Status = -1;
xil_printf("Data[%d] = %x\r\n", Index, Value);
break;
}
}
if (!Status) {
xil_printf(" Invalidate worked\r\n");
}
else {
xil_printf("Error: Invalidate dcache range not working\r\n");
}
xil_printf("-- Cache Range Test Complete --\r\n");
return Status;
}
/**
* Perform DCache all related API test such as Xil_DCacheFlush and
* Xil_DCacheInvalidate. This test function writes a constant value
* to the Data array, flushes the DCache, writes a new value, then invalidates
* the DCache.
*
* @return
* - 0 is returned for a pass
* - -1 is returned for a failure
*/
s32 Xil_TestDCacheAll(void)
{
s32 Index;
s32 Status;
INTPTR Value;
u32 CtrlReg;
xil_printf("-- Cache All Test --\n\r");
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0x50500A0A;
xil_printf(" initialize Data done:\r\n");
Xil_DCacheFlush();
xil_printf(" flush all done\r\n");
dsb();
#ifdef __aarch64__
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
mtcp(SCTLR_EL3,CtrlReg);
#else
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
dsb();
Status = 0;
for (Index = 0; Index < DATA_LENGTH; Index++) {
Value = Data[Index];
if (Value != 0x50500A0A) {
Status = -1;
xil_printf("Data[%d] = %x\r\n", Index, Value);
break;
}
}
if (!Status) {
xil_printf(" Flush all worked\r\n");
}
else {
xil_printf("Error: Flush dcache all not working\r\n");
}
dsb();
#ifdef __aarch64__
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
mtcp(SCTLR_EL3,CtrlReg);
#else
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
dsb();
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0x505FFA0A;
Xil_DCacheFlush();
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = Index + 3;
Xil_DCacheInvalidate();
xil_printf(" invalidate all done\r\n");
dsb();
#ifdef __aarch64__
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
mtcp(SCTLR_EL3,CtrlReg);
#else
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
dsb();
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0x50CFA0A;
dsb();
#ifdef __aarch64__
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
mtcp(SCTLR_EL3,CtrlReg);
#else
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
dsb();
Status = 0;
for (Index = 0; Index < DATA_LENGTH; Index++) {
Value = Data[Index];
if (Value != 0x50CFA0A) {
Status = -1;
xil_printf("Data[%d] = %x\r\n", Index, Value);
break;
}
}
if (!Status) {
xil_printf(" Invalidate all worked\r\n");
}
else {
xil_printf("Error: Invalidate dcache all not working\r\n");
}
xil_printf("-- DCache all Test Complete --\n\r");
return Status;
}
/**
* Perform Xil_ICacheInvalidateRange() on a few function pointers.
*
* @return
*
* - 0 is returned for a pass
* The function will hang if it fails.
*/
s32 Xil_TestICacheRange(void)
{
Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
xil_printf("-- Invalidate icache range done --\r\n");
return 0;
}
/**
* Perform Xil_ICacheInvalidate().
*
* @return
*
* - 0 is returned for a pass
* The function will hang if it fails.
*/
s32 Xil_TestICacheAll(void)
{
Xil_ICacheInvalidate();
xil_printf("-- Invalidate icache all done --\r\n");
return 0;
}
#endif

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testcache.h
*
* This file contains utility functions to test cache.
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 07/29/09 First release
*
******************************************************************************/
#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
#define XIL_TESTCACHE_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern s32 Xil_TestDCacheRange(void);
extern s32 Xil_TestDCacheAll(void);
extern s32 Xil_TestICacheRange(void);
extern s32 Xil_TestICacheAll(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmemend.c
*
* Contains the memory test utility functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xil_testio.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions ****************************/
/************************** Function Prototypes *****************************/
/**
*
* Endian swap a 16-bit word.
* @param Data is the 16-bit word to be swapped.
* @return The endian swapped value.
*
*/
static u16 Swap16(u16 Data)
{
return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
}
/**
*
* Endian swap a 32-bit word.
* @param Data is the 32-bit word to be swapped.
* @return The endian swapped value.
*
*/
static u32 Swap32(u32 Data)
{
u16 Lo16;
u16 Hi16;
u16 Swap16Lo;
u16 Swap16Hi;
Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
Lo16 = (u16)(Data & 0x0000FFFFU);
Swap16Lo = Swap16(Lo16);
Swap16Hi = Swap16(Hi16);
return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
}
/*****************************************************************************/
/**
*
* Perform a destructive 8-bit wide register IO test where the register is
* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
* values.
*
* @param Addr is a pointer to the region of memory to be tested.
* @param Length is the Length of the block.
* @param Value is the constant used for writting the memory.
*
* @return
*
* - -1 is returned for a failure
* - 0 is returned for a pass
*
*****************************************************************************/
s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
{
u8 ValueIn;
s32 Index;
s32 Status = 0;
for (Index = 0; Index < Length; Index++) {
Xil_Out8((INTPTR)Addr, Value);
ValueIn = Xil_In8((INTPTR)Addr);
if ((Value != ValueIn) && (Status == 0)) {
Status = -1;
break;
}
}
return Status;
}
/*****************************************************************************/
/**
*
* Perform a destructive 16-bit wide register IO test. Each location is tested
* by sequentially writing a 16-bit wide register, reading the register, and
* comparing value. This function tests three kinds of register IO functions,
* normal register IO, little-endian register IO, and big-endian register IO.
* When testing little/big-endian IO, the function performs the following
* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
* read-in value before comparing is controlled by the 5th argument.
*
* @param Addr is a pointer to the region of memory to be tested.
* @param Length is the Length of the block.
* @param Value is the constant used for writting the memory.
* @param Kind is the test kind. Acceptable values are:
* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
* @param Swap indicates whether to byte swap the read-in value.
*
* @return
*
* - -1 is returned for a failure
* - 0 is returned for a pass
*
*****************************************************************************/
s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
{
u16 *TempAddr16;
u16 ValueIn = 0U;
s32 Index;
TempAddr16 = Addr;
Xil_AssertNonvoid(TempAddr16 != NULL);
for (Index = 0; Index < Length; Index++) {
switch (Kind) {
case XIL_TESTIO_LE:
Xil_Out16LE((INTPTR)TempAddr16, Value);
break;
case XIL_TESTIO_BE:
Xil_Out16BE((INTPTR)TempAddr16, Value);
break;
default:
Xil_Out16((INTPTR)TempAddr16, Value);
break;
}
ValueIn = Xil_In16((INTPTR)TempAddr16);
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap16(ValueIn);
}
if (Value != ValueIn) {
return -1;
}
/* second round */
Xil_Out16((INTPTR)TempAddr16, Value);
switch (Kind) {
case XIL_TESTIO_LE:
ValueIn = Xil_In16LE((INTPTR)TempAddr16);
break;
case XIL_TESTIO_BE:
ValueIn = Xil_In16BE((INTPTR)TempAddr16);
break;
default:
ValueIn = Xil_In16((INTPTR)TempAddr16);
break;
}
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap16(ValueIn);
}
if (Value != ValueIn) {
return -1;
}
TempAddr16 += sizeof(u16);
}
return 0;
}
/*****************************************************************************/
/**
*
* Perform a destructive 32-bit wide register IO test. Each location is tested
* by sequentially writing a 32-bit wide regsiter, reading the register, and
* comparing value. This function tests three kinds of register IO functions,
* normal register IO, little-endian register IO, and big-endian register IO.
* When testing little/big-endian IO, the function perform the following
* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
* before comparing is controlled by the 5th argument.
*
* @param Addr is a pointer to the region of memory to be tested.
* @param Length is the Length of the block.
* @param Value is the constant used for writting the memory.
* @param Kind is the test kind. Acceptable values are:
* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
* @param Swap indicates whether to byte swap the read-in value.
*
* @return
*
* - -1 is returned for a failure
* - 0 is returned for a pass
*
*****************************************************************************/
s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
{
u32 *TempAddr;
u32 ValueIn = 0U;
s32 Index;
TempAddr = Addr;
Xil_AssertNonvoid(TempAddr != NULL);
for (Index = 0; Index < Length; Index++) {
switch (Kind) {
case XIL_TESTIO_LE:
Xil_Out32LE((INTPTR)TempAddr, Value);
break;
case XIL_TESTIO_BE:
Xil_Out32BE((INTPTR)TempAddr, Value);
break;
default:
Xil_Out32((INTPTR)TempAddr, Value);
break;
}
ValueIn = Xil_In32((INTPTR)TempAddr);
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap32(ValueIn);
}
if (Value != ValueIn) {
return -1;
}
/* second round */
Xil_Out32((INTPTR)TempAddr, Value);
switch (Kind) {
case XIL_TESTIO_LE:
ValueIn = Xil_In32LE((INTPTR)TempAddr);
break;
case XIL_TESTIO_BE:
ValueIn = Xil_In32BE((INTPTR)TempAddr);
break;
default:
ValueIn = Xil_In32((INTPTR)TempAddr);
break;
}
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap32(ValueIn);
}
if (Value != ValueIn) {
return -1;
}
TempAddr += sizeof(u32);
}
return 0;
}

91
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@ -0,0 +1,91 @@
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmemend.h
*
* This file contains utility functions to teach endian related memory
* IO functions.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00 hbm 08/05/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTIO_H /* prevent circular inclusions */
#define XIL_TESTIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define XIL_TESTIO_DEFAULT 0
#define XIL_TESTIO_LE 1
#define XIL_TESTIO_BE 2
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

882
lib/bsp/standalone/src/common/xil_testmem.c Normal file
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@ -0,0 +1,882 @@
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmem.c
*
* Contains the memory test utility functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xil_testmem.h"
#include "xil_io.h"
#include "xil_assert.h"
/************************** Constant Definitions ****************************/
/************************** Function Prototypes *****************************/
static u32 RotateLeft(u32 Input, u8 Width);
/* define ROTATE_RIGHT to give access to this functionality */
/* #define ROTATE_RIGHT */
#ifdef ROTATE_RIGHT
static u32 RotateRight(u32 Input, u8 Width);
#endif /* ROTATE_RIGHT */
/*****************************************************************************/
/**
*
* Perform a destructive 32-bit wide memory test.
*
* @param Addr is a pointer to the region of memory to be tested.
* @param Words is the length of the block.
* @param Pattern is the constant used for the constant pattern test, if 0,
* 0xDEADBEEF is used.
* @param Subtest is the test selected. See xil_testmem.h for possible
* values.
*
* @return
*
* - 0 is returned for a pass
* - -1 is returned for a failure
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** Width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundry of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
*****************************************************************************/
s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
{
u32 I;
u32 j;
u32 Val;
u32 FirtVal;
u32 WordMem32;
s32 Status = 0;
Xil_AssertNonvoid(Words != (u32)0);
Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
Xil_AssertNonvoid(Addr != NULL);
/*
* variable initialization
*/
Val = XIL_TESTMEM_INIT_VALUE;
FirtVal = XIL_TESTMEM_INIT_VALUE;
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
/*
* Fill the memory with incrementing
* values starting from 'FirtVal'
*/
for (I = 0U; I < Words; I++) {
*(Addr+I) = Val;
Val++;
}
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = FirtVal;
/*
* Check every word within the words
* of tested memory and compare it
* with the incrementing reference
* Val
*/
for (I = 0U; I < Words; I++) {
WordMem32 = *(Addr+I);
if (WordMem32 != Val) {
Status = -1;
goto End_Label;
}
Val++;
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
/*
* set up to cycle through all possible initial
* test Patterns for walking ones test
*/
for (j = 0U; j < (u32)32; j++) {
/*
* Generate an initial value for walking ones test
* to test for bad data bits
*/
Val = (1U << j);
/*
* START walking ones test
* Write a one to each data bit indifferent locations
*/
for (I = 0U; I < (u32)32; I++) {
/* write memory location */
*(Addr+I) = Val;
Val = (u32) RotateLeft(Val, 32U);
}
/*
* Restore the reference 'val' to the
* initial value
*/
Val = 1U << j;
/* Read the values from each location that was
* written */
for (I = 0U; I < (u32)32; I++) {
/* read memory location */
WordMem32 = *(Addr+I);
if (WordMem32 != Val) {
Status = -1;
goto End_Label;
}
Val = (u32)RotateLeft(Val, 32U);
}
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
/*
* set up to cycle through all possible
* initial test Patterns for walking zeros test
*/
for (j = 0U; j < (u32)32; j++) {
/*
* Generate an initial value for walking ones test
* to test for bad data bits
*/
Val = ~(1U << j);
/*
* START walking zeros test
* Write a one to each data bit indifferent locations
*/
for (I = 0U; I < (u32)32; I++) {
/* write memory location */
*(Addr+I) = Val;
Val = ~((u32)RotateLeft(~Val, 32U));
}
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = ~(1U << j);
/* Read the values from each location that was
* written */
for (I = 0U; I < (u32)32; I++) {
/* read memory location */
WordMem32 = *(Addr+I);
if (WordMem32 != Val) {
Status = -1;
goto End_Label;
}
Val = ~((u32)RotateLeft(~Val, 32U));
}
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
/* Fill the memory with inverse of address */
for (I = 0U; I < Words; I++) {
/* write memory location */
Val = (u32) (~((INTPTR) (&Addr[I])));
*(Addr+I) = Val;
}
/*
* Check every word within the words
* of tested memory
*/
for (I = 0U; I < Words; I++) {
/* Read the location */
WordMem32 = *(Addr+I);
Val = (u32) (~((INTPTR) (&Addr[I])));
if ((WordMem32 ^ Val) != 0x00000000U) {
Status = -1;
goto End_Label;
}
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
/*
* Generate an initial value for
* memory testing
*/
if (Pattern == (u32)0) {
Val = 0xDEADBEEFU;
}
else {
Val = Pattern;
}
/*
* Fill the memory with fixed Pattern
*/
for (I = 0U; I < Words; I++) {
/* write memory location */
*(Addr+I) = Val;
}
/*
* Check every word within the words
* of tested memory and compare it
* with the fixed Pattern
*/
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem32 = *(Addr+I);
if (WordMem32 != Val) {
Status = -1;
goto End_Label;
}
}
}
End_Label:
return Status;
}
/*****************************************************************************/
/**
*
* Perform a destructive 16-bit wide memory test.
*
* @param Addr is a pointer to the region of memory to be tested.
* @param Words is the length of the block.
* @param Pattern is the constant used for the constant Pattern test, if 0,
* 0xDEADBEEF is used.
* @param Subtest is the test selected. See xil_testmem.h for possible
* values.
*
* @return
*
* - -1 is returned for a failure
* - 0 is returned for a pass
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** Width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundry of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
*****************************************************************************/
s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
{
u32 I;
u32 j;
u16 Val;
u16 FirtVal;
u16 WordMem16;
s32 Status = 0;
Xil_AssertNonvoid(Words != (u32)0);
Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
Xil_AssertNonvoid(Addr != NULL);
/*
* variable initialization
*/
Val = XIL_TESTMEM_INIT_VALUE;
FirtVal = XIL_TESTMEM_INIT_VALUE;
/*
* selectthe proper Subtest(s)
*/
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
/*
* Fill the memory with incrementing
* values starting from 'FirtVal'
*/
for (I = 0U; I < Words; I++) {
/* write memory location */
*(Addr+I) = Val;
Val++;
}
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = FirtVal;
/*
* Check every word within the words
* of tested memory and compare it
* with the incrementing reference val
*/
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem16 = *(Addr+I);
if (WordMem16 != Val) {
Status = -1;
goto End_Label;
}
Val++;
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
/*
* set up to cycle through all possible initial test
* Patterns for walking ones test
*/
for (j = 0U; j < (u32)16; j++) {
/*
* Generate an initial value for walking ones test
* to test for bad data bits
*/
Val = (u16)((u32)1 << j);
/*
* START walking ones test
* Write a one to each data bit indifferent locations
*/
for (I = 0U; I < (u32)16; I++) {
/* write memory location */
*(Addr+I) = Val;
Val = (u16)RotateLeft(Val, 16U);
}
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = (u16)((u32)1 << j);
/* Read the values from each location that was written */
for (I = 0U; I < (u32)16; I++) {
/* read memory location */
WordMem16 = *(Addr+I);
if (WordMem16 != Val) {
Status = -1;
goto End_Label;
}
Val = (u16)RotateLeft(Val, 16U);
}
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
/*
* set up to cycle through all possible initial
* test Patterns for walking zeros test
*/
for (j = 0U; j < (u32)16; j++) {
/*
* Generate an initial value for walking ones
* test to test for bad
* data bits
*/
Val = ~(1U << j);
/*
* START walking zeros test
* Write a one to each data bit indifferent locations
*/
for (I = 0U; I < (u32)16; I++) {
/* write memory location */
*(Addr+I) = Val;
Val = ~((u16)RotateLeft(~Val, 16U));
}
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = ~(1U << j);
/* Read the values from each location that was written */
for (I = 0U; I < (u32)16; I++) {
/* read memory location */
WordMem16 = *(Addr+I);
if (WordMem16 != Val) {
Status = -1;
goto End_Label;
}
Val = ~((u16)RotateLeft(~Val, 16U));
}
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
/* Fill the memory with inverse of address */
for (I = 0U; I < Words; I++) {
/* write memory location */
Val = (u16) (~((INTPTR)(&Addr[I])));
*(Addr+I) = Val;
}
/*
* Check every word within the words
* of tested memory
*/
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem16 = *(Addr+I);
Val = (u16) (~((INTPTR) (&Addr[I])));
if ((WordMem16 ^ Val) != 0x0000U) {
Status = -1;
goto End_Label;
}
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
/*
* Generate an initial value for
* memory testing
*/
if (Pattern == (u16)0) {
Val = 0xDEADU;
}
else {
Val = Pattern;
}
/*
* Fill the memory with fixed pattern
*/
for (I = 0U; I < Words; I++) {
/* write memory location */
*(Addr+I) = Val;
}
/*
* Check every word within the words
* of tested memory and compare it
* with the fixed pattern
*/
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem16 = *(Addr+I);
if (WordMem16 != Val) {
Status = -1;
goto End_Label;
}
}
}
End_Label:
return Status;
}
/*****************************************************************************/
/**
*
* Perform a destructive 8-bit wide memory test.
*
* @param Addr is a pointer to the region of memory to be tested.
* @param Words is the length of the block.
* @param Pattern is the constant used for the constant pattern test, if 0,
* 0xDEADBEEF is used.
* @param Subtest is the test selected. See xil_testmem.h for possible
* values.
*
* @return
*
* - -1 is returned for a failure
* - 0 is returned for a pass
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** Width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundry of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
*****************************************************************************/
s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
{
u32 I;
u32 j;
u8 Val;
u8 FirtVal;
u8 WordMem8;
s32 Status = 0;
Xil_AssertNonvoid(Words != (u32)0);
Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
Xil_AssertNonvoid(Addr != NULL);
/*
* variable initialization
*/
Val = XIL_TESTMEM_INIT_VALUE;
FirtVal = XIL_TESTMEM_INIT_VALUE;
/*
* select the proper Subtest(s)
*/
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
/*
* Fill the memory with incrementing
* values starting from 'FirtVal'
*/
for (I = 0U; I < Words; I++) {
/* write memory location */
*(Addr+I) = Val;
Val++;
}
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = FirtVal;
/*
* Check every word within the words
* of tested memory and compare it
* with the incrementing reference
* Val
*/
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem8 = *(Addr+I);
if (WordMem8 != Val) {
Status = -1;
goto End_Label;
}
Val++;
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
/*
* set up to cycle through all possible initial
* test Patterns for walking ones test
*/
for (j = 0U; j < (u32)8; j++) {
/*
* Generate an initial value for walking ones test
* to test for bad data bits
*/
Val = (u8)((u32)1 << j);
/*
* START walking ones test
* Write a one to each data bit indifferent locations
*/
for (I = 0U; I < (u32)8; I++) {
/* write memory location */
*(Addr+I) = Val;
Val = (u8)RotateLeft(Val, 8U);
}
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = (u8)((u32)1 << j);
/* Read the values from each location that was written */
for (I = 0U; I < (u32)8; I++) {
/* read memory location */
WordMem8 = *(Addr+I);
if (WordMem8 != Val) {
Status = -1;
goto End_Label;
}
Val = (u8)RotateLeft(Val, 8U);
}
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
/*
* set up to cycle through all possible initial test
* Patterns for walking zeros test
*/
for (j = 0U; j < (u32)8; j++) {
/*
* Generate an initial value for walking ones test to test
* for bad data bits
*/
Val = ~(1U << j);
/*
* START walking zeros test
* Write a one to each data bit indifferent locations
*/
for (I = 0U; I < (u32)8; I++) {
/* write memory location */
*(Addr+I) = Val;
Val = ~((u8)RotateLeft(~Val, 8U));
}
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = ~(1U << j);
/* Read the values from each location that was written */
for (I = 0U; I < (u32)8; I++) {
/* read memory location */
WordMem8 = *(Addr+I);
if (WordMem8 != Val) {
Status = -1;
goto End_Label;
}
Val = ~((u8)RotateLeft(~Val, 8U));
}
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
/* Fill the memory with inverse of address */
for (I = 0U; I < Words; I++) {
/* write memory location */
Val = (u8) (~((INTPTR) (&Addr[I])));
*(Addr+I) = Val;
}
/*
* Check every word within the words
* of tested memory
*/
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem8 = *(Addr+I);
Val = (u8) (~((INTPTR) (&Addr[I])));
if ((WordMem8 ^ Val) != 0x00U) {
Status = -1;
goto End_Label;
}
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
/*
* Generate an initial value for
* memory testing
*/
if (Pattern == (u8)0) {
Val = 0xA5U;
}
else {
Val = Pattern;
}
/*
* Fill the memory with fixed Pattern
*/
for (I = 0U; I < Words; I++) {
/* write memory location */
*(Addr+I) = Val;
}
/*
* Check every word within the words
* of tested memory and compare it
* with the fixed Pattern
*/
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem8 = *(Addr+I);
if (WordMem8 != Val) {
Status = -1;
goto End_Label;
}
}
}
End_Label:
return Status;
}
/*****************************************************************************/
/**
*
* Rotates the provided value to the left one bit position
*
* @param Input is value to be rotated to the left
* @param Width is the number of bits in the input data
*
* @return
*
* The resulting unsigned long value of the rotate left
*
* @note
*
* None.
*
*****************************************************************************/
static u32 RotateLeft(u32 Input, u8 Width)
{
u32 Msb;
u32 ReturnVal;
u32 WidthMask;
u32 MsbMask;
u32 LocalInput = Input;
/*
* set up the WidthMask and the MsbMask
*/
MsbMask = 1U << (Width - 1U);
WidthMask = (MsbMask << (u32)1) - (u32)1;
/*
* set the Width of the Input to the correct width
*/
LocalInput = LocalInput & WidthMask;
Msb = LocalInput & MsbMask;
ReturnVal = LocalInput << 1U;
if (Msb != 0x00000000U) {
ReturnVal = ReturnVal | (u32)0x00000001;
}
ReturnVal = ReturnVal & WidthMask;
return ReturnVal;
}
#ifdef ROTATE_RIGHT
/*****************************************************************************/
/**
*
* Rotates the provided value to the right one bit position
*
* @param Input is value to be rotated to the right
* @param Width is the number of bits in the input data
*
* @return
*
* The resulting u32 value of the rotate right
*
* @note
*
* None.
*
*****************************************************************************/
static u32 RotateRight(u32 Input, u8 Width)
{
u32 Lsb;
u32 ReturnVal;
u32 WidthMask;
u32 MsbMask;
u32 LocalInput = Input;
/*
* set up the WidthMask and the MsbMask
*/
MsbMask = 1U << (Width - 1U);
WidthMask = (MsbMask << 1U) - 1U;
/*
* set the width of the input to the correct width
*/
LocalInput = LocalInput & WidthMask;
ReturnVal = LocalInput >> 1U;
Lsb = LocalInput & 0x00000001U;
if (Lsb != 0x00000000U) {
ReturnVal = ReturnVal | MsbMask;
}
ReturnVal = ReturnVal & WidthMask;
return ReturnVal;
}
#endif /* ROTATE_RIGHT */

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmem.h
*
* This file contains utility functions to test memory.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* Subtest descriptions:
* <pre>
* XIL_TESTMEM_ALLMEMTESTS:
* Runs all of the following tests
*
* XIL_TESTMEM_INCREMENT:
* Incrementing Value Test.
* This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
* incrementing value as the test value for memory.
*
* XIL_TESTMEM_WALKONES:
* Walking Ones Test.
* This test uses a walking '1' as the test value for memory.
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
*
* XIL_TESTMEM_WALKZEROS:
* Walking Zero's Test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*
* XIL_TESTMEM_INVERSEADDR:
* Inverse Address Test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* XIL_TESTMEM_FIXEDPATTERN:
* Fixed Pattern Test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
* </pre>
*
* <i>WARNING</i>
*
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
*
* The address provided to the memory tests is not checked for
* validity except for the NULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundry of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
#define XIL_TESTMEM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* xutil_memtest defines */
#define XIL_TESTMEM_INIT_VALUE 1U
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XIL_TESTMEM_ALLMEMTESTS 0x00U
#define XIL_TESTMEM_INCREMENT 0x01U
#define XIL_TESTMEM_WALKONES 0x02U
#define XIL_TESTMEM_WALKZEROS 0x03U
#define XIL_TESTMEM_INVERSEADDR 0x04U
#define XIL_TESTMEM_FIXEDPATTERN 0x05U
#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* xutil_testmem prototypes */
extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_types.h
*
* This file contains basic types for Xilinx software IP.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
* Define LONG and ULONG datatypes and mask values
* </pre>
*
******************************************************************************/
#ifndef XIL_TYPES_H /* prevent circular inclusions */
#define XIL_TYPES_H /* by using protection macros */
#include <stdint.h>
#include <stddef.h>
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XBASIC_TYPES_H
/**
* guarded against xbasic_types.h.
*/
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
#define __XUINT64__
typedef struct
{
u32 Upper;
u32 Lower;
} Xuint64;
/*****************************************************************************/
/**
* Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#endif /* XBASIC_TYPES_H */
/**
* xbasic_types.h does not typedef s* or u64
*/
typedef char char8;
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef int64_t s64;
typedef uint64_t u64;
typedef int sint32;
typedef intptr_t INTPTR;
typedef uintptr_t UINTPTR;
typedef ptrdiff_t PTRDIFF;
#if !defined(LONG) || !defined(ULONG)
typedef long LONG;
typedef unsigned long ULONG;
#endif
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
#else
#include <linux/types.h>
#endif
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/**
* This data type defines an exception handler for a processor.
* The argument points to the instance of the component
*/
typedef void (*XExceptionHandler) (void *InstancePtr);
/*@}*/
/************************** Constant Definitions *****************************/
#ifndef TRUE
#define TRUE 1U
#endif
#ifndef FALSE
#define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xplatform_info.c
*
* This file contains information about hardware for which the code is built
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.00 pkp 12/15/14 Initial release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* This API is used to provide information about platform
*
* @param None.
*
* @return The information about platform defined in xplatform_info.h
*
* @note None.
*
******************************************************************************/
u32 XGetPlatform_Info()
{
u32 reg;
#if defined (ARMR5) || (__aarch64__)
return XPLAT_ZYNQ_ULTRA_MP;
#elif (__microblaze__)
return XPLAT_MICROBLAZE;
#else
return XPLAT_ZYNQ;
#endif
}
/*****************************************************************************/
/**
*
* This API is used to provide information about zynq ultrascale MP platform
*
* @param None.
*
* @return The information about zynq ultrascale MP platform defined in
* xplatform_info.h
*
* @note None.
*
******************************************************************************/
#if defined (ARMR5) || (__aarch64__)
u32 XGet_Zynq_UltraMp_Platform_info()
{
u32 reg;
reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
return reg;
}
#endif

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xplatform_info.h
*
* This file contains definitions for various platforms available
*
******************************************************************************/
#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
#define XPLATFORM_INFO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define XPAR_CSU_BASEADDR 0xFFCA0000U
#define XPAR_CSU_VER_OFFSET 0x00000044U
#define XPLAT_ZYNQ_ULTRA_MP 0x1
#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
#define XPLAT_ZYNQ 0x4
#define XPLAT_MICROBLAZE 0x5
#define XPLAT_INFO_MASK (0xF)
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
u32 XGetPlatform_Info();
#if defined (ARMR5) || (__aarch64__)
u32 XGet_Zynq_UltraMp_Platform_info();
#endif
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

430
lib/bsp/standalone/src/common/xstatus.h Normal file
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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xstatus.h
*
* This file contains Xilinx software status codes. Status codes have their
* own data type called int. These codes are used throughout the Xilinx
* device drivers.
*
******************************************************************************/
#ifndef XSTATUS_H /* prevent circular inclusions */
#define XSTATUS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/*********************** Common statuses 0 - 500 *****************************/
#define XST_SUCCESS 0L
#define XST_FAILURE 1L
#define XST_DEVICE_NOT_FOUND 2L
#define XST_DEVICE_BLOCK_NOT_FOUND 3L
#define XST_INVALID_VERSION 4L
#define XST_DEVICE_IS_STARTED 5L
#define XST_DEVICE_IS_STOPPED 6L
#define XST_FIFO_ERROR 7L /* an error occurred during an
operation with a FIFO such as
an underrun or overrun, this
error requires the device to
be reset */
#define XST_RESET_ERROR 8L /* an error occurred which requires
the device to be reset */
#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
typically requires the device
using the DMA to be reset */
#define XST_NOT_POLLED 10L /* the device is not configured for
polled mode operation */
#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
the specified data into */
#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
to hold the expected data */
#define XST_NO_DATA 13L /* there was no data available */
#define XST_REGISTER_ERROR 14L /* a register did not contain the
expected value */
#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
into the function */
#define XST_NOT_SGDMA 16L /* the device is not configured for
scatter-gather DMA operation */
#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
#define XST_NO_CALLBACK 18L /* a callback has not yet been
registered */
#define XST_NO_FEATURE 19L /* device is not configured with
the requested feature */
#define XST_NOT_INTERRUPT 20L /* device is not configured for
interrupt mode operation */
#define XST_DEVICE_BUSY 21L /* device is busy */
#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
have maxed out */
#define XST_IS_STARTED 23L /* used when part of device is
already started i.e.
sub channel */
#define XST_IS_STOPPED 24L /* used when part of device is
already stopped i.e.
sub channel */
#define XST_DATA_LOST 26L /* driver defined error */
#define XST_RECV_ERROR 27L /* generic receive error */
#define XST_SEND_ERROR 28L /* generic transmit error */
#define XST_NOT_ENABLED 29L /* a requested service is not
available because it has not
been enabled */
/***************** Utility Component statuses 401 - 500 *********************/
#define XST_MEMTEST_FAILED 401L /* memory test failed */
/***************** Common Components statuses 501 - 1000 *********************/
/********************* Packet Fifo statuses 501 - 510 ************************/
#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
was invalid after reset */
#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
* empty and full simultaneously
*/
/************************** DMA statuses 511 - 530 ***************************/
#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
failed */
#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
was invalid after reset */
#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
no buffer descriptors ready
to be processed */
#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
the scatter gather list are
being used */
#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
descriptor which is to be
copied over in the scatter
list is locked */
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
put into the scatter gather
list to be commited */
#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
specified was larger than the
total # of buffer descriptors
in the scatter gather list */
#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
already been created */
#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
been created */
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
being started was not committed
to the list */
#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
has already been used by the
hardware so it can't be reused
*/
#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
error */
#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
error */
/************************** IPIF statuses 531 - 550 ***************************/
#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
was passed into the function */
#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
reset was not valid */
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
status register did not read
back correctly */
#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
register did not reset when
acked */
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
register was not updated when
other registers changed */
#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
status register did not read
back correctly */
#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
did not reset when acked */
#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
not updated correctly when other
registers changed */
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
register did not indicate the
expected value */
#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
did not indicate the expected
value */
#define XST_IPIF_ERROR 541L /* generic ipif error */
/****************** Device specific statuses 1001 - 4095 *********************/
/********************* Ethernet statuses 1001 - 1050 *************************/
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
* to hold the minimum number of
* buffers or descriptors */
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
* collision on polled send */
/*********************** UART statuses 1051 - 1075 ***************************/
#define XST_UART
#define XST_UART_INIT_ERROR 1051L
#define XST_UART_START_ERROR 1052L
#define XST_UART_CONFIG_ERROR 1053L
#define XST_UART_TEST_FAIL 1054L
#define XST_UART_BAUD_ERROR 1055L
#define XST_UART_BAUD_RANGE 1056L
/************************ IIC statuses 1076 - 1100 ***************************/
#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
/* general call address */
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
/* value after reset not valid */
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
/* value after reset not valid */
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
/* value after reset not valid */
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
/* value after reset not valid */
#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
/* didn't return value written */
#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
/* didn't return value written */
#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
/* didn't return written value */
#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
/*********************** ATMC statuses 1101 - 1125 ***************************/
#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
controller hit the max value
which requires the statistics
to be cleared */
/*********************** Flash statuses 1126 - 1150 **************************/
#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
*/
#define XST_FLASH_READY 1127L /* Flash is ready for commands */
#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
error. Use XFlash_DeviceControl
to retrieve device specific codes
*/
#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
*/
#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
*/
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
driver */
#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
aborted due to a timeout */
#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
addressible range */
#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
write/erase function with
XFL_NON_BLOCKING_WRITE/ERASE
option cleared */
#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
/*********************** SPI statuses 1151 - 1175 ****************************/
#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
* selected */
#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
*/
#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
* one master assigned to two or more
* priorities, or one master not
* assigned to any priority
*/
#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
* priority levels without first
* suspending the use of priority
* levels
*/
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
* bus parking was not enabled
*/
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
* priority mode to allow the
* priorities to be changed
*/
/************************ Intc statuses 1201 - 1225 **************************/
#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
/********************** TmrCtr statuses 1226 - 1250 **************************/
#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
/********************** WdtTb statuses 1251 - 1275 ***************************/
#define XST_WDTTB_TIMER_FAILED 1251L
/********************** PlbArb statuses 1276 - 1300 **************************/
#define XST_PLBARB_FAIL_SELFTEST 1276L
/********************** Plb2Opb statuses 1301 - 1325 *************************/
#define XST_PLB2OPB_FAIL_SELFTEST 1301L
/********************** Opb2Plb statuses 1326 - 1350 *************************/
#define XST_OPB2PLB_FAIL_SELFTEST 1326L
/********************** SysAce statuses 1351 - 1360 **************************/
#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
/********************** PCI Bridge statuses 1361 - 1375 **********************/
#define XST_PCI_INVALID_ADDRESS 1361L
/********************** FlexRay constants 1400 - 1409 *************************/
#define XST_FR_TX_ERROR 1400
#define XST_FR_TX_BUSY 1401
#define XST_FR_BUF_LOCKED 1402
#define XST_FR_NO_BUF 1403
/****************** USB constants 1410 - 1420 *******************************/
#define XST_USB_ALREADY_CONFIGURED 1410
#define XST_USB_BUF_ALIGN_ERROR 1411
#define XST_USB_NO_DESC_AVAILABLE 1412
#define XST_USB_BUF_TOO_BIG 1413
#define XST_USB_NO_BUF 1414
/****************** HWICAP constants 1421 - 1429 *****************************/
#define XST_HWICAP_WRITE_DONE 1421
/****************** AXI VDMA constants 1430 - 1440 *****************************/
#define XST_VDMA_MISMATCH_ERROR 1430
/*********************** NAND Flash statuses 1441 - 1459 *********************/
#define XST_NAND_BUSY 1441L /* Flash is erasing or
* programming
*/
#define XST_NAND_READY 1442L /* Flash is ready for commands
*/
#define XST_NAND_ERROR 1443L /* Flash had detected an
* internal error.
*/
#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
* driver
*/
#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
*/
#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
* operation aborted due to a
* timeout
*/
#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
* addressible range
*/
#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
*/
#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
* page of the device
*/
#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
*/
#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
*/
/**************************** Type Definitions *******************************/
typedef s32 XStatus;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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###############################################################################
#
# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
include config.make
AS=aarch64-none-elf-as
CC=aarch64-none-elf-gcc
AR=aarch64-none-elf-ar
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
LIB=libxil.a
CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
#The following flags are required for PEEP. We can remove them later
ECC_FLAGS += -march=armv8-a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
INCLUDEFILES=*.h
libs: $(LIBS)
standalone_libs: $(LIBSOURCES)
echo "Compiling standalone A53"
$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
.PHONY: include
include: standalone_includes
standalone_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OUTS}
$(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <unistd.h>
#include "xil_types.h"
/* _exit - Simple implementation. Does not return.
*/
__attribute__((weak)) void _exit (sint32 status)
{
(void)status;
while (1)
{
__asm__("wfi");
}
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <errno.h>
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
}
#endif
/*
* _open -- open a file descriptor. We don't have a filesystem, so
* we return an error.
*/
__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
{
(void *)buf;
(void)flags;
(void)mode;
errno = EIO;
return (-1);
}

70
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <sys/types.h>
#include "xil_types.h"
extern u8 _heap_start[];
extern u8 _heap_end[];
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) caddr_t _sbrk ( s32 incr );
}
#endif
__attribute__((weak)) caddr_t _sbrk ( s32 incr )
{
static u8 *heap = NULL;
u8 *prev_heap;
static u8 *HeapEndPtr = (u8 *)&_heap_end;
caddr_t Status;
if (heap == NULL) {
heap = (u8 *)&_heap_start;
}
prev_heap = heap;
heap += incr;
if (heap > HeapEndPtr){
Status = (caddr_t) -1;
}
else if (prev_heap != NULL) {
Status = (caddr_t) ((void *)prev_heap);
}
else {
Status = (caddr_t) -1;
}
return Status;
}

42
lib/bsp/standalone/src/cortexa53/gcc/abort.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <stdlib.h>
#include <unistd.h>
/*
* abort -- go out via exit...
*/
__attribute__((weak)) void abort(void)
{
_exit(1);
}

208
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file asm_vectors.s
*
* This file contains the initial vector table for the Cortex A53 processor
* Currently NEON registers are not saved on stack if interrupt is taken.
* It will be implemented.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 5/21/14 Initial version
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
.org 0
.text
.globl _boot
.globl _vector_table
.globl FIQInterrupt
.globl IRQInterrupt
.globl SErrorInterrupt
.globl SynchronousInterrupt
.org 0
.section .vectors, "a"
_vector_table:
.set VBAR, _vector_table
.org VBAR
b _boot
.org (VBAR + 0x200)
b SynchronousInterruptHandler
.org (VBAR + 0x280)
b IRQInterruptHandler
.org (VBAR + 0x300)
b FIQInterruptHandler
.org (VBAR + 0x380)
b SErrorInterruptHandler
SynchronousInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl SynchronousInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
IRQInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl IRQInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
FIQInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl FIQInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
SErrorInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl SErrorInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
.end

265
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file boot.S
*
* This file contains the initial startup code for the Cortex A53 processor
* Currently the processor starts at EL3 and boot code, startup and main
* code will run on secure EL3.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 5/21/14 Initial version
*
* @note
*
* None.
*
******************************************************************************/
#include "xparameters.h"
.globl MMUTableL0
.globl MMUTableL1
.globl MMUTableL2
.global _prestart
.global _boot
.global __el3_stack
.global __el2_stack
.global __el1_stack
.global __el0_stack
.global _vector_table
.set EL3_stack, __el3_stack
.set EL2_stack, __el2_stack
.set EL1_stack, __el1_stack
.set EL0_stack, __el0_stack
.set TT_S1_FAULT, 0x0
.set TT_S1_TABLE, 0x3
.set L0Table, MMUTableL0
.set L1Table, MMUTableL1
.set L2Table, MMUTableL2
.set vector_base, _vector_table
.section .boot,"ax"
/* this initializes the various processor modes */
_prestart:
_boot:
mov x0, #0
mov x1, #0
mov x2, #0
mov x3, #0
mov x4, #0
mov x5, #0
mov x6, #0
mov x7, #0
mov x8, #0
mov x9, #0
mov x10, #0
mov x11, #0
mov x12, #0
mov x13, #0
mov x14, #0
mov x15, #0
mov x16, #0
mov x17, #0
mov x18, #0
mov x19, #0
mov x20, #0
mov x21, #0
mov x22, #0
mov x23, #0
mov x24, #0
mov x25, #0
mov x26, #0
mov x27, #0
mov x28, #0
mov x29, #0
mov x30, #0
#if 0 //dont put other a53 cpus in wfi
//Which core am I
// ----------------
mrs x0, MPIDR_EL1
and x0, x0, #0xFF //Mask off to leave Aff0
cbz x0, OKToRun //If core 0, run the primary init code
EndlessLoop0:
wfi
b EndlessLoop0
#endif
OKToRun:
/*Set vector table base address*/
ldr x1, =vector_base
msr VBAR_EL3,x1
/*Define stack pointer for current exception level*/
ldr x2,=EL3_stack
mov sp,x2
/* Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU*/
mov x0, #0 // Clear all trap bits
msr CPTR_EL3, x0
/* Configure SCR_EL3 */
mov w1, #0 //; Initial value of register is unknown
orr w1, w1, #(1 << 11) //; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
orr w1, w1, #(1 << 10) //; Set RW bit (EL1 is AArch64, as this is the Secure world)
orr w1, w1, #(1 << 3) //; Set EA bit (SError routed to EL3)
orr w1, w1, #(1 << 2) //; Set FIQ bit (FIQs routed to EL3)
orr w1, w1, #(1 << 1) //; Set IRQ bit (IRQs routed to EL3)
msr SCR_EL3, x1
/*Enable ECC protection*/
mrs x0, S3_1_C11_C0_2 // register L2CTLR_EL1
orr x0, x0, #(1<<22)
msr S3_1_C11_C0_2, x0
/*configure cpu auxiliary control register EL1 */
ldr x0,=0x80CA000 // L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
msr S3_1_C15_C2_0, x0 //CPUACTLR_EL1
/*Enable hardware coherency between cores*/
mrs x0, S3_1_c15_c2_1 //Read EL1 CPU Extended Control Register
orr x0, x0, #(1 << 6) //Set the SMPEN bit
msr S3_1_c15_c2_1, x0 //Write EL1 CPU Extended Control Register
isb
tlbi ALLE3
ic IALLU //; Invalidate I cache to PoU
bl invalidate_dcaches
dsb sy
isb
ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL1
msr TTBR0_EL3, x1 //; Set TTBR0_EL3 (NOTE: There is no TTBR1 at EL1)
/**********************************************
* Set up memory attributes
* This equates to:
* 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
* 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
* 2 = b00000000 = Device-nGnRnE
**********************************************/
ldr x1, =0x000000000000FF44
msr MAIR_EL3, x1
/**********************************************
* Set up TCR_EL3
* Physical Address Size PS = 010 -> 40bits 1TB
* Granual Size TG0 = 00 -> 4KB
* size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
***************************************************/
ldr x1,=0x80823518
msr TCR_EL3, x1
isb
/* Configure SCTLR_EL3 */
mov x1, #0 //Most of the SCTLR_EL3 bits are unknown at reset
orr x1, x1, #(1 << 12) //Enable I cache
orr x1, x1, #(1 << 3) //Enable SP alignment check
orr x1, x1, #(1 << 2) //Enable caches
orr x1, x1, #(1 << 0) //Enable MMU
msr SCTLR_EL3, x1
dsb sy
isb
bl _startup //jump to start
loop: b loop
invalidate_dcaches:
dmb ISH
mrs x0, CLIDR_EL1 //; x0 = CLIDR
ubfx w2, w0, #24, #3 //; w2 = CLIDR.LoC
cmp w2, #0 //; LoC is 0?
b.eq invalidateCaches_end //; No cleaning required and enable MMU
mov w1, #0 //; w1 = level iterator
invalidateCaches_flush_level:
add w3, w1, w1, lsl #1 //; w3 = w1 * 3 (right-shift for cache type)
lsr w3, w0, w3 //; w3 = w0 >> w3
ubfx w3, w3, #0, #3 //; w3 = cache type of this level
cmp w3, #2 //; No cache at this level?
b.lt invalidateCaches_next_level
lsl w4, w1, #1
msr CSSELR_EL1, x4 //; Select current cache level in CSSELR
isb //; ISB required to reflect new CSIDR
mrs x4, CCSIDR_EL1 //; w4 = CSIDR
ubfx w3, w4, #0, #3
add w3, w3, #2 //; w3 = log2(line size)
ubfx w5, w4, #13, #15
ubfx w4, w4, #3, #10 //; w4 = Way number
clz w6, w4 //; w6 = 32 - log2(number of ways)
invalidateCaches_flush_set:
mov w8, w4 //; w8 = Way number
invalidateCaches_flush_way:
lsl w7, w1, #1 //; Fill level field
lsl w9, w5, w3
orr w7, w7, w9 //; Fill index field
lsl w9, w8, w6
orr w7, w7, w9 //; Fill way field
dc CISW, x7 //; Invalidate by set/way to point of coherency
subs w8, w8, #1 //; Decrement way
b.ge invalidateCaches_flush_way
subs w5, w5, #1 //; Descrement set
b.ge invalidateCaches_flush_set
invalidateCaches_next_level:
add w1, w1, #1 //; Next level
cmp w2, w1
b.gt invalidateCaches_flush_level
invalidateCaches_end:
ret
.end

47
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 _close(s32 fd);
}
#endif
/*
* close -- We don't need to do anything, but pretend we did.
*/
__attribute__((weak)) s32 _close(s32 fd)
{
(void)fd;
return (0);
}

51
lib/bsp/standalone/src/cortexa53/gcc/errno.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/* The errno variable is stored in the reentrancy structure. This
function returns its address for use by the macro errno defined in
errno.h. */
#include <errno.h>
#include <reent.h>
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) sint32 * __errno (void);
}
#endif
__attribute__((weak)) sint32 *
__errno (void)
{
return &_REENT->_errno;
}

46
lib/bsp/standalone/src/cortexa53/gcc/fcntl.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <stdio.h>
#include "xil_types.h"
/*
* fcntl -- Manipulate a file descriptor.
* We don't have a filesystem, so we do nothing.
*/
__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg)
{
(void)fd;
(void)cmd;
(void)arg;
return 0;
}

50
lib/bsp/standalone/src/cortexa53/gcc/fstat.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <sys/stat.h>
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
}
#endif
/*
* fstat -- Since we have no file system, we just return an error.
*/
__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
{
(void)fd;
buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
return (0);
}

51
lib/bsp/standalone/src/cortexa53/gcc/getpid.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "xil_types.h"
/*
* getpid -- only one process, so just return 1.
*/
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 _getpid(void);
}
#endif
__attribute__((weak)) s32 getpid(void)
{
return 1;
}
__attribute__((weak)) s32 _getpid(void)
{
return 1;
}

52
lib/bsp/standalone/src/cortexa53/gcc/initialise_monitor_handles.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file initialise_monitor_handles.c
*
* Contains blank function to avoid compilation error
*
* @note
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
******************************************************************************/
__attribute__((weak)) void initialise_monitor_handles(){
}

56
lib/bsp/standalone/src/cortexa53/gcc/isatty.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <unistd.h>
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) sint32 _isatty(sint32 fd);
}
#endif
/*
* isatty -- returns 1 if connected to a terminal device,
* returns 0 if not. Since we're hooked up to a
* serial port, we'll say yes _AND return a 1.
*/
__attribute__((weak)) sint32 isatty(sint32 fd)
{
(void)fd;
return (1);
}
__attribute__((weak)) sint32 _isatty(sint32 fd)
{
(void)fd;
return (1);
}

60
lib/bsp/standalone/src/cortexa53/gcc/kill.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <signal.h>
#include <unistd.h>
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 _kill(s32 pid, s32 sig);
}
#endif
/*
* kill -- go out via exit...
*/
__attribute__((weak)) s32 kill(s32 pid, s32 sig)
{
if(pid == 1) {
_exit(sig);
}
return 0;
}
__attribute__((weak)) s32 _kill(s32 pid, s32 sig)
{
if(pid == 1) {
_exit(sig);
}
return 0;
}

61
lib/bsp/standalone/src/cortexa53/gcc/lseek.c Normal file
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@ -0,0 +1,61 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <sys/types.h>
#include <errno.h>
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
}
#endif
/*
* lseek -- Since a serial port is non-seekable, we return an error.
*/
__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
{
(void)fd;
(void)offset;
(void)whence;
errno = ESPIPE;
return ((off_t)-1);
}
__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
{
(void)fd;
(void)offset;
(void)whence;
errno = ESPIPE;
return ((off_t)-1);
}

52
lib/bsp/standalone/src/cortexa53/gcc/open.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <errno.h>
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode);
}
#endif
/*
* open -- open a file descriptor. We don't have a filesystem, so
* we return an error.
*/
__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode)
{
(void *)buf;
(void)flags;
(void)mode;
errno = EIO;
return (-1);
}

111
lib/bsp/standalone/src/cortexa53/gcc/read.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/* read.c -- read bytes from a input device.
*/
#include "xparameters.h"
#include "xil_printf.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
}
#endif
/*
* read -- read bytes from the serial port. Ignore fd, since
* we only have stdin.
*/
__attribute__((weak)) s32
read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
s32 i;
char8* LocalBuf = buf;
(void)fd;
for (i = 0; i < nbytes; i++) {
if(LocalBuf != NULL) {
LocalBuf += i;
}
if(LocalBuf != NULL) {
*LocalBuf = inbyte();
if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
break;
}
}
if(LocalBuf != NULL) {
LocalBuf -= i;
}
}
return (i + 1);
#else
(void)fd;
(void)buf;
(void)nbytes;
return 0;
#endif
}
__attribute__((weak)) s32
_read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
s32 i;
char8* LocalBuf = buf;
(void)fd;
for (i = 0; i < nbytes; i++) {
if(LocalBuf != NULL) {
LocalBuf += i;
}
if(LocalBuf != NULL) {
*LocalBuf = inbyte();
if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
break;
}
}
if(LocalBuf != NULL) {
LocalBuf -= i;
}
}
return (i + 1);
#else
(void)fd;
(void)buf;
(void)nbytes;
return 0;
#endif
}

65
lib/bsp/standalone/src/cortexa53/gcc/sbrk.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <errno.h>
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) char8 *sbrk (s32 nbytes);
}
#endif
extern u8 _heap_start[];
extern u8 _heap_end[];
extern char8 HeapBase[];
extern char8 HeapLimit[];
__attribute__((weak)) char8 *sbrk (s32 nbytes)
{
char8 *base;
static char8 *heap_ptr = HeapBase;
base = heap_ptr;
if(heap_ptr != NULL) {
heap_ptr += nbytes;
}
/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
return base;
} else {
errno = ENOMEM;
return ((char8 *)-1);
}
}

170
lib/bsp/standalone/src/cortexa53/gcc/translation_table.s Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file translation_table.s
*
* This file contains the initialization for the MMU table in RAM
* needed by the Cortex A53 processor
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/21/14 Initial version
*
*
* @note
*
* None.
*
******************************************************************************/
.globl MMUTableL0
.globl MMUTableL1
.globl MMUTableL2
.set reserved, 0x0 /* Fault*/
.set Memory, 0x405 | (3 << 8) | (0x0) /* normal writeback write allocate inner shared read write */
.set Device, 0x409 | (1 << 53)| (1 << 54) |(0x0) /* strongly ordered read write non executable*/
.section .mmu_tbl0,"a"
MMUTableL0:
.set SECT, MMUTableL1
.8byte SECT + 0x3
.set SECT, MMUTableL1+0x1000
.8byte SECT + 0x3
.section .mmu_tbl1,"a"
MMUTableL1:
.set SECT, MMUTableL2 /*1GB DDR*/
.8byte SECT + 0x3
.rept 0x3 /*1GB DDR, 1GB PL, 2GB other devices n memory*/
.set SECT, SECT + 0x1000
.8byte SECT + 0x3
.endr
.set SECT,0x100000000
.rept 0xC
.8byte SECT + reserved
.set SECT, SECT + 0x40000000 /*12GB Reserved*/
.endr
.rept 0x10
.8byte SECT + Device
.set SECT, SECT + 0x40000000 /*8GB PL, 8GB PCIe*/
.endr
.rept 0x20
.8byte SECT + Memory
.set SECT, SECT + 0x40000000 /*32GB DDR*/
.endr
.rept 0xC0
.8byte SECT + Device
.set SECT, SECT + 0x40000000 /*192GB PL*/
.endr
.rept 0x100
.8byte SECT + Device
.set SECT, SECT + 0x40000000 /*256GB PL/PCIe*/
.endr
.rept 0x200
.8byte SECT + Device
.set SECT, SECT + 0x40000000 /*512GB PL/DDR*/
.endr
.section .mmu_tbl2,"a"
MMUTableL2:
.set SECT, 0
.rept 0x0400 /*2GB DDR */
.8byte SECT + Memory
.set SECT, SECT+0x200000
.endr
.rept 0x0200 /*1GB lower PL*/
.8byte SECT + Device
.set SECT, SECT+0x200000
.endr
.rept 0x0100 /*512MB QSPI*/
.8byte SECT + Device
.set SECT, SECT+0x200000
.endr
.rept 0x080 /*256MB lower PCIe*/
.8byte SECT + Device
.set SECT, SECT+0x200000
.endr
.rept 0x040 /*128MB Reserved*/
.8byte SECT + reserved
.set SECT, SECT+0x200000
.endr
.rept 0x8 /*16MB coresight*/
.8byte SECT + Device
.set SECT, SECT+0x200000
.endr
.rept 0x8 /*16MB RPU low latency port*/
.8byte SECT + Device
.set SECT, SECT+0x200000
.endr
.rept 0x022 /*68MB Device*/
.8byte SECT + Device
.set SECT, SECT+0x200000
.endr
.rept 0x8 /*8MB FPS*/
.8byte SECT + Device
.set SECT, SECT+0x200000
.endr
.rept 0x4 /*16MB LPS*/
.8byte SECT + Device
.set SECT, SECT+0x200000
.endr
.8byte SECT + Device /*2MB PMU/CSU */
.set SECT, SECT+0x200000
.8byte SECT + Memory /*2MB OCM/TCM*/
.end

50
lib/bsp/standalone/src/cortexa53/gcc/unlink.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include <errno.h>
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 unlink(char8 *path);
}
#endif
/*
* unlink -- since we have no file system,
* we just return an error.
*/
__attribute__((weak)) s32 unlink(char8 *path)
{
(void *)path;
errno = EIO;
return (-1);
}

111
lib/bsp/standalone/src/cortexa53/gcc/write.c Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/* write.c -- write bytes to an output device.
*/
#include "xparameters.h"
#include "xil_printf.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
}
#endif
/*
* write -- write bytes to the serial port. Ignore fd, since
* stdout and stderr are the same. Since we have no filesystem,
* open will only return an error.
*/
__attribute__((weak)) s32
write (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDOUT_BASEADDRESS
s32 i;
char8* LocalBuf = buf;
(void)fd;
for (i = 0; i < nbytes; i++) {
if(LocalBuf != NULL) {
LocalBuf += i;
}
if(LocalBuf != NULL) {
if (*LocalBuf == '\n') {
outbyte ('\r');
}
outbyte (*LocalBuf);
}
if(LocalBuf != NULL) {
LocalBuf -= i;
}
}
return (nbytes);
#else
(void)fd;
(void)buf;
(void)nbytes;
return 0;
#endif
}
__attribute__((weak)) s32
_write (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDOUT_BASEADDRESS
s32 i;
char8* LocalBuf = buf;
(void)fd;
for (i = 0; i < nbytes; i++) {
if(LocalBuf != NULL) {
LocalBuf += i;
}
if(LocalBuf != NULL) {
if (*LocalBuf == '\n') {
outbyte ('\r');
}
outbyte (*LocalBuf);
}
if(LocalBuf != NULL) {
LocalBuf -= i;
}
}
return (nbytes);
#else
(void)fd;
(void)buf;
(void)nbytes;
return 0;
#endif
}

118
lib/bsp/standalone/src/cortexa53/gcc/xil-crt0.S Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil-crt0.S
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/21/14 Initial version
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
.file "xil-crt0.S"
.section ".got2","aw"
.align 2
.text
.Lsbss_start:
.long __sbss_start
.Lsbss_end:
.long __sbss_end
.Lbss_start:
.long __bss_start__
.Lbss_end:
.long __bss_end__
.globl _startup
_startup:
mov x0, #0
/* clear sbss */
ldr w1,.Lsbss_start /* calculate beginning of the SBSS */
ldr w2,.Lsbss_end /* calculate end of the SBSS */
uxtw x1, w1 /*zero extension to w1 register*/
uxtw x2, w2 /*zero extension to w2 register*/
.Lloop_sbss:
cmp x1,x2
bge .Lenclsbss /* If no SBSS, no clearing required */
str x0, [x1], #8
b .Lloop_sbss
.Lenclsbss:
/* clear bss */
ldr w1,.Lbss_start /* calculate beginning of the BSS */
ldr w2,.Lbss_end /* calculate end of the BSS */
uxtw x1, w1 /*zero extension to w1 register*/
uxtw x2, w2 /*zero extension to w2 register*/
.Lloop_bss:
cmp x1,x2
bge .Lenclbss /* If no BSS, no clearing required */
str x0, [x1], #8
b .Lloop_bss
.Lenclbss:
bl Init_Uart /* Initialize UART */
/* make sure argc and argv are valid */
mov x0, #0
mov x1, #0
bl main /* Jump to main C code */
bl _exit
.Lexit: /* should never get here */
b .Lexit
.Lstart:
.size _startup,.Lstart-_startup

169
lib/bsp/standalone/src/cortexa53/gcc/xpseudo_asm_gcc.h Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpseudo_asm_gcc.h
*
* This header file contains macros for using inline assembler code. It is
* written specifically for the GNU compiler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/21/14 First release
* </pre>
*
******************************************************************************/
#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
#define XPSEUDO_ASM_GCC_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
/* pseudo assembler instructions */
#define mfcpsr() ({u32 rval; \
asm volatile("mrs %0, DAIF" : "=r" (rval));\
rval;\
})
#define mtcpsr(v) asm ("msr DAIF, %0" : : "r" (v))
#define cpsiei() //__asm__ __volatile__("cpsie i\n")
#define cpsidi() //__asm__ __volatile__("cpsid i\n")
#define cpsief() //__asm__ __volatile__("cpsie f\n")
#define cpsidf() //__asm__ __volatile__("cpsid f\n")
#define mtgpr(rn, v) /*__asm__ __volatile__(\
"mov r" stringify(rn) ", %0 \n"\
: : "r" (v)\
)*/
#define mfgpr(rn) /*({u32 rval; \
__asm__ __volatile__(\
"mov %0,r" stringify(rn) "\n"\
: "=r" (rval)\
);\
rval;\
})*/
/* memory synchronization operations */
/* Instruction Synchronization Barrier */
#define isb() asm ("isb sy")
/* Data Synchronization Barrier */
#define dsb() asm("dsb sy")
/* Data Memory Barrier */
#define dmb() asm("dmb sy")
/* Memory Operations */
#define ldr(adr) ({u32 rval; \
__asm__ __volatile__(\
"ldr %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#define ldrb(adr) ({u8 rval; \
__asm__ __volatile__(\
"ldrb %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#define str(adr, val) __asm__ __volatile__(\
"str %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
#define strb(adr, val) __asm__ __volatile__(\
"strb %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
/* Count leading zeroes (clz) */
#define clz(arg) ({u8 rval; \
__asm__ __volatile__(\
"clz %0,%1"\
: "=r" (rval) : "r" (arg)\
);\
rval;\
})
#define mtcpdc(reg,val) asm("dc " #reg ",%0" : : "r" (val))
#define mtcpic(reg,val) asm("ic " #reg ",%0" : : "r" (val))
#define mtcpicall(reg) asm("ic " #reg)
#define mtcptlbi(reg) asm("tlbi " #reg)
#define mtcpat(reg,val) asm("at " #reg ",%0" : : "r" (val))
/* CP15 operations */
#define mfcp(reg) ({u32 rval;\
asm("mrs %0, " #reg : "=r" (rval));\
rval;\
})
#define mtcp(reg,val) asm("msr " #reg ",%0" : : "r" (val))
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XPSEUDO_ASM_GCC_H */

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/* print.c -- print a string on the output device.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
*/
/*
* print -- do a raw print of a string
*/
#include "xil_printf.h"
void print(const char8 *ptr)
{
#ifdef STDOUT_BASEADDRESS
while (*ptr != (char8)0) {
outbyte (*ptr);
*ptr++;
}
#else
(void)ptr;
#endif
}

59
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/* putnum.c -- put a hex number on the output device.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* putnum -- print a 32 bit number in hex
*/
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Function Prototypes ******************************/
extern void print (const char8 *ptr);
void putnum(u32 num);
void putnum(u32 num)
{
char8 buf[9];
u32 cnt;
s32 i;
char8 *ptr;
u32 digit;
for(i = 0; i<9; i++) {
buf[i] = '0';
}
ptr = buf;
for (cnt = 7U ; cnt >= 0U ; cnt--) {
digit = ((num >> (cnt * 4U)) & 0x0000000FU);
if ((digit <= 9U) && (ptr != NULL)) {
digit += (u32)'0';
*ptr = ((char8) digit);
ptr += 1;
} else if (ptr != NULL) {
digit += ((u32)'a' - (u32)10);
*ptr = ((char8)digit);
ptr += 1;
} else {
/*Made for MisraC Compliance*/;
}
}
if(ptr != NULL) {
*ptr = (char8) 0;
}
print (buf);
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************
*
* @file sleep.c
*
* This function provides a second delay using the Global Timer register in
* the ARM Cortex A53 MP core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "sleep.h"
#include "xtime_l.h"
#include "xparameters.h"
/*****************************************************************************/
/*
*
* This API is used to provide delays in seconds
*
* @param seconds requested
*
* @return 0 always
*
* @note None.
*
****************************************************************************/
s32 sleep(u32 seconds)
{
XTime tEnd, tCur;
/*write 50MHz frequency to System Time Stamp Generator Register*/
Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),XIOU_SCNTRS_FREQ);
/*Enable the counter*/
Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),XIOU_SCNTRS_CNT_CNTRL_REG_EN);
XTime_GetTime(&tCur);
tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
do
{
XTime_GetTime(&tCur);
} while (tCur < tEnd);
/*Disable the counter*/
Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),(~(XIOU_SCNTRS_CNT_CNTRL_REG_EN)));
return 0;
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef SLEEP_H
#define SLEEP_H
#include "xil_types.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
s32 usleep(u32 useconds);
s32 sleep(u32 seconds);
#ifdef __cplusplus
}
#endif
#endif

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file uart.c
*
* This file contains APIs for configuring the UART.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "xparameters.h"
/* Register offsets */
#define UART_CR_OFFSET 0x00000000U
#define UART_MR_OFFSET 0x00000004U
#define UART_BAUDGEN_OFFSET 0x00000018U
#define UART_BAUDDIV_OFFSET 0x00000034U
#define MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
#define UART_BAUDRATE 115200U
#define CSU_VERSION_REG 0xFFCA0044U
void Init_Uart(void);
void Init_Uart(void)
{
#ifdef STDOUT_BASEADDRESS
u8 IterBAUDDIV; /* Iterator for available baud divisor values */
u32 BRGR_Value; /* Calculated value for baud rate generator */
u32 CalcBaudRate; /* Calculated baud rate */
u32 BaudError; /* Diff between calculated and requested baud
* rate */
u32 Best_BRGR = 0U; /* Best value for baud rate generator */
u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
u32 Best_Error = 0xFFFFFFFFU;
u32 PercentError;
u32 InputClk;
u32 BaudRate = UART_BAUDRATE;
/* set CD and BDIV */
#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
#else
/* STDIO is not set or axi_uart is being used for STDIO */
return;
#endif
InputClk = 25000000U;
/*
* Determine the Baud divider. It can be 4to 254.
* Loop through all possible combinations
*/
for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) {
/*
* Calculate the value for BRGR register
*/
BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 1U));
/*
* Calculate the baud rate from the BRGR value
*/
CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 1U));
/*
* Avoid unsigned integer underflow
*/
if (BaudRate > CalcBaudRate) {
BaudError = BaudRate - CalcBaudRate;
} else {
BaudError = CalcBaudRate - BaudRate;
}
/*
* Find the calculated baud rate closest to requested baud rate.
*/
if (Best_Error > BaudError) {
Best_BRGR = BRGR_Value;
Best_BAUDDIV = IterBAUDDIV;
Best_Error = BaudError;
}
}
/*
* Make sure the best error is not too large.
*/
PercentError = (Best_Error * 100U) / BaudRate;
if (((u32)MAX_BAUD_ERROR_RATE) < PercentError) {
return;
}
/* set CD and BDIV */
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV);
/*
* Veloce specific code
*/
if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) {
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 2U);
Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 4U);
}
/*
* 8 data, 1 stop, 0 parity bits
* sel_clk=uart_clk=APB clock
*/
Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U);
/* enable Tx/Rx and reset Tx/Rx data path */
Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U);
return;
#endif
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file usleep.c
*
* This function provides a microsecond delay using the Global Timer register in
* the ARM Cortex A53 MP core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "sleep.h"
#include "xtime_l.h"
#include "xparameters.h"
#include "xpseudo_asm.h"
#include "xreg_cortexa53.h"
/* Global Timer is always clocked at half of the CPU frequency */
#define COUNTS_PER_USECOND (COUNTS_PER_SECOND/1000000 )
/*****************************************************************************/
/**
*
* This API gives a delay in microseconds
*
* @param useconds requested
*
* @return 0 if the delay can be achieved, -1 if the requested delay
* is out of range
*
* @note None.
*
****************************************************************************/
s32 usleep(u32 useconds)
{
XTime tEnd, tCur;
/*write 50MHz frequency to System Time Stamp Generator Register*/
Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),XIOU_SCNTRS_FREQ);
/*Enable the counter*/
Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),XIOU_SCNTRS_CNT_CNTRL_REG_EN);
XTime_GetTime(&tCur);
tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
do
{
XTime_GetTime(&tCur);
} while (tCur < tEnd);
/*Disable the counter*/
Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),(~(XIOU_SCNTRS_CNT_CNTRL_REG_EN)));
return 0;
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file vectors.c
*
* This file contains the C level vectors for the ARM Cortex A53 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_exception.h"
#include "vectors.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
typedef struct {
Xil_ExceptionHandler Handler;
void *Data;
} XExc_VectorTableEntry;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
extern XExc_VectorTableEntry XExc_VectorTable[];
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* This is the C level wrapper for the FIQ interrupt called from the vectors.s
* file.
*
* @param None.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void FIQInterrupt(void)
{
XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
XIL_EXCEPTION_ID_FIQ_INT].Data);
}
/*****************************************************************************/
/**
*
* This is the C level wrapper for the IRQ interrupt called from the vectors.s
* file.
*
* @param None.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void IRQInterrupt(void)
{
XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
XIL_EXCEPTION_ID_IRQ_INT].Data);
}
/*****************************************************************************/
/**
*
* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
* file.
*
* @param None.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void SynchronousInterrupt(void)
{
XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
XIL_EXCEPTION_ID_SYNC_INT].Data);
}
/*****************************************************************************/
/**
*
* This is the C level wrapper for the SError Interrupt called from the
* vectors.s file.
*
* @param None.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void SErrorInterrupt(void)
{
XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file vectors.h
*
* This file contains the C level vector prototypes for the ARM Cortex A53 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _VECTORS_H_
#define _VECTORS_H_
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
void FIQInterrupt(void);
void IRQInterrupt(void);
void SynchronousInterrupt(void);
void SErrorInterrupt(void);
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

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lib/bsp/standalone/src/cortexa53/xfpd_slcr.h Normal file
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/* ### HEADER ### */
#ifndef __XFPD_SLCR_H__
#define __XFPD_SLCR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XfpdSlcr Base Address
*/
#define XFPD_SLCR_BASEADDR 0xFD610000UL
/**
* Register: XfpdSlcrWprot0
*/
#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL
#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL
#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL
#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL
#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL
/**
* Register: XfpdSlcrCtrl
*/
#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL
#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIsr
*/
#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrImr
*/
#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XfpdSlcrIer
*/
#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
#define XFPD_SLCR_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIdr
*/
#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrItr
*/
#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrWdtClkSel
*/
#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL
#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL
#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL
#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL
#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIntFpd
*/
#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL
/**
* Register: XfpdSlcrGpu
*/
#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL
#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL
#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL
#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL
#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL
#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL
#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL
#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL
#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL
#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL
#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL
#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL
#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL
#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL
#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL
#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL
#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL
#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL
/**
* Register: XfpdSlcrGdmaCfg
*/
#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL
/**
* Register: XfpdSlcrGdma
*/
#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL
#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL
/**
* Register: XfpdSlcrAfiFs
*/
#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL
/**
* Register: XfpdSlcrErrAtbIsr
*/
#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrErrAtbImr
*/
#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrErrAtbIer
*/
#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrErrAtbIdr
*/
#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrAtbCmdstore
*/
#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrAtbRespEn
*/
#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrAtbResptype
*/
#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrAtbPrescale
*/
#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL
#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL
#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL
#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL
#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL
#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_SLCR_H__ */

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/* ### HEADER ### */
#ifndef __XFPD_SLCR_SECURE_H__
#define __XFPD_SLCR_SECURE_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XfpdSlcrSecure Base Address
*/
#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL
/**
* Register: XfpdSlcrSecCtrl
*/
#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecIsr
*/
#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecImr
*/
#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecIer
*/
#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecIdr
*/
#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecItr
*/
#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecSata
*/
#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecPcie
*/
#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecDpdma
*/
#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL
#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL
#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL
#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL
#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecGdma
*/
#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL
#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL
#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL
#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL
#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL
/**
* Register: XfpdSlcrSecGic
*/
#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_SLCR_SECURE_H__ */

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lib/bsp/standalone/src/cortexa53/xfpd_xmpu_cfg.h Normal file
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/* ### HEADER ### */
#ifndef __XFPD_XMPU_SINK_H__
#define __XFPD_XMPU_SINK_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XfpdXmpuSink Base Address
*/
#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL
/**
* Register: XfpdXmpuSinkErrSts
*/
#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkIsr
*/
#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkImr
*/
#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
/**
* Register: XfpdXmpuSinkIer
*/
#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkIdr
*/
#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_XMPU_SINK_H__ */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.c
*
* Contains required functions for the ARM cache functionality. Cache APIs are
* yet to be implemented. They are left blank to avoid any compilation error
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_cache.h"
#include "xil_io.h"
#include "xpseudo_asm.h"
#include "xparameters.h"
#include "xreg_cortexa53.h"
#include "xil_exception.h"
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
/****************************************************************************
*
* Enable the Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheEnable(void)
{
u32 CtrlReg;
CtrlReg = mfcp(SCTLR_EL3);
/* enable caches only if they are disabled */
if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){
/* invalidate the Data cache */
Xil_DCacheInvalidate();
CtrlReg |= XREG_CONTROL_DCACHE_BIT;
/* enable the Data cache */
mtcp(SCTLR_EL3,CtrlReg);
}
}
/****************************************************************************
*
* Disable the Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheDisable(void)
{
u32 CtrlReg;
/* clean and invalidate the Data cache */
Xil_DCacheFlush();
CtrlReg = mfcp(SCTLR_EL3);
CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
/* disable the Data cache */
mtcp(SCTLR_EL3,CtrlReg);
}
/****************************************************************************
*
* invalidate the Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheInvalidate(void)
{
register u32 CsidReg, C7Reg;
u32 LineSize, NumWays;
u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
/* Number of level of cache*/
NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
CacheLevel=0U;
/* Select cache level 0 and D cache in CSSR */
mtcp(CSSELR_EL1,CacheLevel);
isb();
CsidReg = mfcp(CCSIDR_EL1);
/* Get the cacheline size, way size, index size from csidr */
LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
/* Number of Ways */
NumWays = (CsidReg & 0x00001FFFU) >> 3U;
NumWays += 0X00000001U;
/*Number of Set*/
NumSet = (CsidReg >> 13U) & 0x00007FFFU;
NumSet += 0X00000001U;
WayAdjust = clz(NumWays) - (u32)0x0000001FU;
Way = 0U;
Set = 0U;
/* Invalidate all the cachelines */
for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
C7Reg = Way | Set | CacheLevel;
mtcpdc(ISW,C7Reg);
Set += (0x00000001U << LineSize);
}
Set = 0U;
Way += (0x00000001U << WayAdjust);
}
/* Wait for invalidate to complete */
dsb();
/* Select cache level 1 and D cache in CSSR */
CacheLevel += (0x00000001U<<1U) ;
mtcp(CSSELR_EL1,CacheLevel);
isb();
CsidReg = mfcp(CCSIDR_EL1);
/* Get the cacheline size, way size, index size from csidr */
LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
/* Number of Ways */
NumWays = (CsidReg & 0x00001FFFU) >> 3U;
NumWays += 0x00000001U;
/* Number of Sets */
NumSet = (CsidReg >> 13U) & 0x00007FFFU;
NumSet += 0x00000001U;
WayAdjust = clz(NumWays) - (u32)0x0000001FU;
Way = 0U;
Set = 0U;
/* Invalidate all the cachelines */
for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
C7Reg = Way | Set | CacheLevel;
mtcpdc(ISW,C7Reg);
Set += (0x00000001U << LineSize);
}
Set = 0U;
Way += (0x00000001U << WayAdjust);
}
/* Wait for invalidate to complete */
dsb();
mtcpsr(currmask);
}
/****************************************************************************
*
* Invalidate a Data cache line. If the byte specified by the address (adr)
* is cached by the Data cache, the cacheline containing that byte is
* invalidated. If the cacheline is modified (dirty), the modified contents
* are written to system memory before the line is invalidated.
*
* @param Address to be flushed.
*
* @return None.
*
* @note The bottom 6 bits are set to 0, forced by architecture.
*
****************************************************************************/
void Xil_DCacheInvalidateLine(INTPTR adr)
{
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
/* Select cache level 0 and D cache in CSSR */
mtcp(CSSELR_EL1,0x0);
mtcpdc(IVAC,(adr & (~0x3F)));
/* Wait for invalidate to complete */
dsb();
/* Select cache level 1 and D cache in CSSR */
mtcp(CSSELR_EL1,0x2);
mtcpdc(IVAC,(adr & (~0x3F)));
/* Wait for invalidate to complete */
dsb();
mtcpsr(currmask);
}
/****************************************************************************
*
* Invalidate the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are written to system memory
* before the line is invalidated.
*
* @param Start address of range to be invalidated.
* @param Length of range to be invalidated in bytes.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
{
const u32 cacheline = 64U;
u32 end;
u32 tempadr = adr;
u32 tempend;
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0U) {
end = tempadr + len;
tempend = end;
if ((tempadr & (cacheline-1U)) != 0U) {
tempadr &= (~(cacheline - 1U));
Xil_DCacheFlushLine(tempadr);
tempadr += cacheline;
}
if ((tempend & (cacheline-1U)) != 0U) {
tempend &= (~(cacheline - 1U));
Xil_DCacheFlushLine(tempend);
}
while (tempadr < tempend) {
/* Select cache level 0 and D cache in CSSR */
mtcp(CSSELR_EL1,0x0);
/* Invalidate Data cache line */
mtcpdc(IVAC,(tempadr & (~0x3F)));
/* Wait for invalidate to complete */
dsb();
/* Select cache level 0 and D cache in CSSR */
mtcp(CSSELR_EL1,0x2);
/* Invalidate Data cache line */
mtcpdc(IVAC,(tempadr & (~0x3F)));
/* Wait for invalidate to complete */
dsb();
tempadr += cacheline;
}
}
mtcpsr(currmask);
}
/****************************************************************************
*
* Flush the Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheFlush(void)
{
register u32 CsidReg, C7Reg;
u32 LineSize, NumWays;
u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
/* Number of level of cache*/
NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
CacheLevel = 0U;
/* Select cache level 0 and D cache in CSSR */
mtcp(CSSELR_EL1,CacheLevel);
isb();
CsidReg = mfcp(CCSIDR_EL1);
/* Get the cacheline size, way size, index size from csidr */
LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
/* Number of Ways */
NumWays = (CsidReg & 0x00001FFFU) >> 3U;
NumWays += 0x00000001U;
/*Number of Set*/
NumSet = (CsidReg >> 13U) & 0x00007FFFU;
NumSet += 0x00000001U;
WayAdjust = clz(NumWays) - (u32)0x0000001FU;
Way = 0U;
Set = 0U;
/* Flush all the cachelines */
for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
C7Reg = Way | Set | CacheLevel;
mtcpdc(CISW,C7Reg);
Set += (0x00000001U << LineSize);
}
Set = 0U;
Way += (0x00000001U << WayAdjust);
}
/* Wait for Flush to complete */
dsb();
/* Select cache level 1 and D cache in CSSR */
CacheLevel += (0x00000001U << 1U);
mtcp(CSSELR_EL1,CacheLevel);
isb();
CsidReg = mfcp(CCSIDR_EL1);
/* Get the cacheline size, way size, index size from csidr */
LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
/* Number of Ways */
NumWays = (CsidReg & 0x00001FFFU) >> 3U;
NumWays += 0x00000001U;
/* Number of Sets */
NumSet = (CsidReg >> 13U) & 0x00007FFFU;
NumSet += 0x00000001U;
WayAdjust=clz(NumWays) - (u32)0x0000001FU;
Way = 0U;
Set = 0U;
/* Flush all the cachelines */
for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
C7Reg = Way | Set | CacheLevel;
mtcpdc(CISW,C7Reg);
Set += (0x00000001U << LineSize);
}
Set=0U;
Way += (0x00000001U<<WayAdjust);
}
/* Wait for Flush to complete */
dsb();
mtcpsr(currmask);
}
/****************************************************************************
*
* Flush a Data cache line. If the byte specified by the address (adr)
* is cached by the Data cache, the cacheline containing that byte is
* invalidated. If the cacheline is modified (dirty), the entire
* contents of the cacheline are written to system memory before the
* line is invalidated.
*
* @param Address to be flushed.
*
* @return None.
*
* @note The bottom 6 bits are set to 0, forced by architecture.
*
****************************************************************************/
void Xil_DCacheFlushLine(INTPTR adr)
{
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
/* Select cache level 0 and D cache in CSSR */
mtcp(CSSELR_EL1,0x0);
mtcpdc(CIVAC,(adr & (~0x3F)));
/* Wait for flush to complete */
dsb();
/* Select cache level 1 and D cache in CSSR */
mtcp(CSSELR_EL1,0x2);
mtcpdc(CIVAC,(adr & (~0x3F)));
/* Wait for flush to complete */
dsb();
mtcpsr(currmask);
}
/****************************************************************************
* Flush the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the written to system memory first before the
* before the line is invalidated.
*
* @param Start address of range to be flushed.
* @param Length of range to be flushed in bytes.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheFlushRange(INTPTR adr, u32 len)
{
const u32 cacheline = 64U;
u32 end;
u32 tempadr = adr;
u32 tempend;
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0x00000000U) {
end = tempadr + len;
tempend = end;
if ((tempadr & (0x3F)) != 0) {
tempadr &= ~(0x3F);
Xil_DCacheFlushLine(tempadr);
tempadr += cacheline;
}
if ((tempend & (0x3F)) != 0) {
tempend &= ~(0x3F);
Xil_DCacheFlushLine(tempend);
}
while (tempadr < tempend) {
/* Select cache level 0 and D cache in CSSR */
mtcp(CSSELR_EL1,0x0);
/* Flush Data cache line */
mtcpdc(CIVAC,(tempadr & (~0x3F)));
/* Wait for flush to complete */
dsb();
/* Select cache level 1 and D cache in CSSR */
mtcp(CSSELR_EL1,0x2);
/* Flush Data cache line */
mtcpdc(CIVAC,(tempadr & (~0x3F)));
/* Wait for flush to complete */
dsb();
tempadr += cacheline;
}
}
mtcpsr(currmask);
}
/****************************************************************************
*
* Enable the instruction cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_ICacheEnable(void)
{
u32 CtrlReg;
CtrlReg = mfcp(SCTLR_EL3);
/* enable caches only if they are disabled */
if((CtrlReg & XREG_CONTROL_ICACHE_BIT)==0x00000000U){
/* invalidate the instruction cache */
Xil_ICacheInvalidate();
CtrlReg |= XREG_CONTROL_ICACHE_BIT;
/* enable the instruction cache */
mtcp(SCTLR_EL3,CtrlReg);
}
}
/****************************************************************************
*
* Disable the instruction cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_ICacheDisable(void)
{
u32 CtrlReg;
CtrlReg = mfcp(SCTLR_EL3);
/* invalidate the instruction cache */
Xil_ICacheInvalidate();
CtrlReg &= ~(XREG_CONTROL_ICACHE_BIT);
/* disable the instruction cache */
mtcp(SCTLR_EL3,CtrlReg);
}
/****************************************************************************
*
* Invalidate the entire instruction cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_ICacheInvalidate(void)
{
unsigned int currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
mtcp(CSSELR_EL1,0x1);
dsb();
/* invalidate the instruction cache */
mtcpicall(IALLU);
/* Wait for invalidate to complete */
dsb();
mtcpsr(currmask);
}
/****************************************************************************
*
* Invalidate an instruction cache line. If the instruction specified by the
* parameter adr is cached by the instruction cache, the cacheline containing
* that instruction is invalidated.
*
* @param None.
*
* @return None.
*
* @note The bottom 6 bits are set to 0, forced by architecture.
*
****************************************************************************/
void Xil_ICacheInvalidateLine(INTPTR adr)
{
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
mtcp(CSSELR_EL1,0x1);
/*Invalidate I Cache line*/
mtcpic(IVAU,adr & (~0x3F));
/* Wait for invalidate to complete */
dsb();
mtcpsr(currmask);
}
/****************************************************************************
*
* Invalidate the instruction cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are lost and are NOT
* written to system memory before the line is invalidated.
*
* @param Start address of range to be invalidated.
* @param Length of range to be invalidated in bytes.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
{
const u32 cacheline = 64U;
u32 end;
u32 tempadr = adr;
u32 tempend;
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0x00000000U) {
end = tempadr + len;
tempend = end;
tempadr &= ~(cacheline - 0x00000001U);
/* Select cache Level 0 I-cache in CSSR */
mtcp(CSSELR_EL1,0x1);
while (tempadr < tempend) {
/*Invalidate I Cache line*/
mtcpic(IVAU,adr & (~0x3F));
tempadr += cacheline;
}
}
/* Wait for invalidate to complete */
dsb();
mtcpsr(currmask);
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* Contains required functions for the ARM cache functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
void Xil_DCacheEnable(void);
void Xil_DCacheDisable(void);
void Xil_DCacheInvalidate(void);
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
void Xil_DCacheInvalidateLine(INTPTR adr);
void Xil_DCacheFlush(void);
void Xil_DCacheFlushRange(INTPTR adr, u32 len);
void Xil_DCacheFlushLine(INTPTR adr);
void Xil_ICacheEnable(void);
void Xil_ICacheDisable(void);
void Xil_ICacheInvalidate(void);
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
void Xil_ICacheInvalidateLine(INTPTR adr);
#ifdef __cplusplus
}
#endif
#endif

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xil_exception.c
*
* This file contains low-level driver functions for the Cortex A53 exception
* Handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#include "xpseudo_asm.h"
#include "xdebug.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
typedef struct {
Xil_ExceptionHandler Handler;
void *Data;
} XExc_VectorTableEntry;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
static void Xil_ExceptionNullHandler(void *Data);
/************************** Variable Definitions *****************************/
/*
* Exception vector table to store handlers for each exception vector.
*/
XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
{
{Xil_ExceptionNullHandler, NULL},
{Xil_SyncAbortHandler, NULL},
{Xil_ExceptionNullHandler, NULL},
{Xil_ExceptionNullHandler, NULL},
{Xil_SErrorAbortHandler, NULL},
};
/****************************************************************************/
/**
*
* This function is a stub Handler that is the default Handler that gets called
* if the application has not setup a Handler for a specific exception. The
* function interface has to match the interface specified for a Handler even
* though none of the arguments are used.
*
* @param Data is unused by this function.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
static void Xil_ExceptionNullHandler(void *Data)
{
(void *)Data;
DieLoop: goto DieLoop;
}
/****************************************************************************/
/**
*
* The function is a common API used to initialize exception handlers across all
* processors supported. For ARM CortexA53, the exception handlers are being
* initialized statically and hence this function does not do anything.
*
*
* @param None.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void Xil_ExceptionInit(void)
{
return;
}
/*****************************************************************************/
/**
*
* Makes the connection between the Id of the exception source and the
* associated Handler that is to run when the exception is recognized. The
* argument provided in this call as the Data is used as the argument
* for the Handler when it is called.
*
* @param exception_id contains the ID of the exception source and should
* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
See xil_exception_l.h for further information.
* @param Handler to the Handler for that exception.
* @param Data is a reference to Data that will be passed to the
* Handler when it gets called.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_ExceptionRegisterHandler(u32 Exception_id,
Xil_ExceptionHandler Handler,
void *Data)
{
XExc_VectorTable[Exception_id].Handler = Handler;
XExc_VectorTable[Exception_id].Data = Data;
}
/*****************************************************************************/
/**
*
* Removes the Handler for a specific exception Id. The stub Handler is then
* registered for this exception Id.
*
* @param exception_id contains the ID of the exception source and should
* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
* See xil_exception_l.h for further information.
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_ExceptionRemoveHandler(u32 Exception_id)
{
Xil_ExceptionRegisterHandler(Exception_id,
Xil_ExceptionNullHandler,
NULL);
}
/*****************************************************************************/
/**
*
* Default Synchronous abort handler which prints a debug message on console if
* Debug flag is enabled
*
* @param None
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_SyncAbortHandler(void *CallBackRef){
xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
while(1) {
;
}
}
/*****************************************************************************/
/**
*
* Default SError abort handler which prints a debug message on console if
* Debug flag is enabled
*
* @param None
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_SErrorAbortHandler(void *CallBackRef){
xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
while(1) {
;
}
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_exception.h
*
* This header file contains ARM Cortex A53 specific exception related APIs.
* For exception related functions that can be used across all Xilinx supported
* processors, please use xil_exception.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
#define XIL_EXCEPTION_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xpseudo_asm.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions ****************************/
#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
#define XIL_EXCEPTION_ID_FIRST 0U
#define XIL_EXCEPTION_ID_SYNC_INT 1U
#define XIL_EXCEPTION_ID_IRQ_INT 2U
#define XIL_EXCEPTION_ID_FIQ_INT 3U
#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
#define XIL_EXCEPTION_ID_LAST 5U
/*
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
*/
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
/**************************** Type Definitions ******************************/
/**
* This typedef is the exception handler function.
*/
typedef void (*Xil_ExceptionHandler)(void *data);
typedef void (*Xil_InterruptHandler)(void *data);
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* Enable Exceptions.
*
* @param Mask for exceptions to be enabled.
*
* @return None.
*
* @note If bit is 0, exception is enabled.
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
*
******************************************************************************/
#define Xil_ExceptionEnableMask(Mask) \
mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
/****************************************************************************/
/**
* Enable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define Xil_ExceptionEnable() \
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
/****************************************************************************/
/**
* Disable Exceptions.
*
* @param Mask for exceptions to be enabled.
*
* @return None.
*
* @note If bit is 1, exception is disabled.
* C-Style signature: Xil_ExceptionDisableMask(Mask)
*
******************************************************************************/
#define Xil_ExceptionDisableMask(Mask) \
mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
/****************************************************************************/
/**
* Disable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define Xil_ExceptionDisable() \
Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
Xil_ExceptionHandler Handler,
void *Data);
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
extern void Xil_ExceptionInit(void);
void Xil_SyncAbortHandler(void *CallBackRef);
void Xil_SErrorAbortHandler(void *CallBackRef);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_EXCEPTION_H */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.c
*
* Contains I/O functions for memory-mapped or non-memory-mapped I/O
* architectures. These functions encapsulate Cortex A53 architecture-specific
* I/O requirements.
*
* @note
*
* This file contains architecture-dependent code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xpseudo_asm.h"
#include "xreg_cortexa53.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Performs an input operation for an 8-bit memory location by reading from the
* specified address and returning the Value read from that address.
*
* @param Addr contains the address to perform the input operation
* at.
*
* @return The Value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u8 Xil_In8(INTPTR Addr)
{
return *(volatile u8 *) Addr;
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the Value read from that address.
*
* @param Addr contains the address to perform the input operation
* at.
*
* @return The Value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u16 Xil_In16(INTPTR Addr)
{
return *(volatile u16 *) Addr;
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the Value read from that address.
*
* @param Addr contains the address to perform the input operation
* at.
*
* @return The Value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u32 Xil_In32(INTPTR Addr)
{
return *(volatile u32 *) Addr;
}
/*****************************************************************************/
/**
*
* Performs an output operation for an 8-bit memory location by writing the
* specified Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Out8(INTPTR Addr, u8 Value)
{
u8 *LocalAddr = (u8 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Out16(INTPTR Addr, u16 Value)
{
u16 *LocalAddr = (u16 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Out32(INTPTR Addr, u32 Value)
{
u32 *LocalAddr = (u32 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 64-bit memory location by writing the
* specified Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Out64(INTPTR Addr, u64 Value)
{
u64 *LocalAddr = (u64 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 64-bit memory location by reading the
* specified Value to the the specified address.
*
* @param OutAddress contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
u64 Xil_In64(INTPTR Addr)
{
return *(volatile u64 *) Addr;
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the byte-swapped Value read from that
* address.
*
* @param Addr contains the address to perform the input operation
* at.
*
* @return The byte-swapped Value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u16 Xil_In16BE(INTPTR Addr)
{
u16 temp;
u16 result;
temp = Xil_In16(Addr);
result = Xil_EndianSwap16(temp);
return result;
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the byte-swapped Value read from that
* address.
*
* @param Addr contains the address to perform the input operation
* at.
*
* @return The byte-swapped Value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u32 Xil_In32BE(INTPTR Addr)
{
u32 temp;
u32 result;
temp = Xil_In32(Addr);
result = Xil_EndianSwap32(temp);
return result;
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified Value to the the specified address. The Value is byte-swapped
* before being written.
*
* @param Addr contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Out16BE(INTPTR Addr, u16 Value)
{
u16 temp;
temp = Xil_EndianSwap16(Value);
Xil_Out16(Addr, temp);
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified Value to the the specified address. The Value is byte-swapped
* before being written.
*
* @param Addr contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Out32BE(INTPTR Addr, u32 Value)
{
u32 temp;
temp = Xil_EndianSwap32(Value);
Xil_Out32(Addr, temp);
}
/*****************************************************************************/
/**
*
* Perform a 16-bit endian converion.
*
* @param Data contains the value to be converted.
*
* @return converted value.
*
* @note None.
*
******************************************************************************/
u16 Xil_EndianSwap16(u16 Data)
{
return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
}
/*****************************************************************************/
/**
*
* Perform a 32-bit endian converion.
*
* @param Data contains the value to be converted.
*
* @return converted value.
*
* @note None.
*
******************************************************************************/
u32 Xil_EndianSwap32(u32 Data)
{
u16 LoWord;
u16 HiWord;
/* get each of the half words from the 32 bit word */
LoWord = (u16) (Data & 0x0000FFFFU);
HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
/* byte swap each of the 16 bit half words */
LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
/* swap the half words before returning the value */
return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
}

240
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.h
*
* This file contains the interface for the general IO component, which
* encapsulates the Input/Output functions for processors that do not
* require any special I/O handling.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xpseudo_asm.h"
#include "xil_printf.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
# define SYNCHRONIZE_IO dmb()
# define INST_SYNC isb()
# define DATA_SYNC dsb()
/*****************************************************************************/
/**
*
* Perform an big-endian input operation for a 16-bit memory location
* by reading from the specified address and returning the Value read from
* that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The Value read from the specified input address with the
* proper endianness. The return Value has the same endianness
* as that of the processor, i.e. if the processor is
* little-engian, the return Value is the byte-swapped Value read
* from the address.
*
* @note None.
*
******************************************************************************/
#define Xil_In16LE(Addr) Xil_In16((Addr))
/*****************************************************************************/
/**
*
* Perform a big-endian input operation for a 32-bit memory location
* by reading from the specified address and returning the Value read from
* that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The Value read from the specified input address with the
* proper endianness. The return Value has the same endianness
* as that of the processor, i.e. if the processor is
* little-engian, the return Value is the byte-swapped Value read
* from the address.
*
*
* @note None.
*
******************************************************************************/
#define Xil_In32LE(Addr) Xil_In32((Addr))
/*****************************************************************************/
/**
*
* Perform a big-endian output operation for a 16-bit memory location
* by writing the specified Value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param Value contains the Value to be output at the specified address.
* The Value has the same endianness as that of the processor.
* If the processor is little-endian, the byte-swapped Value is
* written to the address.
*
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
/*****************************************************************************/
/**
*
* Perform a big-endian output operation for a 32-bit memory location
* by writing the specified Value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param Value contains the Value to be output at the specified address.
* The Value has the same endianness as that of the processor.
* If the processor is little-endian, the byte-swapped Value is
* written to the address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
/*****************************************************************************/
/**
*
* Convert a 32-bit number from host byte order to network byte order.
*
* @param Data the 32-bit number to be converted.
*
* @return The converted 32-bit number in network byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
/*****************************************************************************/
/**
*
* Convert a 16-bit number from host byte order to network byte order.
*
* @param Data the 16-bit number to be converted.
*
* @return The converted 16-bit number in network byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Htons(Data) Xil_EndianSwap16((Data))
/*****************************************************************************/
/**
*
* Convert a 32-bit number from network byte order to host byte order.
*
* @param Data the 32-bit number to be converted.
*
* @return The converted 32-bit number in host byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
/*****************************************************************************/
/**
*
* Convert a 16-bit number from network byte order to host byte order.
*
* @param Data the 16-bit number to be converted.
*
* @return The converted 16-bit number in host byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
/************************** Function Prototypes ******************************/
/* The following functions allow the software to be transportable across
* processors which may use memory mapped I/O or I/O which is mapped into a
* seperate address space.
*/
u8 Xil_In8(INTPTR Addr);
u16 Xil_In16(INTPTR Addr);
u32 Xil_In32(INTPTR Addr);
u64 Xil_In64(INTPTR Addr);
void Xil_Out8(INTPTR Addr, u8 Value);
void Xil_Out16(INTPTR Addr, u16 Value);
void Xil_Out32(INTPTR Addr, u32 Value);
void Xil_Out64(INTPTR Addr, u64 Value);
u16 Xil_In16BE(INTPTR Addr);
u32 Xil_In32BE(INTPTR Addr);
void Xil_Out16BE(INTPTR Addr, u16 Value);
void Xil_Out32BE(INTPTR Addr, u32 Value);
u16 Xil_EndianSwap16(u16 Data);
u32 Xil_EndianSwap32(u32 Data);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_mmu.c
*
* This file provides APIs for enabling/disabling MMU and setting the memory
* attributes for sections, in the MMU translation table.
* MMU APIs are yet to be implemented. They are left blank to avoid any
* compilation error
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_cache.h"
#include "xpseudo_asm.h"
#include "xil_types.h"
#include "xil_mmu.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
extern INTPTR MMUTableL1;
extern INTPTR MMUTableL2;
/************************** Function Prototypes ******************************/
/*****************************************************************************
*
* Set the memory attributes for a section, in the translation table.
*
* @param addr is the address for which attributes are to be set.
* @param attrib specifies the attributes for that memory region.
*
* @return None.
*
* @note The MMU and D-cache need not be disabled before changing an
* translation table attribute.
*
******************************************************************************/
void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib)
{
INTPTR *ptr;
INTPTR section;
/* if region is less than 4GB MMUTable level 2 need to be modified */
if(Addr<0x100000000){
section = Addr / 0x00200000U;
ptr = &MMUTableL2 + section;
*ptr = (Addr & (~0x001FFFFFU)) | attrib;
}
/* if region is greater than 4GB MMUTable level 1 need to be modified */
else{
section = Addr / 0x40000000U;
ptr = &MMUTableL1 + section;
*ptr = (Addr & (~0x3FFFFFFFU)) | attrib;
}
Xil_DCacheFlush();
mtcptlbi(ALLE3);
dsb(); /* ensure completion of the BP and TLB invalidation */
isb(); /* synchronize context on this processor */
}

79
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_mmu.h
*
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef XIL_MMU_H
#define XIL_MMU_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_MMU_H */

329
lib/bsp/standalone/src/cortexa53/xil_printf.c Normal file
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/*---------------------------------------------------*/
/* Modified from : */
/* Public Domain version of printf */
/* Rud Merriam, Compsult, Inc. Houston, Tx. */
/* For Embedded Systems Programming, 1991 */
/* */
/*---------------------------------------------------*/
#include "xil_printf.h"
#include "xil_types.h"
#include "xil_assert.h"
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
typedef struct params_s {
s32 len;
s32 num1;
s32 num2;
char8 pad_character;
s32 do_padding;
s32 left_flag;
} params_t;
static void padding( const s32 l_flag,const params_t *par);
static void outs(const charptr lp, params_t *par);
static void outnum( const s32 n, const s32 base, params_t *par);
static s32 getnum( charptr* linep);
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
/* same as the standard printf function without the */
/* overhead most run-time libraries involve. Usually */
/* the printf brings in many kilobytes of code and */
/* that is unacceptable in most embedded systems. */
/*---------------------------------------------------*/
/*---------------------------------------------------*/
/* */
/* This routine puts pad characters into the output */
/* buffer. */
/* */
static void padding( const s32 l_flag, const params_t *par)
{
s32 i;
if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
i=(par->len);
for (; i<(par->num1); i++) {
outbyte( par->pad_character);
}
}
}
/*---------------------------------------------------*/
/* */
/* This routine moves a string to the output buffer */
/* as directed by the padding and positioning flags. */
/* */
static void outs(const charptr lp, params_t *par)
{
charptr LocalPtr;
LocalPtr = lp;
/* pad on left if needed */
if(LocalPtr != NULL) {
par->len = (s32)strlen( LocalPtr);
}
padding( !(par->left_flag), par);
/* Move string to the buffer */
while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
(par->num2)--;
outbyte(*LocalPtr);
LocalPtr += 1;
}
/* Pad on right if needed */
/* CR 439175 - elided next stmt. Seemed bogus. */
/* par->len = strlen( lp) */
padding( par->left_flag, par);
}
/*---------------------------------------------------*/
/* */
/* This routine moves a number to the output buffer */
/* as directed by the padding and positioning flags. */
/* */
static void outnum( const s32 n, const s32 base, params_t *par)
{
charptr cp;
s32 negative;
s32 i;
char8 outbuf[32];
const char8 digits[] = "0123456789ABCDEF";
u32 num;
for(i = 0; i<32; i++) {
outbuf[i] = '0';
}
/* Check if number is negative */
if ((base == 10) && (n < 0L)) {
negative = 1;
num =(-(n));
}
else{
num = (n);
negative = 0;
}
/* Build number (backwards) in outbuf */
i = 0;
do {
outbuf[i] = digits[(num % base)];
i++;
num /= base;
} while (num > 0);
if (negative != 0) {
outbuf[i] = '-';
i++;
}
outbuf[i] = 0;
i--;
/* Move the converted number to the buffer and */
/* add in the padding where needed. */
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
outbyte( outbuf[i] );
i--;
}
padding( par->left_flag, par);
}
/*---------------------------------------------------*/
/* */
/* This routine gets a number from the format */
/* string. */
/* */
static s32 getnum( charptr* linep)
{
s32 n;
s32 ResultIsDigit = 0;
charptr cptr;
n = 0;
cptr = *linep;
if(cptr != NULL){
ResultIsDigit = isdigit(((s32)*cptr));
}
while (ResultIsDigit != 0) {
if(cptr != NULL){
n = ((n*10) + (((s32)*cptr) - (s32)'0'));
cptr += 1;
if(cptr != NULL){
ResultIsDigit = isdigit(((s32)*cptr));
}
}
ResultIsDigit = isdigit(((s32)*cptr));
}
*linep = ((charptr )(cptr));
return(n);
}
/*---------------------------------------------------*/
/* */
/* This routine operates just like a printf/sprintf */
/* routine. It outputs a set of data under the */
/* control of a formatting string. Not all of the */
/* standard C format control are supported. The ones */
/* provided are primarily those needed for embedded */
/* systems work. Primarily the floating point */
/* routines are omitted. Other formats could be */
/* added easily by following the examples shown for */
/* the supported formats. */
/* */
/* void esp_printf( const func_ptr f_ptr,
const charptr ctrl1, ...) */
void xil_printf( const char8 *ctrl1, ...)
{
s32 Check;
s32 long_flag;
s32 dot_flag;
params_t par;
char8 ch;
va_list argp;
char8 *ctrl = (char8 *)ctrl1;
va_start( argp, ctrl1);
while ((ctrl != NULL) && (*ctrl != (char8)0)) {
/* move format string chars to buffer until a */
/* format control is found. */
if (*ctrl != '%') {
outbyte(*ctrl);
ctrl += 1;
continue;
}
/* initialize all the flags for this format. */
dot_flag = 0;
long_flag = 0;
par.left_flag = 0;
par.do_padding = 0;
par.pad_character = ' ';
par.num2=32767;
par.num1=0;
par.len=0;
try_next:
if(ctrl != NULL) {
ctrl += 1;
}
if(ctrl != NULL) {
ch = *ctrl;
}
else {
ch = *ctrl;
}
if (isdigit((s32)ch) != 0) {
if (dot_flag != 0) {
par.num2 = getnum(&ctrl);
}
else {
if (ch == '0') {
par.pad_character = '0';
}
if(ctrl != NULL) {
par.num1 = getnum(&ctrl);
}
par.do_padding = 1;
}
if(ctrl != NULL) {
ctrl -= 1;
}
goto try_next;
}
switch (tolower((s32)ch)) {
case '%':
outbyte( '%');
Check = 1;
break;
case '-':
par.left_flag = 1;
Check = 0;
break;
case '.':
dot_flag = 1;
Check = 0;
break;
case 'l':
long_flag = 1;
Check = 0;
break;
case 'd':
if ((long_flag != 0) || (ch == 'D')) {
outnum( va_arg(argp, s32), 10L, &par);
}
else {
outnum( va_arg(argp, s32), 10L, &par);
}
Check = 1;
break;
case 'x':
outnum((s32)va_arg(argp, s32), 16L, &par);
Check = 1;
break;
case 's':
outs( va_arg( argp, char *), &par);
Check = 1;
break;
case 'c':
outbyte( va_arg( argp, s32));
Check = 1;
break;
case '\\':
switch (*ctrl) {
case 'a':
outbyte( ((char8)0x07));
break;
case 'h':
outbyte( ((char8)0x08));
break;
case 'r':
outbyte( ((char8)0x0D));
break;
case 'n':
outbyte( ((char8)0x0D));
outbyte( ((char8)0x0A));
break;
default:
outbyte( *ctrl);
break;
}
ctrl += 1;
Check = 0;
break;
default:
Check = 1;
break;
}
if(Check == 1) {
if(ctrl != NULL) {
ctrl += 1;
}
continue;
}
goto try_next;
}
va_end( argp);
}
/*---------------------------------------------------*/

44
lib/bsp/standalone/src/cortexa53/xil_printf.h Normal file
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#ifndef XIL_PRINTF_H
#define XIL_PRINTF_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
#include "xil_types.h"
#include "xparameters.h"
/*----------------------------------------------------*/
/* Use the following parameter passing structure to */
/* make xil_printf re-entrant. */
/*----------------------------------------------------*/
struct params_s;
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
/* same as the standard printf function without the */
/* overhead most run-time libraries involve. Usually */
/* the printf brings in many kilobytes of code and */
/* that is unacceptable in most embedded systems. */
/*---------------------------------------------------*/
typedef char8* charptr;
typedef s32 (*func_ptr)(int c);
/* */
void xil_printf( const char8 *ctrl1, ...);
void print( const char8 *ptr);
extern void outbyte (char8 c);
extern char8 inbyte(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/* ### HEADER ### */
#ifndef __XIOU_SECURE_SLCR_H__
#define __XIOU_SECURE_SLCR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XiouSecureSlcr Base Address
*/
#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL
/**
* Register: XiouSecSlcrAxiWprtcn
*/
#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrAxiRprtcn
*/
#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrCtrl
*/
#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrIsr
*/
#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrImr
*/
#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XiouSecSlcrIer
*/
#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrIdr
*/
#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrItr
*/
#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XIOU_SECURE_SLCR_H__ */

4029
lib/bsp/standalone/src/cortexa53/xiou_slcr.h Normal file
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5667
lib/bsp/standalone/src/cortexa53/xlpd_slcr.h Normal file
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141
lib/bsp/standalone/src/cortexa53/xlpd_slcr_secure.h Normal file
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/* ### HEADER ### */
#ifndef __XLPD_SLCR_SECURE_H__
#define __XLPD_SLCR_SECURE_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XlpdSlcrSecure Base Address
*/
#define XLPD_SLCR_SECURE_BASEADDR 0xFF4B0000UL
/**
* Register: XlpdSlcrSecCtrl
*/
#define XLPD_SLCR_SEC_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
#define XLPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecIsr
*/
#define XLPD_SLCR_SEC_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
#define XLPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecImr
*/
#define XLPD_SLCR_SEC_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
#define XLPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XlpdSlcrSecIer
*/
#define XLPD_SLCR_SEC_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
#define XLPD_SLCR_SEC_IER_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecIdr
*/
#define XLPD_SLCR_SEC_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
#define XLPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecItr
*/
#define XLPD_SLCR_SEC_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
#define XLPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecRpu
*/
#define XLPD_SLCR_SEC_RPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
#define XLPD_SLCR_SEC_RPU_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT 1UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH 1UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK 0x00000002UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL 0x0UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT 0UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH 1UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK 0x00000001UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecAdma
*/
#define XLPD_SLCR_SEC_ADMA ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
#define XLPD_SLCR_SEC_ADMA_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT 0UL
#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH 8UL
#define XLPD_SLCR_SEC_ADMA_TZ_MASK 0x000000ffUL
#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecSafetyChk
*/
#define XLPD_SLCR_SEC_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT 0UL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH 32UL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK 0xffffffffUL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecUsb
*/
#define XLPD_SLCR_SEC_USB ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
#define XLPD_SLCR_SEC_USB_RSTVAL 0x00000003UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT 1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH 1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK 0x00000002UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL 0x1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT 0UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH 1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK 0x00000001UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL 0x1UL
#ifdef __cplusplus
}
#endif
#endif /* __XLPD_SLCR_SECURE_H__ */

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/* ### HEADER ### */
#ifndef __XLPD_XPPU_H__
#define __XLPD_XPPU_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XlpdXppu Base Address
*/
#define XLPD_XPPU_BASEADDR 0xFF980000UL
/**
* Register: XlpdXppuCtrl
*/
#define XLPD_XPPU_CTRL ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL )
#define XLPD_XPPU_CTRL_RSTVAL 0x00000000UL
#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT 2UL
#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH 1UL
#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK 0x00000004UL
#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL 0x0UL
#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT 1UL
#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH 1UL
#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK 0x00000002UL
#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL 0x0UL
#define XLPD_XPPU_CTRL_EN_SHIFT 0UL
#define XLPD_XPPU_CTRL_EN_WIDTH 1UL
#define XLPD_XPPU_CTRL_EN_MASK 0x00000001UL
#define XLPD_XPPU_CTRL_EN_DEFVAL 0x0UL
/**
* Register: XlpdXppuErrSts1
*/
#define XLPD_XPPU_ERR_STS1 ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL )
#define XLPD_XPPU_ERR_STS1_RSTVAL 0x00000000UL
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT 0UL
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH 32UL
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL
/**
* Register: XlpdXppuErrSts2
*/
#define XLPD_XPPU_ERR_STS2 ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL )
#define XLPD_XPPU_ERR_STS2_RSTVAL 0x00000000UL
#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT 0UL
#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH 16UL
#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK 0x0000ffffUL
#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL 0x0UL
/**
* Register: XlpdXppuPoison
*/
#define XLPD_XPPU_POISON ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL )
#define XLPD_XPPU_POISON_RSTVAL 0x00000000UL
#define XLPD_XPPU_POISON_BASE_SHIFT 0UL
#define XLPD_XPPU_POISON_BASE_WIDTH 20UL
#define XLPD_XPPU_POISON_BASE_MASK 0x000fffffUL
#define XLPD_XPPU_POISON_BASE_DEFVAL 0x0UL
/**
* Register: XlpdXppuIsr
*/
#define XLPD_XPPU_ISR ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL )
#define XLPD_XPPU_ISR_RSTVAL 0x00000000UL
#define XLPD_XPPU_ISR_APER_PARITY_SHIFT 7UL
#define XLPD_XPPU_ISR_APER_PARITY_WIDTH 1UL
#define XLPD_XPPU_ISR_APER_PARITY_MASK 0x00000080UL
#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_APER_TZ_SHIFT 6UL
#define XLPD_XPPU_ISR_APER_TZ_WIDTH 1UL
#define XLPD_XPPU_ISR_APER_TZ_MASK 0x00000040UL
#define XLPD_XPPU_ISR_APER_TZ_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_APER_PERM_SHIFT 5UL
#define XLPD_XPPU_ISR_APER_PERM_WIDTH 1UL
#define XLPD_XPPU_ISR_APER_PERM_MASK 0x00000020UL
#define XLPD_XPPU_ISR_APER_PERM_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_MID_PARITY_SHIFT 3UL
#define XLPD_XPPU_ISR_MID_PARITY_WIDTH 1UL
#define XLPD_XPPU_ISR_MID_PARITY_MASK 0x00000008UL
#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_MID_RO_SHIFT 2UL
#define XLPD_XPPU_ISR_MID_RO_WIDTH 1UL
#define XLPD_XPPU_ISR_MID_RO_MASK 0x00000004UL
#define XLPD_XPPU_ISR_MID_RO_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_MID_MISS_SHIFT 1UL
#define XLPD_XPPU_ISR_MID_MISS_WIDTH 1UL
#define XLPD_XPPU_ISR_MID_MISS_MASK 0x00000002UL
#define XLPD_XPPU_ISR_MID_MISS_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_INV_APB_SHIFT 0UL
#define XLPD_XPPU_ISR_INV_APB_WIDTH 1UL
#define XLPD_XPPU_ISR_INV_APB_MASK 0x00000001UL
#define XLPD_XPPU_ISR_INV_APB_DEFVAL 0x0UL
/**
* Register: XlpdXppuImr
*/
#define XLPD_XPPU_IMR ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL )
#define XLPD_XPPU_IMR_RSTVAL 0x000000efUL
#define XLPD_XPPU_IMR_APER_PARITY_SHIFT 7UL
#define XLPD_XPPU_IMR_APER_PARITY_WIDTH 1UL
#define XLPD_XPPU_IMR_APER_PARITY_MASK 0x00000080UL
#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_APER_TZ_SHIFT 6UL
#define XLPD_XPPU_IMR_APER_TZ_WIDTH 1UL
#define XLPD_XPPU_IMR_APER_TZ_MASK 0x00000040UL
#define XLPD_XPPU_IMR_APER_TZ_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_APER_PERM_SHIFT 5UL
#define XLPD_XPPU_IMR_APER_PERM_WIDTH 1UL
#define XLPD_XPPU_IMR_APER_PERM_MASK 0x00000020UL
#define XLPD_XPPU_IMR_APER_PERM_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_MID_PARITY_SHIFT 3UL
#define XLPD_XPPU_IMR_MID_PARITY_WIDTH 1UL
#define XLPD_XPPU_IMR_MID_PARITY_MASK 0x00000008UL
#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_MID_RO_SHIFT 2UL
#define XLPD_XPPU_IMR_MID_RO_WIDTH 1UL
#define XLPD_XPPU_IMR_MID_RO_MASK 0x00000004UL
#define XLPD_XPPU_IMR_MID_RO_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_MID_MISS_SHIFT 1UL
#define XLPD_XPPU_IMR_MID_MISS_WIDTH 1UL
#define XLPD_XPPU_IMR_MID_MISS_MASK 0x00000002UL
#define XLPD_XPPU_IMR_MID_MISS_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_INV_APB_SHIFT 0UL
#define XLPD_XPPU_IMR_INV_APB_WIDTH 1UL
#define XLPD_XPPU_IMR_INV_APB_MASK 0x00000001UL
#define XLPD_XPPU_IMR_INV_APB_DEFVAL 0x1UL
/**
* Register: XlpdXppuIen
*/
#define XLPD_XPPU_IEN ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL )
#define XLPD_XPPU_IEN_RSTVAL 0x00000000UL
#define XLPD_XPPU_IEN_APER_PARITY_SHIFT 7UL
#define XLPD_XPPU_IEN_APER_PARITY_WIDTH 1UL
#define XLPD_XPPU_IEN_APER_PARITY_MASK 0x00000080UL
#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_APER_TZ_SHIFT 6UL
#define XLPD_XPPU_IEN_APER_TZ_WIDTH 1UL
#define XLPD_XPPU_IEN_APER_TZ_MASK 0x00000040UL
#define XLPD_XPPU_IEN_APER_TZ_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_APER_PERM_SHIFT 5UL
#define XLPD_XPPU_IEN_APER_PERM_WIDTH 1UL
#define XLPD_XPPU_IEN_APER_PERM_MASK 0x00000020UL
#define XLPD_XPPU_IEN_APER_PERM_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_MID_PARITY_SHIFT 3UL
#define XLPD_XPPU_IEN_MID_PARITY_WIDTH 1UL
#define XLPD_XPPU_IEN_MID_PARITY_MASK 0x00000008UL
#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_MID_RO_SHIFT 2UL
#define XLPD_XPPU_IEN_MID_RO_WIDTH 1UL
#define XLPD_XPPU_IEN_MID_RO_MASK 0x00000004UL
#define XLPD_XPPU_IEN_MID_RO_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_MID_MISS_SHIFT 1UL
#define XLPD_XPPU_IEN_MID_MISS_WIDTH 1UL
#define XLPD_XPPU_IEN_MID_MISS_MASK 0x00000002UL
#define XLPD_XPPU_IEN_MID_MISS_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_INV_APB_SHIFT 0UL
#define XLPD_XPPU_IEN_INV_APB_WIDTH 1UL
#define XLPD_XPPU_IEN_INV_APB_MASK 0x00000001UL
#define XLPD_XPPU_IEN_INV_APB_DEFVAL 0x0UL
/**
* Register: XlpdXppuIds
*/
#define XLPD_XPPU_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL )
#define XLPD_XPPU_IDS_RSTVAL 0x00000000UL
#define XLPD_XPPU_IDS_APER_PARITY_SHIFT 7UL
#define XLPD_XPPU_IDS_APER_PARITY_WIDTH 1UL
#define XLPD_XPPU_IDS_APER_PARITY_MASK 0x00000080UL
#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_APER_TZ_SHIFT 6UL
#define XLPD_XPPU_IDS_APER_TZ_WIDTH 1UL
#define XLPD_XPPU_IDS_APER_TZ_MASK 0x00000040UL
#define XLPD_XPPU_IDS_APER_TZ_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_APER_PERM_SHIFT 5UL
#define XLPD_XPPU_IDS_APER_PERM_WIDTH 1UL
#define XLPD_XPPU_IDS_APER_PERM_MASK 0x00000020UL
#define XLPD_XPPU_IDS_APER_PERM_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_MID_PARITY_SHIFT 3UL
#define XLPD_XPPU_IDS_MID_PARITY_WIDTH 1UL
#define XLPD_XPPU_IDS_MID_PARITY_MASK 0x00000008UL
#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_MID_RO_SHIFT 2UL
#define XLPD_XPPU_IDS_MID_RO_WIDTH 1UL
#define XLPD_XPPU_IDS_MID_RO_MASK 0x00000004UL
#define XLPD_XPPU_IDS_MID_RO_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_MID_MISS_SHIFT 1UL
#define XLPD_XPPU_IDS_MID_MISS_WIDTH 1UL
#define XLPD_XPPU_IDS_MID_MISS_MASK 0x00000002UL
#define XLPD_XPPU_IDS_MID_MISS_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_INV_APB_SHIFT 0UL
#define XLPD_XPPU_IDS_INV_APB_WIDTH 1UL
#define XLPD_XPPU_IDS_INV_APB_MASK 0x00000001UL
#define XLPD_XPPU_IDS_INV_APB_DEFVAL 0x0UL
/**
* Register: XlpdXppuMMstrIds
*/
#define XLPD_XPPU_M_MSTR_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL )
#define XLPD_XPPU_M_MSTR_IDS_RSTVAL 0x00000014UL
#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT 0UL
#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH 32UL
#define XLPD_XPPU_M_MSTR_IDS_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL 0x14UL
/**
* Register: XlpdXppuMAperture32b
*/
#define XLPD_XPPU_M_APERTURE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL )
#define XLPD_XPPU_M_APERTURE_32B_RSTVAL 0x00000080UL
#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT 0UL
#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH 32UL
#define XLPD_XPPU_M_APERTURE_32B_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL 0x80UL
/**
* Register: XlpdXppuMAperture64kb
*/
#define XLPD_XPPU_M_APERTURE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL )
#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL 0x00000100UL
#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT 0UL
#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH 32UL
#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL 0x100UL
/**
* Register: XlpdXppuMAperture1mb
*/
#define XLPD_XPPU_M_APERTURE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL )
#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL 0x00000010UL
#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT 0UL
#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH 32UL
#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL 0x10UL
/**
* Register: XlpdXppuMAperture512mb
*/
#define XLPD_XPPU_M_APERTURE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL )
#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL 0x00000001UL
#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT 0UL
#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH 32UL
#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL 0x1UL
/**
* Register: XlpdXppuBase32b
*/
#define XLPD_XPPU_BASE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL )
#define XLPD_XPPU_BASE_32B_RSTVAL 0xff990000UL
#define XLPD_XPPU_BASE_32B_ADDR_SHIFT 0UL
#define XLPD_XPPU_BASE_32B_ADDR_WIDTH 32UL
#define XLPD_XPPU_BASE_32B_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL 0xff990000UL
/**
* Register: XlpdXppuBase64kb
*/
#define XLPD_XPPU_BASE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL )
#define XLPD_XPPU_BASE_64KB_RSTVAL 0xff000000UL
#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT 0UL
#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH 32UL
#define XLPD_XPPU_BASE_64KB_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL 0xff000000UL
/**
* Register: XlpdXppuBase1mb
*/
#define XLPD_XPPU_BASE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL )
#define XLPD_XPPU_BASE_1MB_RSTVAL 0xfe000000UL
#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT 0UL
#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH 32UL
#define XLPD_XPPU_BASE_1MB_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL 0xfe000000UL
/**
* Register: XlpdXppuBase512mb
*/
#define XLPD_XPPU_BASE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL )
#define XLPD_XPPU_BASE_512MB_RSTVAL 0xc0000000UL
#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT 0UL
#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH 32UL
#define XLPD_XPPU_BASE_512MB_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL 0xc0000000UL
/**
* Register: XlpdXppuMstrId00
*/
#define XLPD_XPPU_MSTR_ID00 ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL )
#define XLPD_XPPU_MSTR_ID00_RSTVAL 0x83ff0040UL
#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID00_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID00_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID00_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL 0x3ffUL
#define XLPD_XPPU_MSTR_ID00_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID00_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID00_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL 0x40UL
/**
* Register: XlpdXppuMstrId01
*/
#define XLPD_XPPU_MSTR_ID01 ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL )
#define XLPD_XPPU_MSTR_ID01_RSTVAL 0x03f00000UL
#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID01_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID01_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID01_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL 0x3f0UL
#define XLPD_XPPU_MSTR_ID01_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID01_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID01_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId02
*/
#define XLPD_XPPU_MSTR_ID02 ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL )
#define XLPD_XPPU_MSTR_ID02_RSTVAL 0x83f00010UL
#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID02_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID02_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID02_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL 0x3f0UL
#define XLPD_XPPU_MSTR_ID02_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID02_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID02_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL 0x10UL
/**
* Register: XlpdXppuMstrId03
*/
#define XLPD_XPPU_MSTR_ID03 ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL )
#define XLPD_XPPU_MSTR_ID03_RSTVAL 0x83c00080UL
#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID03_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID03_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID03_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL 0x3c0UL
#define XLPD_XPPU_MSTR_ID03_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID03_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID03_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL 0x80UL
/**
* Register: XlpdXppuMstrId04
*/
#define XLPD_XPPU_MSTR_ID04 ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL )
#define XLPD_XPPU_MSTR_ID04_RSTVAL 0x83c30080UL
#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID04_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID04_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID04_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL 0x3c3UL
#define XLPD_XPPU_MSTR_ID04_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID04_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID04_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL 0x80UL
/**
* Register: XlpdXppuMstrId05
*/
#define XLPD_XPPU_MSTR_ID05 ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL )
#define XLPD_XPPU_MSTR_ID05_RSTVAL 0x03c30081UL
#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID05_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID05_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID05_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL 0x3c3UL
#define XLPD_XPPU_MSTR_ID05_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID05_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID05_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL 0x81UL
/**
* Register: XlpdXppuMstrId06
*/
#define XLPD_XPPU_MSTR_ID06 ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL )
#define XLPD_XPPU_MSTR_ID06_RSTVAL 0x03c30082UL
#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID06_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID06_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID06_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL 0x3c3UL
#define XLPD_XPPU_MSTR_ID06_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID06_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID06_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL 0x82UL
/**
* Register: XlpdXppuMstrId07
*/
#define XLPD_XPPU_MSTR_ID07 ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL )
#define XLPD_XPPU_MSTR_ID07_RSTVAL 0x83c30083UL
#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID07_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID07_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID07_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL 0x3c3UL
#define XLPD_XPPU_MSTR_ID07_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID07_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID07_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL 0x83UL
/**
* Register: XlpdXppuMstrId08
*/
#define XLPD_XPPU_MSTR_ID08 ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL )
#define XLPD_XPPU_MSTR_ID08_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID08_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID08_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID08_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID08_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID08_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID08_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId09
*/
#define XLPD_XPPU_MSTR_ID09 ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL )
#define XLPD_XPPU_MSTR_ID09_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID09_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID09_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID09_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID09_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID09_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID09_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId10
*/
#define XLPD_XPPU_MSTR_ID10 ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL )
#define XLPD_XPPU_MSTR_ID10_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID10_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID10_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID10_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID10_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID10_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID10_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId11
*/
#define XLPD_XPPU_MSTR_ID11 ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL )
#define XLPD_XPPU_MSTR_ID11_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID11_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID11_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID11_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID11_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID11_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID11_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId12
*/
#define XLPD_XPPU_MSTR_ID12 ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL )
#define XLPD_XPPU_MSTR_ID12_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID12_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID12_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID12_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID12_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID12_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID12_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId13
*/
#define XLPD_XPPU_MSTR_ID13 ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL )
#define XLPD_XPPU_MSTR_ID13_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID13_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID13_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID13_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID13_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID13_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID13_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId14
*/
#define XLPD_XPPU_MSTR_ID14 ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL )
#define XLPD_XPPU_MSTR_ID14_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID14_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID14_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID14_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID14_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID14_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID14_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId15
*/
#define XLPD_XPPU_MSTR_ID15 ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL )
#define XLPD_XPPU_MSTR_ID15_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID15_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID15_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID15_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID15_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID15_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID15_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId16
*/
#define XLPD_XPPU_MSTR_ID16 ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL )
#define XLPD_XPPU_MSTR_ID16_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID16_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID16_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID16_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID16_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID16_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID16_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId17
*/
#define XLPD_XPPU_MSTR_ID17 ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL )
#define XLPD_XPPU_MSTR_ID17_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID17_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID17_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID17_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID17_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID17_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID17_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId18
*/
#define XLPD_XPPU_MSTR_ID18 ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL )
#define XLPD_XPPU_MSTR_ID18_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID18_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID18_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID18_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID18_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID18_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID18_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId19
*/
#define XLPD_XPPU_MSTR_ID19 ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL )
#define XLPD_XPPU_MSTR_ID19_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID19_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID19_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID19_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID19_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID19_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID19_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XLPD_XPPU_H__ */

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/* ### HEADER ### */
#ifndef __XLPD_XPPU_SINK_H__
#define __XLPD_XPPU_SINK_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XlpdXppuSink Base Address
*/
#define XLPD_XPPU_SINK_BASEADDR 0xFF9C0000UL
/**
* Register: XlpdXppuSinkErrSts
*/
#define XLPD_XPPU_SINK_ERR_STS ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
#define XLPD_XPPU_SINK_ERR_STS_RSTVAL 0x00000000UL
#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT 31UL
#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH 1UL
#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT 0UL
#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH 12UL
#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
/**
* Register: XlpdXppuSinkIsr
*/
#define XLPD_XPPU_SINK_ISR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
#define XLPD_XPPU_SINK_ISR_RSTVAL 0x00000000UL
#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT 0UL
#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH 1UL
#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XlpdXppuSinkImr
*/
#define XLPD_XPPU_SINK_IMR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
#define XLPD_XPPU_SINK_IMR_RSTVAL 0x00000001UL
#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT 0UL
#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH 1UL
#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
/**
* Register: XlpdXppuSinkIer
*/
#define XLPD_XPPU_SINK_IER ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
#define XLPD_XPPU_SINK_IER_RSTVAL 0x00000000UL
#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT 0UL
#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH 1UL
#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XlpdXppuSinkIdr
*/
#define XLPD_XPPU_SINK_IDR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
#define XLPD_XPPU_SINK_IDR_RSTVAL 0x00000000UL
#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT 0UL
#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH 1UL
#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XLPD_XPPU_SINK_H__ */

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lib/bsp/standalone/src/cortexa53/xocm_xmpu_cfg.h Normal file
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317
lib/bsp/standalone/src/cortexa53/xparameters_ps.h Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
*
* This file contains the address definitions for the hard peripherals
* attached to the ARM Cortex A53 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _XPARAMETERS_PS_H_
#define _XPARAMETERS_PS_H_
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID
#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID
#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID
#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID
#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID
#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID
#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID
#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID
#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID
#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for backwards compatibilty
*/
#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
#define XPS_SCU_PERIPH_BASE 0xF9000000U
/* Shared Peripheral Interrupts (SPI) */
/* FIXME */
/*#define XPS_FPGA0_INT_ID 100U */
#define XPS_FPGA1_INT_ID 62U
#define XPS_FPGA2_INT_ID 63U
#define XPS_FPGA3_INT_ID 64U
#define XPS_FPGA4_INT_ID 65U
#define XPS_FPGA5_INT_ID 66U
#define XPS_FPGA6_INT_ID 67U
#define XPS_FPGA7_INT_ID 68U
#define XPS_DMA4_INT_ID 72U
#define XPS_DMA5_INT_ID 73U
#define XPS_DMA6_INT_ID 74U
#define XPS_DMA7_INT_ID 75U
#define XPS_FPGA8_INT_ID 84U
#define XPS_FPGA9_INT_ID 85U
#define XPS_FPGA10_INT_ID 86U
#define XPS_FPGA11_INT_ID 87U
#define XPS_FPGA12_INT_ID 88U
#define XPS_FPGA13_INT_ID 89U
#define XPS_FPGA14_INT_ID 90U
#define XPS_FPGA15_INT_ID 91U
/* Updated Interrupt-IDs */
#define XPS_OCMINTR_INT_ID (10U + 32U)
#define XPS_NAND_INT_ID (14U + 32U)
#define XPS_QSPI_INT_ID (15U + 32U)
#define XPS_GPIO_INT_ID (16U + 32U)
#define XPS_I2C0_INT_ID (17U + 32U)
#define XPS_I2C1_INT_ID (18U + 32U)
#define XPS_SPI0_INT_ID (19U + 32U)
#define XPS_SPI1_INT_ID (20U + 32U)
#define XPS_UART0_INT_ID (21U + 32U)
#define XPS_UART1_INT_ID (22U + 32U)
#define XPS_CAN0_INT_ID (23U + 32U)
#define XPS_CAN1_INT_ID (24U + 32U)
#define XPS_WDT_INT_ID (52U + 32U)
#define XPS_TTC0_0_INT_ID (36U + 32U)
#define XPS_TTC0_1_INT_ID (37U + 32U)
#define XPS_TTC0_2_INT_ID (38U + 32U)
#define XPS_TTC1_0_INT_ID (39U + 32U)
#define XPS_TTC1_1_INT_ID (40U + 32U)
#define XPS_TTC1_2_INT_ID (41U + 32U)
#define XPS_TTC2_0_INT_ID (42U + 32U)
#define XPS_TTC2_1_INT_ID (43U + 32U)
#define XPS_TTC2_2_INT_ID (44U + 32U)
#define XPS_TTC3_0_INT_ID (45U + 32U)
#define XPS_TTC3_1_INT_ID (46U + 32U)
#define XPS_TTC3_2_INT_ID (47U + 32U)
#define XPS_SDIO0_INT_ID (48U + 32U)
#define XPS_SDIO1_INT_ID (49U + 32U)
#define XPS_GEM0_INT_ID (57U + 32U)
#define XPS_GEM0_WAKE_INT_ID (58U + 32U)
#define XPS_GEM1_INT_ID (59U + 32U)
#define XPS_GEM1_WAKE_INT_ID (60U + 32U)
#define XPS_GEM2_INT_ID (61U + 32U)
#define XPS_GEM2_WAKE_INT_ID (62U + 32U)
#define XPS_GEM3_INT_ID (63U + 32U)
#define XPS_GEM3_WAKE_INT_ID (64U + 32U)
#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U)
#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U)
#define XPS_ADMA_CH0_INT_ID (77U + 32U)
#define XPS_ADMA_CH1_INT_ID (78U + 32U)
#define XPS_ADMA_CH2_INT_ID (79U + 32U)
#define XPS_ADMA_CH3_INT_ID (80U + 32U)
#define XPS_ADMA_CH4_INT_ID (81U + 32U)
#define XPS_ADMA_CH5_INT_ID (82U + 32U)
#define XPS_ADMA_CH6_INT_ID (83U + 32U)
#define XPS_ADMA_CH7_INT_ID (84U + 32U)
#define XPS_CSU_DMA_INT_ID (86U + 32U)
#define XPS_XMPU_LPD_INT_ID (88U + 32U)
#define XPS_ZDMA_CH0_INT_ID (124U + 32U)
#define XPS_ZDMA_CH1_INT_ID (125U + 32U)
#define XPS_ZDMA_CH2_INT_ID (126U + 32U)
#define XPS_ZDMA_CH3_INT_ID (127U + 32U)
#define XPS_ZDMA_CH4_INT_ID (128U + 32U)
#define XPS_ZDMA_CH5_INT_ID (129U + 32U)
#define XPS_ZDMA_CH6_INT_ID (130U + 32U)
#define XPS_ZDMA_CH7_INT_ID (131U + 32U)
#define XPS_XMPU_FPD_INT_ID (134U + 32U)
#define XPS_FPD_CCI_INT_ID (154U + 32U)
#define XPS_FPD_SMMU_INT_ID (155U + 32U)
/* Private Peripheral Interrupts (PPI) */
/*#define XPS_GLOBAL_TMR_INT_ID 27 SCU Global Timer interrupt */
/*#define XPS_FIQ_INT_ID 28 FIQ from FPGA fabric */
/*#define XPS_SCU_TMR_INT_ID 29 SCU Private Timer interrupt */
/*#define XPS_SCU_WDT_INT_ID 30 SCU Private WDT interrupt */
/*#define XPS_IRQ_INT_ID 31 IRQ from FPGA fabric */
/* REDEFINES for TEST APP */
/* Definitions for UART */
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID
#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_XADCPS_NUM_INSTANCES 1U
#define XPAR_XADCPS_0_DEVICE_ID 0U
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibilty */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
#endif
#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
#endif
#define XPAR_SCUTIMER_DEVICE_ID 0U
#define XPAR_SCUWDT_DEVICE_ID 0U
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpseudo_asm.h
*
* This header file contains macros for using inline assembler code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
#ifndef XPSEUDO_ASM_H
#define XPSEUDO_ASM_H
#include "xreg_cortexa53.h"
#include "xpseudo_asm_gcc.h"
#endif /* XPSEUDO_ASM_H */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xreg_cortexa53.h
*
* This header file contains definitions for using inline assembler code. It is
* written specifically for the GNU compiler.
*
* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along
* with the positions of the bits within the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
#ifndef XREG_CORTEXA53_H
#define XREG_CORTEXA53_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* GPRs */
#define XREG_GPR0 x0
#define XREG_GPR1 x1
#define XREG_GPR2 x2
#define XREG_GPR3 x3
#define XREG_GPR4 x4
#define XREG_GPR5 x5
#define XREG_GPR6 x6
#define XREG_GPR7 x7
#define XREG_GPR8 x8
#define XREG_GPR9 x9
#define XREG_GPR10 x10
#define XREG_GPR11 x11
#define XREG_GPR12 x12
#define XREG_GPR13 x13
#define XREG_GPR14 x14
#define XREG_GPR15 x15
#define XREG_GPR16 x16
#define XREG_GPR17 x17
#define XREG_GPR18 x18
#define XREG_GPR19 x19
#define XREG_GPR20 x20
#define XREG_GPR21 x21
#define XREG_GPR22 x22
#define XREG_GPR23 x23
#define XREG_GPR24 x24
#define XREG_GPR25 x25
#define XREG_GPR26 x26
#define XREG_GPR27 x27
#define XREG_GPR28 x28
#define XREG_GPR29 x29
#define XREG_GPR30 x30
#define XREG_CPSR cpsr
/* Current Processor Status Register (CPSR) Bits */
#define XREG_CPSR_MODE_BITS 0x1F
#define XREG_CPSR_EL3h_MODE 0xD
#define XREG_CPSR_EL3t_MODE 0xC
#define XREG_CPSR_EL2h_MODE 0x9
#define XREG_CPSR_EL2t_MODE 0x8
#define XREG_CPSR_EL1h_MODE 0x5
#define XREG_CPSR_EL1t_MODE 0x4
#define XREG_CPSR_EL0t_MODE 0x0
#define XREG_CPSR_IRQ_ENABLE 0x80
#define XREG_CPSR_FIQ_ENABLE 0x40
#define XREG_CPSR_N_BIT 0x80000000U
#define XREG_CPSR_Z_BIT 0x40000000U
#define XREG_CPSR_C_BIT 0x20000000U
#define XREG_CPSR_V_BIT 0x10000000U
/* FPSID bits */
#define XREG_FPSID_IMPLEMENTER_BIT (24U)
#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT)
#define XREG_FPSID_SOFTWARE (0X00000001U<<23U)
#define XREG_FPSID_ARCH_BIT (16U)
#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT)
#define XREG_FPSID_PART_BIT (8U)
#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT)
#define XREG_FPSID_VARIANT_BIT (4U)
#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT)
#define XREG_FPSID_REV_BIT (0U)
#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT)
/* FPSCR bits */
#define XREG_FPSCR_N_BIT (0X00000001U << 31U)
#define XREG_FPSCR_Z_BIT (0X00000001U << 30U)
#define XREG_FPSCR_C_BIT (0X00000001U << 29U)
#define XREG_FPSCR_V_BIT (0X00000001U << 28U)
#define XREG_FPSCR_QC (0X00000001U << 27U)
#define XREG_FPSCR_AHP (0X00000001U << 26U)
#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U)
#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U)
#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U)
#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U)
#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U)
#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U)
#define XREG_FPSCR_RMODE_BIT (22U)
#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT)
#define XREG_FPSCR_STRIDE_BIT (20U)
#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT)
#define XREG_FPSCR_LENGTH_BIT (16U)
#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT)
#define XREG_FPSCR_IDC (0X00000001U << 7U)
#define XREG_FPSCR_IXC (0X00000001U << 4U)
#define XREG_FPSCR_UFC (0X00000001U << 3U)
#define XREG_FPSCR_OFC (0X00000001U << 2U)
#define XREG_FPSCR_DZC (0X00000001U << 1U)
#define XREG_FPSCR_IOC (0X00000001U << 0U)
/* MVFR0 bits */
#define XREG_MVFR0_RMODE_BIT (28U)
#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT)
#define XREG_MVFR0_SHORT_VEC_BIT (24U)
#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
#define XREG_MVFR0_SQRT_BIT (20U)
#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT)
#define XREG_MVFR0_DIVIDE_BIT (16U)
#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
#define XREG_MVFR0_EXEC_TRAP_BIT (0X00000012U)
#define XREG_MVFR0_EXEC_TRAP_MASK (0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
#define XREG_MVFR0_DP_BIT (8U)
#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT)
#define XREG_MVFR0_SP_BIT (4U)
#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT)
#define XREG_MVFR0_A_SIMD_BIT (0U)
#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT)
/* FPEXC bits */
#define XREG_FPEXC_EX (0X00000001U << 31U)
#define XREG_FPEXC_EN (0X00000001U << 30U)
#define XREG_FPEXC_DEX (0X00000001U << 29U)
#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U)
#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U)
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XREG_CORTEXA53_H */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xstatus.h
*
* This file contains Xilinx software status codes. Status codes have their
* own data type called int. These codes are used throughout the Xilinx
* device drivers.
*
******************************************************************************/
#ifndef XSTATUS_H /* prevent circular inclusions */
#define XSTATUS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/*********************** Common statuses 0 - 500 *****************************/
#define XST_SUCCESS 0L
#define XST_FAILURE 1L
#define XST_DEVICE_NOT_FOUND 2L
#define XST_DEVICE_BLOCK_NOT_FOUND 3L
#define XST_INVALID_VERSION 4L
#define XST_DEVICE_IS_STARTED 5L
#define XST_DEVICE_IS_STOPPED 6L
#define XST_FIFO_ERROR 7L /* an error occurred during an
operation with a FIFO such as
an underrun or overrun, this
error requires the device to
be reset */
#define XST_RESET_ERROR 8L /* an error occurred which requires
the device to be reset */
#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
typically requires the device
using the DMA to be reset */
#define XST_NOT_POLLED 10L /* the device is not configured for
polled mode operation */
#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
the specified data into */
#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
to hold the expected data */
#define XST_NO_DATA 13L /* there was no data available */
#define XST_REGISTER_ERROR 14L /* a register did not contain the
expected value */
#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
into the function */
#define XST_NOT_SGDMA 16L /* the device is not configured for
scatter-gather DMA operation */
#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
#define XST_NO_CALLBACK 18L /* a callback has not yet been
registered */
#define XST_NO_FEATURE 19L /* device is not configured with
the requested feature */
#define XST_NOT_INTERRUPT 20L /* device is not configured for
interrupt mode operation */
#define XST_DEVICE_BUSY 21L /* device is busy */
#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
have maxed out */
#define XST_IS_STARTED 23L /* used when part of device is
already started i.e.
sub channel */
#define XST_IS_STOPPED 24L /* used when part of device is
already stopped i.e.
sub channel */
#define XST_DATA_LOST 26L /* driver defined error */
#define XST_RECV_ERROR 27L /* generic receive error */
#define XST_SEND_ERROR 28L /* generic transmit error */
#define XST_NOT_ENABLED 29L /* a requested service is not
available because it has not
been enabled */
/***************** Utility Component statuses 401 - 500 *********************/
#define XST_MEMTEST_FAILED 401L /* memory test failed */
/***************** Common Components statuses 501 - 1000 *********************/
/********************* Packet Fifo statuses 501 - 510 ************************/
#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
was invalid after reset */
#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
* empty and full simultaneously
*/
/************************** DMA statuses 511 - 530 ***************************/
#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
failed */
#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
was invalid after reset */
#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
no buffer descriptors ready
to be processed */
#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
the scatter gather list are
being used */
#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
descriptor which is to be
copied over in the scatter
list is locked */
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
put into the scatter gather
list to be commited */
#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
specified was larger than the
total # of buffer descriptors
in the scatter gather list */
#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
already been created */
#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
been created */
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
being started was not committed
to the list */
#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
has already been used by the
hardware so it can't be reused
*/
#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
error */
#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
error */
/************************** IPIF statuses 531 - 550 ***************************/
#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
was passed into the function */
#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
reset was not valid */
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
status register did not read
back correctly */
#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
register did not reset when
acked */
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
register was not updated when
other registers changed */
#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
status register did not read
back correctly */
#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
did not reset when acked */
#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
not updated correctly when other
registers changed */
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
register did not indicate the
expected value */
#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
did not indicate the expected
value */
#define XST_IPIF_ERROR 541L /* generic ipif error */
/****************** Device specific statuses 1001 - 4095 *********************/
/********************* Ethernet statuses 1001 - 1050 *************************/
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
* to hold the minimum number of
* buffers or descriptors */
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
* collision on polled send */
/*********************** UART statuses 1051 - 1075 ***************************/
#define XST_UART
#define XST_UART_INIT_ERROR 1051L
#define XST_UART_START_ERROR 1052L
#define XST_UART_CONFIG_ERROR 1053L
#define XST_UART_TEST_FAIL 1054L
#define XST_UART_BAUD_ERROR 1055L
#define XST_UART_BAUD_RANGE 1056L
/************************ IIC statuses 1076 - 1100 ***************************/
#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
/* general call address */
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
/* value after reset not valid */
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
/* value after reset not valid */
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
/* value after reset not valid */
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
/* value after reset not valid */
#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
/* didn't return value written */
#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
/* didn't return value written */
#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
/* didn't return written value */
#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
/*********************** ATMC statuses 1101 - 1125 ***************************/
#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
controller hit the max value
which requires the statistics
to be cleared */
/*********************** Flash statuses 1126 - 1150 **************************/
#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
*/
#define XST_FLASH_READY 1127L /* Flash is ready for commands */
#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
error. Use XFlash_DeviceControl
to retrieve device specific codes
*/
#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
*/
#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
*/
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
driver */
#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
aborted due to a timeout */
#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
addressible range */
#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
write/erase function with
XFL_NON_BLOCKING_WRITE/ERASE
option cleared */
#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
/*********************** SPI statuses 1151 - 1175 ****************************/
#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
* selected */
#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
*/
#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
* one master assigned to two or more
* priorities, or one master not
* assigned to any priority
*/
#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
* priority levels without first
* suspending the use of priority
* levels
*/
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
* bus parking was not enabled
*/
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
* priority mode to allow the
* priorities to be changed
*/
/************************ Intc statuses 1201 - 1225 **************************/
#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
/********************** TmrCtr statuses 1226 - 1250 **************************/
#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
/********************** WdtTb statuses 1251 - 1275 ***************************/
#define XST_WDTTB_TIMER_FAILED 1251L
/********************** PlbArb statuses 1276 - 1300 **************************/
#define XST_PLBARB_FAIL_SELFTEST 1276L
/********************** Plb2Opb statuses 1301 - 1325 *************************/
#define XST_PLB2OPB_FAIL_SELFTEST 1301L
/********************** Opb2Plb statuses 1326 - 1350 *************************/
#define XST_OPB2PLB_FAIL_SELFTEST 1326L
/********************** SysAce statuses 1351 - 1360 **************************/
#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
/********************** PCI Bridge statuses 1361 - 1375 **********************/
#define XST_PCI_INVALID_ADDRESS 1361L
/********************** FlexRay constants 1400 - 1409 *************************/
#define XST_FR_TX_ERROR 1400
#define XST_FR_TX_BUSY 1401
#define XST_FR_BUF_LOCKED 1402
#define XST_FR_NO_BUF 1403
/****************** USB constants 1410 - 1420 *******************************/
#define XST_USB_ALREADY_CONFIGURED 1410
#define XST_USB_BUF_ALIGN_ERROR 1411
#define XST_USB_NO_DESC_AVAILABLE 1412
#define XST_USB_BUF_TOO_BIG 1413
#define XST_USB_NO_BUF 1414
/****************** HWICAP constants 1421 - 1429 *****************************/
#define XST_HWICAP_WRITE_DONE 1421
/****************** AXI VDMA constants 1430 - 1440 *****************************/
#define XST_VDMA_MISMATCH_ERROR 1430
/*********************** NAND Flash statuses 1441 - 1459 *********************/
#define XST_NAND_BUSY 1441L /* Flash is erasing or
* programming
*/
#define XST_NAND_READY 1442L /* Flash is ready for commands
*/
#define XST_NAND_ERROR 1443L /* Flash had detected an
* internal error.
*/
#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
* driver
*/
#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
*/
#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
* operation aborted due to a
* timeout
*/
#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
* addressible range
*/
#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
*/
#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
* page of the device
*/
#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
*/
#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
*/
/**************************** Type Definitions *******************************/
typedef int XStatus;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xtime_l.c
*
* This file contains low level functions to get/set time from the Global Timer
* register in the ARM Cortex A53 MP core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note None.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xtime_l.h"
#include "xpseudo_asm.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/****************************************************************************
*
* Set the time in the Global Timer Counter Register.
*
* @param Value to be written to the Global Timer Counter Register.
*
* @return None.
*
* @note In multiprocessor environment reference time will reset/lost for
* all processors, when this function called by any one processor.
*
****************************************************************************/
void XTime_SetTime(XTime Xtime_Global)
{
/*As the generic timer of A53 runs constantly time can not be set as desired
so the API is left unimplemented*/
}
/****************************************************************************
*
* Get the time from the Global Timer Counter Register.
*
* @param Pointer to the location to be updated with the time.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XTime_GetTime(XTime *Xtime_Global)
{
*Xtime_Global = mfcp(CNTPCT_EL0);
}

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xtime_l.h
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note None.
*
******************************************************************************/
#ifndef XTIME_H /* prevent circular inclusions */
#define XTIME_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xparameters.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
typedef u64 XTime;
/************************** Constant Definitions *****************************/
/* Global Timer is always clocked at half of the CPU frequency */
#define COUNTS_PER_SECOND 0x007A1200U
#define XIOU_SCNTRS_BASEADDR 0XFF260000U
#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET 0x00000000U
#define XIOU_SCNTRS_FREQ_REG_OFFSET 0x00000020U
#define XIOU_SCNTRS_FREQ 0x02FAF080U /* 50 MHz */
#define XIOU_SCNTRS_CNT_CNTRL_REG_EN 0X00000001U
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void XTime_SetTime(XTime Xtime_Global);
void XTime_GetTime(XTime *Xtime_Global);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XTIME_H */

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void __ARM_argv_veneer(void) {};

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###############################################################################
#
# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
###############################################################################
include config.make
AS=armasm
COMPILER=armcc
ARCHIVER=armar
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
ECC_FLAGS += --cpu=Cortex-A9 --fpu=VFPv3_FP16 --vectorize
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
COBJS = $(addsuffix .o, $(basename $(wildcard *.c)))
AOBJS1 = asm_vectors.o
AOBJS2 = translation_table.o
OBJS = $(COBJS) $(AOBJS1) $(AOBJS2) boot_post.o
ASOURCES1 = asm_vectors.s
ASOURCES2 = translation_table.s
# Replace boot.o with boot_post.o
OBJECTS = $(OBJS)
libs: boot_libs banner $(LIBS)
boot_libs:
ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S)
${COMPILER} $(INCLUDES) -E -o boot_post.s boot.S
endif
${AS} --cpu=Cortex-A9 --fpu=VFPv3 -o boot_post.o boot_post.s
rm -f boot.S
$(AOBJS1): $(ASOURCES1)
${AS} --cpu=Cortex-A9 --fpu=VFPv3 -o $@ $<
$(AOBJS2): $(ASOURCES2)
${AS} --cpu=Cortex-A9 --fpu=VFPv3 -o $@ $<
%.o: %.c
${COMPILER} -c $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
banner:
echo "Compiling standalone"
standalone_libs: ${OBJECTS}
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
.PHONY: include
include: standalone_includes
standalone_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OBJECTS}

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#include "xil_types.h"
/* Stuv for close() sys-call */
__weak s32 _sys_close(s32 fh)
{
return -1;
}

8
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#include "xil_types.h"
/* Stuv for exit() sys-call */
__weak void _sys_exit(s32 rc)
{
while(1) {
;
}
}

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#include "xil_types.h"
/* Stub for iserror() function */
__weak s32 _sys_iserror(s32 status)
{
if(status<0) {
return 1;
}
return 0;
}

7
lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c Normal file
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#include "xil_types.h"
/* Stub for istty sys-call */
__weak s32 _sys_istty(u32* f)
{
/* cannot read/write files */
return 1;
}

6
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#include "xil_types.h"
/* Stub for open sys-call */
__weak s32 _sys_open(const char8* name, s32 openmode)
{
return 0;
}

7
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#include "xil_types.h"
/* Stub for read() sys-call */
__weak s32 _sys_read(u32 fh, u8 *buf, u32 len, s32 mode)
{
/* Return the number of character NOT read */
return len;
}

19
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#include "xil_types.h"
#include "xparameters.h"
__weak s32 _sys_write(u32 fh, const u8 *buf, u32 len, s32 mode)
{
#ifdef STDOUT_BASEADDRESS
u32 volatile *uart_base = (u32 *)STDOUT_BASEADDRESS;
s32 i;
for (i =0; i < len;i++) {
/* wait if TNFUL */
while (*(uart_base + 11U) & (1U << 14U)) {
;
}
*(uart_base + 12U) = buf[i];
}
#endif
return 0;
}

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;******************************************************************************
;
; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in
; all copies or substantial portions of the Software.
;
; Use of the Software is limited solely to applications:
; (a) running on a Xilinx device, or
; (b) that interact with a Xilinx device through a bus or interconnect.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
; SOFTWARE.
;
; Except as contained in this notice, the name of the Xilinx shall not be used
; in advertising or otherwise to promote the sale, use or other dealings in
; this Software without prior written authorization from Xilinx.
;
;*****************************************************************************
;****************************************************************************
;**
; @file asm_vectors.s
;
; This file contains the initial vector table for the Cortex A9 processor
;
; <pre>
; MODIFICATION HISTORY:
;
; Ver Who Date Changes
; ----- ------- -------- ---------------------------------------------------
; 1.00a ecm/sdm 10/20/09 Initial version
; 3.11a asa 9/17/13 Added support for neon.
; 4.00 pkp 01/22/14 Modified return addresses for interrupt
; handlers
; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
; abort and prefetch abort into DataAbortAddr and
; PrefetchAbortAddr for further use to fix CR#854523
;</pre>
;
; @note
;
; None.
;
;****************************************************************************
EXPORT _vector_table
EXPORT IRQHandler
IMPORT _boot
IMPORT _prestart
IMPORT IRQInterrupt
IMPORT FIQInterrupt
IMPORT SWInterrupt
IMPORT DataAbortInterrupt
IMPORT PrefetchAbortInterrupt
IMPORT DataAbortAddr
IMPORT PrefetchAbortAddr
AREA |.vectors|, CODE
REQUIRE8 {TRUE}
PRESERVE8 {TRUE}
ENTRY ; define this as an entry point
_vector_table
B _boot
B Undefined
B SVCHandler
B PrefetchAbortHandler
B DataAbortHandler
NOP ; Placeholder for address exception vector
B IRQHandler
B FIQHandler
IRQHandler ; IRQ vector handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
bl IRQInterrupt ; IRQ vector
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
subs pc, lr, #4 ; adjust return
FIQHandler ; FIQ vector handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
FIQLoop
bl FIQInterrupt ; FIQ vector
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
subs pc, lr, #4 ; adjust return
Undefined ; Undefined handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
b _prestart
movs pc, lr
SVCHandler ; SWI handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
tst r0, #0x20 ; check the T bit
ldrneh r0, [lr,#-2] ; Thumb mode
bicne r0, r0, #0xff00 ; Thumb mode
ldreq r0, [lr,#-4] ; ARM mode
biceq r0, r0, #0xff000000 ; ARM mode
bl SWInterrupt ; SWInterrupt: call C function here
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
movs pc, lr ; adjust return
DataAbortHandler ; Data Abort handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
ldr r0, =DataAbortAddr
sub r1, lr,#8
str r1, [r0] ;Address of instruction causing data abort
bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
subs pc, lr, #8 ; adjust return
PrefetchAbortHandler ; Prefetch Abort handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
ldr r0, =PrefetchAbortAddr
sub r1, lr,#4
str r1, [r0] ;Address of instruction causing prefetch abort
bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
subs pc, lr, #4 ; adjust return
END

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;******************************************************************************
;
; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in
; all copies or substantial portions of the Software.
;
; Use of the Software is limited solely to applications:
; (a) running on a Xilinx device, or
; (b) that interact with a Xilinx device through a bus or interconnect.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
; SOFTWARE.
;
; Except as contained in this notice, the name of the Xilinx shall not be used
; in advertising or otherwise to promote the sale, use or other dealings in
; this Software without prior written authorization from Xilinx.
;
;*****************************************************************************
;****************************************************************************
;**
; @file boot.S
;
; This file contains the initial startup code for the Cortex A9 processor
;
; <pre>
; MODIFICATION HISTORY:
;
; Ver Who Date Changes
; ----- ------- -------- ---------------------------------------------------
; 1.00a ecm/sdm 10/20/09 Initial version
; 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
; 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
; register settings.
; 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
; register settings.
; 3.07a sgd 07/05/12 Updated with reset and start Global Timer
; 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
; initialization of uart smc nor and sram
; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
; MMU is enabled and removed incorrect initialization
; of TLB lockdown register to fix CR#830580
; 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
; caches and TLB, enable MMU and caches, then enable SMP
; bit in ACTLR. L2Cache invalidation and enabling of L2Cache
; is done later.
; </pre>
;
; @note
;
; None.
;
;****************************************************************************
#include "xparameters.h"
#include "xil_errata.h"
#define UART_BAUDRATE 115200
EXPORT _prestart
EXPORT _boot
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
IMPORT |Image$$SPV_STACK$$ZI$$Limit|
IMPORT |Image$$ABORT_STACK$$ZI$$Limit|
IMPORT MMUTable
IMPORT _vector_table
IMPORT __main
IMPORT Xil_ExceptionInit
IMPORT XTime_SetTime
PSS_L2CC_BASE_ADDR EQU 0xF8F02000
PSS_SLCR_BASE_ADDR EQU 0xF8000000
L2CCWay EQU (PSS_L2CC_BASE_ADDR + 0x077C) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)
L2CCSync EQU (PSS_L2CC_BASE_ADDR + 0x0730) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)
L2CCCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0100) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)
L2CCAuxCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0104) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)
L2CCTAGLatReg EQU (PSS_L2CC_BASE_ADDR + 0x0108) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)
L2CCDataLatReg EQU (PSS_L2CC_BASE_ADDR + 0x010C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)
L2CCIntClear EQU (PSS_L2CC_BASE_ADDR + 0x0220) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)
L2CCIntRaw EQU (PSS_L2CC_BASE_ADDR + 0x021C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)
SLCRlockReg EQU (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
SLCRUnlockReg EQU (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
SLCRL2cRamReg EQU (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
SLCRlockKey EQU 0x767B /* SLCR lock key */
SLCRUnlockKey EQU 0xDF0D /* SLCR unlock key */
SLCRL2cRamConfig EQU 0x00020202 /* SLCR L2C ram configuration */
CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU
CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000
L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable
L2CCControl EQU 0x01 ; Enable L2CC
L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM
L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM
FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30)
AREA |.boot|, CODE
PRESERVE8
; this initializes the various processor modes
_prestart
_boot
#if XPAR_CPU_ID==0
; only allow cp0 through
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #0
beq OKToRun
EndlessLoop0
wfe
b EndlessLoop0
#elif XPAR_CPU_ID==1
; only allow cp1 through
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #1
beq OKToRun
EndlessLoop1
wfe
b EndlessLoop1
#endif
OKToRun
mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
and r5, r0, #0x00f00000
and r6, r0, #0x0000000f
orr r6, r6, r5, lsr #20-4
#ifdef CONFIG_ARM_ERRATA_742230
cmp r6, #0x22 /* only present up to r2p2 */
mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orrle r10, r10, #1 << 4 /* set bit #4 */
mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
#ifdef CONFIG_ARM_ERRATA_743622
teq r5, #0x00200000 /* only present in r2p* */
mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orreq r10, r10, #1 << 6 /* set bit #6 */
mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
/* set VBAR to the _vector_table address in scatter file */
ldr r0, =_vector_table
mcr p15, 0, r0, c12, c0, 0
;invalidate scu
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
;Invalidate caches and TLBs
mov r0,#0 ; r0 = 0
mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
bl invalidate_dcache ; invalidate dcache
; Disable MMU, if enabled
mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
bic r0, r0, #0x1 ; clear bit 0
mcr p15, 0, r0, c1, c0, 0 ; write value back
#ifdef SHAREABLE_DDR
; Mark the entire DDR memory as shareable
ldr r3, =0x3ff ; 1024 entries to cover 1G DDR
ldr r0, =TblBase ; MMU Table address in memory
ldr r2, =0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
shareable_loop:
str r2, [r0] ; write the entry to MMU table
add r0, r0, #0x4 ; next entry in the table
add r2, r2, #0x100000 ; next section
subs r3, r3, #1
bge shareable_loop ; loop till 1G is covered
#endif
; In case of AMP, map virtual address 0x20000000 to 0x00000000 and mark it as non-cacheable
#if USE_AMP==1
ldr r3, =0x1ff ; 512 entries to cover 512MB DDR
ldr r0, =TblBase ; MMU Table address in memory
add r0, r0, #0x800 ; Address of entry in MMU table, for 0x20000000
ldr r2, =0x0c02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0
mmu_loop:
str r2, [r0] ; write the entry to MMU table
add r0, r0, #0x4 ; next entry in the table
add r2, r2, #0x100000 ; next section
subs r3, r3, #1
bge mmu_loop ; loop till 512MB is covered
#endif
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the irq stack pointer
and r2, r1, r0
orr r2, r2, #0x12 ; IRQ mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the supervisor stack pointer
and r2, r1, r0
orr r2, r2, #0x13 ; supervisor mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$SPV_STACK$$ZI$$Limit| ; Supervisor stack pointer
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the Abort stack pointer
and r2, r1, r0
orr r2, r2, #0x17 ; Abort mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$ABORT_STACK$$ZI$$Limit| ; Abort stack pointer
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the system stack pointer
and r2, r1, r0
orr r2, r2, #0x1f ; SYS mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer
;set scu enable bit in scu
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
; enable MMU and cache
ldr r0,=MMUTable ; Load MMU translation table base
orr r0, r0, #0x5B ; Outer-cacheable, WB
mcr p15, 0, r0, c2, c0, 0 ; TTB0
mvn r0,#0
mcr p15,0,r0,c3,c0,0
; Enable mmu, icahce and dcache
ldr r0,=CRValMmuCac
mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU
dsb ; dsb allow the MMU to start up
isb ; isb flush prefetch buffer
; Write to ACTLR
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
orr r0, r0, #(0x01 << 6) ; SMP bit
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
; Invalidate L2 Cache and initialize L2 Cache
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
#if USE_AMP!=1
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
mov r1, #0 ; force the disable bit
str r1, [r0] ; disable the L2 Caches
ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
ldr r1,[r0] ; read the register
ldr r2,=L2CCAuxControl ; set the default bits
orr r1,r1,r2
str r1, [r0] ; store the Aux Control Register
ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
str r1, [r0] ; store the TAG Latency register Register
ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
ldr r1,=L2CCDataLatency ; set the latencies for the Data
str r1, [r0] ; store the Data Latency register Register
ldr r0,=L2CCWay ; Load L2CC base address base + way register
ldr r2, =0xFFFF
str r2, [r0] ; force invalidate
ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
; Load L2CC base address base + sync register
; poll for completion
Sync
ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw ; clear pending interrupts
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
ldr r0,=SLCRUnlockReg ;Load SLCR base address base + unlock register
ldr r1,=SLCRUnlockKey ;set unlock key
str r1, [r0] ;Unlock SLCR
ldr r0,=SLCRL2cRamReg ;Load SLCR base address base + l2c Ram Control register
ldr r1,=SLCRL2cRamConfig ;set the configuration value
str r1, [r0] ;store the L2c Ram Control Register
ldr r0,=SLCRlockReg ;Load SLCR base address base + lock register
ldr r1,=SLCRlockKey ;set lock key
str r1, [r0] ;lock SLCR
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
ldr r1,[r0] ; read the register
mov r2, #L2CCControl ; set the enable bit
orr r1,r1,r2
str r1, [r0] ; enable the L2 Caches
#endif
mov r0, r0
mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1
orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11
mcr p15, 0, r1, c1, c0, 2 ; write back into CACR
; enable vfp
fmrx r1, FPEXC ; read the exception register
orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state
fmxr FPEXC, r1 ; write back the exception register
mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable
orr r0, r0, #(0x01 << 11) ; #0x8000
mcr p15,0,r0,c1,c0,0
mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register
orr r0, r0, #(0x1 << 2) ; enable Dside prefetch
orr r0, r0, #(0x1 << 1) ; enable L2 prefetch
mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register
mrs r0, cpsr /* get the current PSR */
bic r0, r0, #0x100 /* enable asynchronous abort exception */
msr cpsr_xsf, r0
; Clear cp15 regs with unknown reset values
mov r0, #0x0
mcr p15, 0, r0, c5, c0, 0 ; DFSR
mcr p15, 0, r0, c5, c0, 1 ; IFSR
mcr p15, 0, r0, c6, c0, 0 ; DFAR
mcr p15, 0, r0, c6, c0, 2 ; IFAR
mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
; Reset and start Cycle Counter
mov r2, #0x80000000 ; clear overflow
mcr p15, 0, r2, c9, c12, 3
mov r2, #0xd ; D, C, E
mcr p15, 0, r2, c9, c12, 0
mov r2, #0x80000000 ; enable cycle counter
mcr p15, 0, r2, c9, c12, 1
; Reset and start Global Timer
mov r0, #0x0
mov r1, #0x0
bl XTime_SetTime
#ifdef PROFILING /* defined in Makefile */
/* Setup profiling stuff */
bl _profile_init
#endif /* PROFILING */
; make sure argc and argv are valid
mov r0, #0
mov r1, #0
b __main ; jump to C startup code
and r0, r0, r0 ; no op
Ldone b Ldone ; Paranoia: we should never get here
; *************************************************************************
; *
; * invalidate_dcache - invalidate the entire d-cache by set/way
; *
; * Note: for Cortex-A9, there is no cp instruction for invalidating
; * the whole D-cache. Need to invalidate each line.
; *
; *************************************************************************
invalidate_dcache
mrc p15, 1, r0, c0, c0, 1 ; read CLIDR
ands r3, r0, #0x7000000
mov r3, r3, lsr #23 ; cache level value (naturally aligned)
beq finished
mov r10, #0 ; start with level 0
loop1
add r2, r10, r10, lsr #1 ; work out 3xcachelevel
mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level
and r1, r1, #7 ; get those 3 bits alone
cmp r1, #2
blt skip ; no cache or only instruction cache at this level
mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
isb ; isb to sync the change to the CacheSizeID reg
mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register
and r2, r1, #7 ; extract the line length field
add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
ldr r4, =0x3ff
ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned)
clz r5, r4 ; r5 is the bit position of the way size increment
ldr r7, =0x7fff
ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned)
loop2
mov r9, r4 ; r9 working copy of the max way size (right aligned)
loop3
orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11
orr r11, r11, r7, lsl r2 ; factor in the index number
mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way
subs r9, r9, #1 ; decrement the way number
bge loop3
subs r7, r7, #1 ; decrement the index
bge loop2
skip
add r10, r10, #2 ; increment the cache number
cmp r3, r10
bgt loop1
finished
mov r10, #0 ; swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
isb
bx lr
END

195
lib/bsp/standalone/src/cortexa9/armcc/translation_table.s Normal file
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@ -0,0 +1,195 @@
;******************************************************************************
;
; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in
; all copies or substantial portions of the Software.
;
; Use of the Software is limited solely to applications:
; (a) running on a Xilinx device, or
; (b) that interact with a Xilinx device through a bus or interconnect.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
; SOFTWARE.
;
; Except as contained in this notice, the name of the Xilinx shall not be used
; in advertising or otherwise to promote the sale, use or other dealings in
; this Software without prior written authorization from Xilinx.
;
;*****************************************************************************
;****************************************************************************
;**
; @file translation_table.s
;
; This file contains the initialization for the MMU table in RAM
; needed by the Cortex A9 processor
;
; <pre>
; MODIFICATION HISTORY:
;
; Ver Who Date Changes
; ----- ---- -------- ---------------------------------------------------
; 1.00a ecm 10/20/09 Initial version
; 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
; instead of strongly-ordered.
; 4.2 pkp 09/02/14 modified translation table entries according to address map
; 4.2 pkp 09/11/14 modified translation table entries to resolve compilation
; error for solving CR#822897
; </pre>
;
; @note
;
; None.
;
;****************************************************************************
EXPORT MMUTable
AREA |.mmu_tbl|,CODE,ALIGN=14
MMUTable
; Each table entry occupies one 32-bit word and there are
; 4096 entries, so the entire table takes up 16KB.
; Each entry covers a 1MB section.
GBLA count
GBLA sect
; 0x00000000 - 0x3ffffff (DDR Cacheable)
count SETA 0
sect SETA 0
WHILE count<0x400
DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
sect SETA sect+0x100000
count SETA count+1
WEND
; 0x40000000 - 0x7fffffff (GpAxi0)
count SETA 0
WHILE count<0x400
DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1
sect SETA sect+0x100000
count SETA count+1
WEND
; 0x80000000 - 0xbfffffff (GpAxi1)
count SETA 0
WHILE count<0x400
DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1w
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xc0000000 - 0xdfffffff (undef)
count SETA 0
WHILE count<0x200
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xe0000000 - 0xe02fffff (IOP dev)
count SETA 0
WHILE count<0x3
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xe0300000 - 0xe0ffffff (undef/reserved)
count SETA 0
WHILE count<0xD
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xe1000000 - 0xe1ffffff (NAND)
count SETA 0
WHILE count<0x10
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xe2000000 - 0xe3ffffff (NOR)
count SETA 0
WHILE count<0x20
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xe4000000 - 0xe5ffffff (SRAM)
count SETA 0
WHILE count<0x20
DCD sect + 0xc0e ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xe6000000 - 0xf7ffffff (reserved)
count SETA 0
WHILE count<0x120
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
; 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
; 1MB, it is not possible to define separate regions for them
; 0xf8000000 - 0xf8ffffff (APB device regs)
count SETA 0
WHILE count<0x10
DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xf9000000 - 0xfbffffff (reserved)
count SETA 0
WHILE count<0x30
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xfc000000 - 0xfdffffff (QSPI)
count SETA 0
WHILE count<0x20
DCD sect + 0xc0a ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xfe000000 - 0xffefffff (reserved)
count SETA 0
WHILE count<0x1F
DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
sect SETA sect+0x100000
count SETA count+1
WEND
; 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
; 1MB, it is not possible to define separate region for it
; 0xfff00000 to 0xfffb0000 (OCM)
count SETA 0
DCD sect + 0x4c0e ; S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1
sect SETA sect+0x100000
END

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